CN117407066A - Method and device for initializing configuration space of PCIE (peripheral component interface express) equipment - Google Patents

Abstract

The embodiment of the application provides a method and a device for initializing a configuration space of PCIE equipment, wherein the method comprises the following steps: when the basic input output system is in a PEI initialization phase in a starting process, a root bridge structure of PCIE equipment is built, wherein the root bridge structure comprises a root bridge structure body array, the root bridge structure body array comprises a first member and a second member, the first member is root bridge information in the PCIE equipment, and the second member is equipment information in the PCIE equipment; and distributing bus resources of the PCIE equipment based on the root bridge structure body array to initialize the configuration space of the PCIE equipment. According to the method and the device, the problem that the initializing of the PCIE equipment cannot be dynamically controlled in the PEI phase in the related technology is solved, and the effects of improving the space resource allocation and the initializing efficiency are achieved.

Description

Method and device for initializing configuration space of PCIE (peripheral component interface express) equipment

Technical Field

The embodiment of the application relates to the field of computers, in particular to a method and a device for initializing a configuration space of PCIE equipment.

Background

Based on the current AMD (Advanced Micro Devices) platform, the startup of the unified extensible firmware interface system (Unified Extensible Firmware Interface, abbreviated as UEFI) follows the UEFI platform initialization standard. UEFI can be divided into 7 phases from power up to power down: SEC (security) security verification- & gt PEI (Pre-EFI Initialization) UEFI Pre-initialization- & gt DXE (Driver Executive Environment) drive execution environment- & gt BDS (Boot Device Select) start device selection- & gt TSL (Transient System Load) operating system loading Pre-stage- & gt RT (Run Time) execution Time- & gt AL (After Life) system disaster recovery stage.

The prior art will perform PCIE (Peripheral Component Interconnect Express) high-speed serial computer expansion bus standard space resource allocation and initialization in the DXE phase, after which we can access and modify the registers of the device. However, the hardware related parts are all completed in the PEI phase, but the PEI phase resources are very limited at present, and only a small amount of initialization is carried out. As the configuration becomes complex, some dynamic implementation of hardware initialization in the PEI phase is required, and at this time, it is required to determine device information in the PCIE configuration space, which is not currently accessible. If the DXE phase is waited to complete the determination, a restart is required to validate the hardware initialization, greatly prolonging the boot time.

Disclosure of Invention

The embodiment of the application provides a method and a device for initializing a configuration space of PCIE equipment, which at least solve the problem that the initialization of the PCIE equipment cannot be dynamically controlled in the PEI phase in the related technology.

According to an embodiment of the present application, there is provided a method for initializing a configuration space of a PCIE device, including: when a Basic Input Output System (BIOS) is in a PEI initialization stage in a starting process, a root bridge structure of PCIE equipment is constructed, wherein the root bridge structure comprises a root bridge structure body array, the root bridge structure body array comprises a first member and a second member, the first member is root bridge information in the PCIE equipment, and the second member is equipment information in the PCIE equipment; and distributing bus resources of the PCIE equipment based on the root bridge structure body number group so as to initialize the configuration space of the PCIE equipment.

In an exemplary embodiment, when the bios is in the PEI initialization phase of the boot process, the root bridge structure of the PCIE device is constructed, including: when the basic input output system is in the initialization phase of the PEI in the starting process, determining the number of processors corresponding to the basic input output system; constructing a bus array based on the number of the processors, wherein the bus array is used for defining basic buses in the PCIE equipment, and a corresponding relation exists between the number of the basic buses and the number of the processors; constructing a structural body array based on an AMD platform by using the foundation bus, wherein the structural body array comprises information of a plurality of members in the AMD platform, and the first member and the second member are respectively contained in the members; the root bridge fabric array is defined in terms of the fabric array.

In one exemplary embodiment, constructing an AMD platform based fabric array using the foundation bus described above includes: traversing the equipment tree of the PCIE equipment by using the equipment threshold value and the function threshold value issued by the base bus and the AMD platform; and constructing the structural body array according to the number of the traversed devices in the device tree, wherein each member in the structural body array is composed of bus information, device information and function information corresponding to the member.

In an exemplary embodiment, after constructing the bus array based on the number of processors, the method further includes: a first cycle is performed to assign a value to the underlying bus in accordance with the number of processors in the bus array.

In an exemplary embodiment, after performing a first cycle to assign a value to the base bus according to the number of processors in the bus array, the method further comprises: a second loop is performed to assign values to the first member and the second member in accordance with the value of the underlying bus.

In an exemplary embodiment, allocating bus resources of the PCIE device based on the root bridge fabric number group to initialize a configuration space of the PCIE device includes: reading the following information of the configuration space of the PCIE equipment according to the root bridge information: main bus information, vendor identification VID, device information DID, field type information; and distributing bus resources of the PCIE equipment based on the information of the configuration space so as to initialize the configuration space of the PCIE equipment.

In an exemplary embodiment, allocating bus resources of the PCIE device based on the information of the configuration space to initialize the configuration space of the PCIE device includes: if the field type information in the information of the configuration space is a first preset value, distributing bus numbers in the bus resources to devices under the root bridge branches in the PCIE device; and when the field type information in the information of the configuration space is a second preset value, reading the equipment information in the PCIE equipment, and distributing the bus number to the equipment in the PCIE equipment according to the equipment information.

According to another embodiment of the present application, there is provided an apparatus for initializing a configuration space of a PCIE device, including: the first construction module is used for constructing a root bridge structure of the PCIE equipment when the basic input output system is in a PEI initialization stage in a starting process, wherein the root bridge structure comprises a root bridge structure array, the root bridge structure array comprises a first member and a second member, the first member is root bridge information in the PCIE equipment, and the second member is equipment information in the PCIE equipment; and the first allocation module is used for allocating bus resources of the PCIE equipment based on the root bridge structure body group so as to initialize the configuration space of the PCIE equipment.

In an exemplary embodiment, the first building block includes: a first determining unit, configured to determine, when the bios is in the PEI initialization phase during a startup process, the number of processors corresponding to the bios; a first construction unit, configured to construct a bus array based on the number of processors, where the bus array is used to define a base bus in the PCIE device, and a correspondence exists between the number of base buses and the number of processors; a second construction unit, configured to construct an array of structures based on an AMD platform using the base bus, where the array of structures includes information of a plurality of members of the AMD platform, and the first member and the second member are included in the plurality of members; and the first definition unit is used for defining the root bridge structure body array according to the structure body array.

In an exemplary embodiment, the second building unit includes: the first traversing subunit is configured to traverse the device tree of the PCIE device by using the device threshold and the function threshold issued by the base bus and the AMD platform; and the first construction subunit is used for constructing the structural body array according to the number of the traversed devices in the device tree, wherein each member in the structural body array is composed of bus information, device information and function information corresponding to the member.

In an exemplary embodiment, the above apparatus further includes: and the first execution module is used for executing a first loop after constructing the bus array based on the number of the processors so as to assign a value to the basic bus according to the number of the processors in the bus array.

In an exemplary embodiment, the apparatus further includes a second execution module configured to execute a first loop to assign values to the first member and the second member according to the values of the underlying bus after assigning values to the underlying bus according to the number of processors in the bus array.

In an exemplary embodiment, the first allocation module includes: the first reading unit reads the following information of the configuration space of the PCIE device according to the root bridge information: main bus information, vendor identification VID, device information DID, field type information; and the first allocation unit is used for allocating bus resources of the PCIE equipment based on the information of the configuration space so as to initialize the configuration space of the PCIE equipment.

In an exemplary embodiment, the first allocation unit includes: a first allocation subunit, configured to allocate, if field type information in the information of the configuration space is a first preset value, a bus number in the bus resource to a device under a root bridge branch in the PCIE device; and the second allocation subunit is configured to read the device information in the PCIE device and allocate the bus number to the device in the PCIE device according to the device information when the field type information in the configuration space is a second preset value.

According to a further embodiment of the present application, there is also provided a computer readable storage medium having stored therein a computer program, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.

According to a further embodiment of the present application, there is also provided an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.

According to the method and the device, the root bridge structure of the PCIE equipment is constructed in the PEI initialization stage, and resource allocation is carried out on the PCIE configuration space according to the root bridge structure so as to enter the PCIE configuration space in advance, and the register information is read and modified. Compared with the traditional technology, PCIE space resource allocation and initialization are carried out in the DXE stage, the startup time wasted by restarting once to enable correction to be effective can be avoided. Therefore, the problem that the initializing of the PCIE equipment cannot be dynamically controlled in the PEI phase in the related technology can be solved, and the effects of improving the space resource allocation and the initializing efficiency are achieved.

Drawings

Fig. 1 is a hardware block diagram of a server device for initializing a configuration space method of a PCIE device according to an embodiment of the present application;

fig. 2 is a flowchart of a method of initializing a configuration space of a PCIE device according to an embodiment of the present application;

fig. 3 is a flowchart of a method for initializing a configuration space of a PCIE device according to an embodiment of the present application;

fig. 4 is a block diagram of a configuration of an apparatus for initializing a configuration space of a PCIE device according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will be described in detail below with reference to the accompanying drawings in conjunction with the embodiments.

It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.

The method embodiments provided in the embodiments of the present application may be performed in a server device or similar computing device. Taking the operation on the server device as an example, fig. 1 is a hardware structural block diagram of the server device of a method for initializing the configuration space of the PCIE device according to an embodiment of the present application. As shown in fig. 1, the server device may include one or more (only one is shown in fig. 1) processors 102 (the processor 102 may include, but is not limited to, a microprocessor MCU, a programmable logic device FPGA, or the like processing means) and a memory 104 for storing data, wherein the server device may further include a transmission device 106 for communication functions and an input-output device 108. It will be appreciated by those of ordinary skill in the art that the architecture shown in fig. 1 is merely illustrative and is not intended to limit the architecture of the server apparatus described above. For example, the server device may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.

The memory 104 may be used to store a computer program, for example, a software program of an application software and a module, such as a computer program corresponding to a method for initializing a configuration space of a PCIE device in the embodiments of the present application, and the processor 102 executes the computer program stored in the memory 104, thereby performing various functional applications and data processing, that is, implementing the method described above. Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory remotely located with respect to the processor 102, which may be connected to the server device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The transmission device 106 is used to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of a server device. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, simply referred to as NIC) that can connect to other network devices through a base station to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module, which is configured to communicate with the internet wirelessly.

In this embodiment, a method for initializing a configuration space of a PCIE device is provided, and fig. 2 is a flowchart of a method for initializing a configuration space of a PCIE device according to an embodiment of the present application, as shown in fig. 2, where the flowchart includes the following steps:

step S202, when a basic input output system is in a PEI initialization stage in a starting process, a root bridge structure of PCIE equipment is constructed, wherein the root bridge structure comprises a root bridge structure body array, the root bridge structure body array comprises a first member and a second member, the first member is root bridge information in the PCIE equipment, and the second member is equipment information in the PCIE equipment;

step S204, allocating bus resources of the PCIE device based on the root bridge fabric array, so as to initialize a configuration space of the PCIE device.

Optionally, in this embodiment, the basic input output system (Basic Input Output System) is the first software loaded at the start of the host, and the main function is to provide the lowest layer, most direct hardware setup and control for the computer.

Optionally, in the present embodiment, the bus resources include, but are not limited to, bus number.

Optionally, in this embodiment, the configuration space of the PCIE device is divided into a compatible configuration space and an extended configuration space, where the compatible configuration space reserves a configuration space of the PCIE bus, and the extended configuration space is used to support a new function in the PCIE bus.

Through the steps, the root bridge structure of the PCIE device is constructed in the initialization phase of the PEI in the starting process. And distributing bus resources of the PCIE equipment based on the root bridge structure body array, and initializing configuration space of the PCIE equipment. The method solves the problem that the initializing of PCIE equipment cannot be dynamically controlled in the PEI phase in the related technology, and achieves the effect of improving the efficiency of space resource allocation and initializing.

The main execution body of the above steps may be, but not limited to, a server, a terminal, etc.

Optionally, the root bridge information in the PCIE device in the step includes: bus information, device information, function information. The device information in the PCIE device includes: bus information, device information, function information.

In an exemplary embodiment, when the bios is in the PEI initialization phase of the boot process, the root bridge structure of the PCIE device is constructed, including: when the basic input output system is in the initialization phase of the PEI in the starting process, determining the number of processors corresponding to the basic input output system; constructing a bus array based on the number of the processors, wherein the bus array is used for defining basic buses in the PCIE equipment, and a corresponding relation exists between the number of the basic buses and the number of the processors; constructing a structural body array based on an AMD platform by using the foundation bus, wherein the structural body array comprises information of a plurality of members in the AMD platform, and the first member and the second member are respectively contained in the members; the root bridge fabric array is defined in terms of the fabric array.

Optionally, in this embodiment, the number of the base buses is in a proportional relationship with the number of the processors, and the more the number of the processors in place, the more the number of the base buses. The number of members in the bus array indicates the underlying bus number of the processor. For example, if the number of processors is two, two bus arrays need to be constructed: socketnum=1: oneSocketRbBus [ ] and socketnum=2: twoSocketRBus [ ], processor A has 4 members of the bus array A with a base bus number of 4. The fabric array includes all root bridges and devices of the AMD platform, totaling 22 members. In the embodiment, the root bridge structure is created through the bus array, the structure array and the root bridge structure array, so that the aim of integrating all device information in the configuration space of the PCIE device in the PEI phase is fulfilled.

In one exemplary embodiment, constructing an AMD platform based fabric array using the foundation bus described above includes: traversing the equipment tree of the PCIE equipment by using the equipment threshold value and the function threshold value issued by the base bus and the AMD platform; and constructing the structural body array according to the number of the traversed devices in the device tree, wherein each member in the structural body array is composed of bus information, device information and function information corresponding to the member.

Optionally, in this embodiment, the device threshold and the function threshold are determined from a guideline file issued by the AMD platform. For example, the device threshold is [1,5], and the function threshold is [1,7]. The basic bus number of the processor a is 4, the bus array a has 4 members, the structure array comprises all root bridges and devices of the AMD platform, and 22 members in total, and then the structure array which is required to be constructed according to the device tree has bus information, device information and function information corresponding to 88 groups of members. The embodiment realizes the purposes of constructing the resource information of the whole PCIE equipment and facilitating the subsequent uniform distribution of bus resources by traversing the equipment tree and constructing the structure array.

In an exemplary embodiment, after constructing the bus array based on the number of processors, the method further includes: a first cycle is performed to assign a value to the underlying bus in accordance with the number of processors in the bus array.

Alternatively, in this embodiment, for example, if the basic bus number of the processor a is 4, the bus array a: socketnum=onesocketrbbus [ ] has 4 members, busbuf=onesocketrbbus [ i ], i takes a value from 0 to 3, and the basic bus is assigned a value. The embodiment realizes the aim of carrying out branch addressing according to the basic bus information by assigning values to the basic bus.

In an exemplary embodiment, after performing a first cycle to assign a value to the base bus according to the number of processors in the bus array, the method further comprises: a second loop is performed to assign values to the first member and the second member in accordance with the value of the underlying bus.

Optionally, in this embodiment, the root bridge fabric array includes a first member and a second member, each of which is composed of bus information, device information, and function information. For example, mNvmeDiskPath [0], mNvmeDiskPath [1] are the first member and the second member of the root bridge structure array, respectively, mDevFunc [ is the structure array, 22 members in total, each member is composed of bus information, device information, and function information. Firstly, mNvmedikPath [0] Bus is equal to the current basic Bus number, mNvmedikPath [1] Bus is equal to the current basic Bus number +1, then mNvmedikPath [0] Dev=mDevFunc [ j ] Dev;

mvmeDiskPath[0].Fun＝mDevFunc[j].Fun；

mNvmeDiskPath[1].Dev＝mDevFunc[j].Dev+1；

mNvmeDiskPath[1].Fun＝mDevFunc[j].Fun+1。

the embodiment realizes the purpose of quickly initializing the configuration space resources of the PCIE equipment by assigning the values to the members of the root bridge structure array.

In an exemplary embodiment, allocating bus resources of the PCIE device based on the root bridge fabric number group to initialize a configuration space of the PCIE device includes: reading the following information of the configuration space of the PCIE equipment according to the root bridge information: main bus information, vendor identification VID, device information DID, field type information; and distributing bus resources of the PCIE equipment based on the information of the configuration space so as to initialize the configuration space of the PCIE equipment.

Optionally, in this embodiment, the configuration space of the PCIE device includes, but is not limited to: the device ID device information register, the Vendor ID Vendor identification register, and the Header Type field Type register. The embodiment can read the main bus information, the manufacturer identification VID, the device information DID and the field type information through the root bridge information in the root bridge structure. The method and the device achieve the purpose of quickly reading the space resource information of the PCIE device.

In an exemplary embodiment, allocating bus resources of the PCIE device based on the information of the configuration space to initialize the configuration space of the PCIE device includes: if the field type information in the information of the configuration space is a first preset value, distributing bus numbers in the bus resources to devices under the root bridge branches in the PCIE device; and when the field type information in the information of the configuration space is a second preset value, reading the equipment information in the PCIE equipment, and distributing the bus number to the equipment in the PCIE equipment according to the equipment information.

Alternatively, in the present embodiment, the first preset value is 0, and the second preset value is 1. For example, if the field type information read by the root bridge information in the root bridge structure is 0, a Secondary Bus slave Bus number and a sub-Bus lower Bus number need to be allocated to a device under the root bridge branch in the PCIE device. And if the read field type information is 1, the device information in the PCIE device can be read according to manufacturer identification VID/device information DID/class code device classification information. The embodiment realizes the purpose of rapidly distributing the resources of the configuration space of the PCIE equipment through the root bridge information in the root bridge structure.

The invention is illustrated below with reference to specific examples:

fig. 3 is a flowchart of a method for initializing a configuration space of a PCIE device according to an embodiment of the present application, where the number of processors is 2, as shown in fig. 3, including the following steps:

s302, starting to create a root bridge structure;

s304, obtaining the number of processors of the basic input/output system through a FabricResourcInit () function, and assigning the number of processors to SocketNum through a pcd (Platform Configuration Database) global configuration mechanism;

s306, creating a bus array A of the processor A according to the quantity of SocketNum in S304: socketnuma=1: oneSOKETRbBus [ ], wherein bus array A has 4 members in total;

s308, creating a bus array B of the processor B according to the quantity of SocketNum in S304: socketnumb=2: twoSocketRBus [ ], wherein bus array B has a total of 2 members;

s310, assigning a value to a basic bus A according to the bus array A, wherein i=0, 1, 2 and 3;

s312, assigning a value to the basic bus B according to the bus array B, wherein BusBufB=OneCommetRbBus [ i ], and i=0 and 1; s314, a structure array mDevFunc is created, wherein the structure array is composed of 22 members, which cover all root bridges and devices of the AMD platform, and each member is composed of bus information, device information and function information. According to bus threshold values [1,5], function threshold values [1,7] and basic bus numbers, circularly carrying in equipment information and function information, and traversing PCIE equipment tree;

s316, creating a root bridge structure array mNvmeDiskPath [ ], wherein the root bridge structure array has 2 members in total, mNvmeDiskPath [0] and mNvmeDiskPath [1], the first member is root bridge information, the second member is device information, and each member information includes: bus information, device information, function information;

s318, assigning a value to the root bridge structure array according to the structure array, wherein mNvmeDiskPath [0]. Bus is equal to the current basic Bus, mNvmeDiskPath [0]. Dev=mDevFunc [ j ]. Dev;

mNvmeDiskPath[0].Fun＝mDevFunc[j].Fun；mNvmeDiskPath[1].Bus＝BusBuf+1

mNvmeDiskPath[1].Dev＝mDevFunc[j].Dev+1；

mNvmEDISkPath [1] Fun=mDevFunc [ j ] Fun+1; wherein j is from 0 to 21;

s320, the root bridge structure is created, and the root bridge structure is saved: writing mNvmeDiskPath [ ], VIDEO_PARAMETERSDeInfoDevInfo;

s322, transmitting DevInfo into a TempassignBusNumbers () function to initialize a configuration space;

s324, reading manufacturer identification VID and device information DID according to the root bridge structure, wherein the reading success is transferred to S326, and the reading failure is transferred to S332;

s326, reading field type information, and if the field type is 0, turning to S328, and if the field type is 1, turning to S330;

s328, distributing the bus number of the device under the root bridge branch in the PCIE device;

s330, reading equipment information in PCIE equipment;

s332, ending.

When the basic input/output system is in the initialization phase of the PEI in the starting process, a bus array, a structure array and a root bridge structure array are defined, wherein the number of the bus array is equal to that of the CPU, the structure array is composed of 22 members, each member is composed of bus information, equipment information and functional information, and the root bridge structure array is composed of two members; and assigning a root bridge structure array according to the member information in the bus array, and distributing the bus number and the reading configuration space of the equipment according to the root bridge information structure. In this embodiment, there are two bus arrays, bus array A has 4 members and bus array B has 2 members. The structure array is 22 members in total and covers all root bridges and devices of the AMD platform, the root bridge structure array is 2 members in total, the first member is root bridge information, and the second member is device information. When assigning a root bridge structure array according to the structure array, the root bridge structure array needs to be circularly assigned according to the bus arrays A and B. After the assignment is finished, a root bridge structure is established, a manufacturer identification VID and device information DID are read according to the root bridge structure, after the completion of reading, the configuration space of PCIE (peripheral component interface express) equipment can be initialized according to field type information, and if the field type is 0, the bus number of the equipment under the root bridge branch in the PCIE equipment is distributed; and if the field type is 1, reading the device information in the PCIE device.

From the description of the above embodiments, it will be clear to a person skilled in the art that the method according to the above embodiments may be implemented by means of software plus the necessary general hardware platform, but of course also by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk), comprising several instructions for causing a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method described in the embodiments of the present application.

In this embodiment, a device for initializing a configuration space of PCIE device is further provided, and the device is used to implement the foregoing embodiments and preferred embodiments, which are not described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

Fig. 4 is a block diagram of a configuration space initializing device of a PCIE device according to an embodiment of the present application, and as shown in fig. 4, the device includes:

a first construction module 402, configured to construct a root bridge structure of a PCIE device when the bios is in an initialization phase of a boot process PEI, where the root bridge structure includes a root bridge structure array, the root bridge structure array includes a first member and a second member, the first member is root bridge information in the PCIE device, and the second member is device information in the PCIE device;

the first allocation module 404 is configured to allocate bus resources of the PCIE device based on the root bridge fabric number group, so as to initialize a configuration space of the PCIE device.

In an exemplary embodiment, the first building block includes: a first determining unit, configured to determine, when the bios is in the PEI initialization phase during a startup process, the number of processors corresponding to the bios; a first construction unit, configured to construct a bus array based on the number of processors, where the bus array is used to define a base bus in the PCIE device, and a correspondence exists between the number of base buses and the number of processors; a second construction unit, configured to construct an array of structures based on an AMD platform using the base bus, where the array of structures includes information of a plurality of members of the AMD platform, and the first member and the second member are included in the plurality of members; and the first definition unit is used for defining the root bridge structure body array according to the structure body array.

In an exemplary embodiment, the second building unit includes: the first traversing subunit is configured to traverse the device tree of the PCIE device by using the device threshold and the function threshold issued by the base bus and the AMD platform; and the first construction subunit is used for constructing the structural body array according to the number of the traversed devices in the device tree, wherein each member in the structural body array is composed of bus information, device information and function information corresponding to the member.

In an exemplary embodiment, the above apparatus further includes: and the first execution module is used for executing a first loop after constructing the bus array based on the number of the processors so as to assign a value to the basic bus according to the number of the processors in the bus array.

In an exemplary embodiment, the apparatus further includes a second execution module configured to execute a first loop to assign values to the first member and the second member according to the values of the underlying bus after assigning values to the underlying bus according to the number of processors in the bus array.

In an exemplary embodiment, the first allocation module includes: the first reading unit reads the following information of the configuration space of the PCIE device according to the root bridge information: main bus information, vendor identification VID, device information DID, field type information; and the first allocation unit is used for allocating bus resources of the PCIE equipment based on the information of the configuration space so as to initialize the configuration space of the PCIE equipment.

In an exemplary embodiment, the first allocation unit includes: a first allocation subunit, configured to allocate, if field type information in the information of the configuration space is a first preset value, a bus number in the bus resource to a device under a root bridge branch in the PCIE device; and the second allocation subunit is configured to read the device information in the PCIE device and allocate the bus number to the device in the PCIE device according to the device information when the field type information in the configuration space is a second preset value.

It should be noted that each of the above modules may be implemented by software or hardware, and for the latter, it may be implemented by, but not limited to: the modules are all located in the same processor; alternatively, the above modules may be located in different processors in any combination.

Embodiments of the present application also provide a computer readable storage medium having a computer program stored therein, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.

In one exemplary embodiment, the computer readable storage medium may include, but is not limited to: a usb disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing a computer program.

Embodiments of the present application also provide an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.

In an exemplary embodiment, the electronic device may further include a transmission device connected to the processor, and an input/output device connected to the processor.

Specific examples in this embodiment may refer to the examples described in the foregoing embodiments and the exemplary implementation, and this embodiment is not described herein.

It will be appreciated by those skilled in the art that the modules or steps of the application described above may be implemented in a general purpose computing device, they may be concentrated on a single computing device, or distributed across a network of computing devices, they may be implemented in program code executable by computing devices, so that they may be stored in a storage device for execution by computing devices, and in some cases, the steps shown or described may be performed in a different order than that shown or described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple modules or steps of them may be fabricated into a single integrated circuit module. Thus, the present application is not limited to any specific combination of hardware and software.

The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application should be included in the protection scope of the present application.

Claims (10)

1. A method for initializing configuration space of PCIE equipment is characterized in that,

comprising the following steps:

when a Basic Input Output System (BIOS) is in a PEI initialization stage in a starting process, a root bridge structure of PCIE equipment is constructed, wherein the root bridge structure comprises a root bridge structure body array, the root bridge structure body array comprises a first member and a second member, the first member is root bridge information in the PCIE equipment, and the second member is equipment information in the PCIE equipment;

and distributing bus resources of the PCIE equipment based on the root bridge structure body array so as to initialize the configuration space of the PCIE equipment.

2. The method of claim 1, wherein constructing the root bridge structure of the PCIE device when the basic input output system is in the PEI initialization phase of the boot process comprises:

when the basic input output system is in the initialization phase of the PEI in the starting process, determining the number of processors corresponding to the basic input output system;

constructing a bus array based on the number of the processors, wherein the bus array is used for defining basic buses in the PCIE equipment, and a corresponding relation exists between the number of the basic buses and the number of the processors;

constructing an AMD platform-based structure array by utilizing the basic bus, wherein the structure array comprises information of a plurality of members in the AMD platform, and the first member and the second member are respectively included in the members; the root bridge fabric array is defined in terms of the fabric array.

3. The method of claim 2, wherein constructing an AMD platform based fabric array using the base bus comprises:

traversing the equipment tree of the PCIE equipment by utilizing the equipment threshold value and the function threshold value issued by the base bus and the AMD platform;

and constructing the structure body array according to the number of the traversed devices in the device tree, wherein each member in the structure body array is composed of bus information, device information and function information corresponding to the member.

4. The method of claim 2, wherein after constructing a bus array based on the number of processors, the method further comprises:

a first loop is performed to assign a value to the underlying bus in accordance with the number of processors in the bus array.

5. The method of claim 4, wherein after performing a first cycle to assign the base bus as a function of the number of processors in the bus array, the method further comprises:

a second loop is performed to assign values to the first member and the second member in accordance with the value of the underlying bus.

6. The method of claim 1, wherein allocating bus resources of the PCIE device based on the root bridge fabric array to initialize a configuration space of the PCIE device comprises:

reading the following information of the configuration space of the PCIE equipment according to the root bridge information: main bus information, vendor identification VID, device information DID, field type information;

and distributing bus resources of the PCIE equipment based on the information of the configuration space so as to initialize the configuration space of the PCIE equipment.

7. The method of claim 6, wherein allocating bus resources of the PCIE device based on the configuration space information to initialize the configuration space of the PCIE device comprises:

if the field type information in the information of the configuration space is a first preset value, distributing bus numbers in the bus resources for devices under the root bridge branches in the PCIE device;

and reading the equipment information in the PCIE equipment and distributing the bus number to the equipment in the PCIE equipment according to the equipment information under the condition that the field type information in the information of the configuration space is a second preset value.

8. An apparatus for initializing a configuration space of a PCIE device, wherein,

comprising the following steps:

the first construction module is used for constructing a root bridge structure of the PCIE equipment when the basic input output system is in a PEI initialization phase in a starting process, wherein the root bridge structure comprises a root bridge structure array, the root bridge structure array comprises a first member and a second member, the first member is root bridge information in the PCIE equipment, and the second member is equipment information in the PCIE equipment;

and the first allocation module is used for allocating bus resources of the PCIE equipment based on the root bridge structure array so as to initialize the configuration space of the PCIE equipment.

9. A computer-readable storage medium comprising,

the computer readable storage medium has stored therein a computer program, wherein the computer program when executed by a processor realizes the steps of the method as claimed in any of claims 1 to 7.

10. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that,

the processor, when executing the computer program, implements the steps of the method as claimed in any one of claims 1 to 7.