CN117395440A - Arithmetic circuit applied to discrete and inverse discrete sine and cosine transformation - Google Patents

Abstract

An arithmetic circuit applied to discrete and inverse discrete sine and cosine transformation. The high-order operation circuit of the first and second sub operation circuits shifts left the multiplicand, outputs and determines the sign when valid, and then carries out the higher-order number when the corresponding bit is higher, and generates a high-order operation result without taking the left shift of the complement. The least significant bit operation circuit of the first and second sub operation circuits outputs the multiplicand and determines the sign when it is valid, and generates the least significant bit operation result. The first adder adds the total low-order operation result as the polynomial operation result. The third sub-operation circuit outputs the addition number and the determined sign when the third sub-operation circuit is effective, and adds up the two complementary codes to generate a third sub-operation result. The two-complement arithmetic circuit performs logic operation to generate two-complement. The second adder sums up the operation results of each time to generate a total operation result.

Description

Arithmetic circuit applied to discrete and inverse discrete sine and cosine transformation

Technical Field

The present invention relates to an arithmetic technique, and more particularly, to an arithmetic circuit for discrete and inverse discrete sine and cosine transforms.

Background

With the increasing application of multimedia technology in military and civil fields and the continuous development of consumer electronics, video coding technology is a research field of great interest. Video coding technology is the main technology for constructing and playing films, and is the basis of all video applications. Among them, video encoding and decoding processes often require the use of computations applied to discrete and inverse discrete sine-cosine transforms, the complexity of their circuitry is substantial.

Therefore, how to design a new operation circuit applied to discrete and inverse discrete sine and cosine transform to achieve the purpose of fast operation to reduce the circuit delay is a problem to be solved in the industry.

Disclosure of Invention

In view of the above problems, an objective of the present invention is to provide an arithmetic circuit for discrete and inverse discrete cosine transform, which improves the prior art.

The invention includes an arithmetic circuit for discrete and inverse discrete sine cosine transform, comprising: the first and second sub-operation circuits, the third sub-operation circuit, the two-complement operation circuit and the second adder. The first sub-operation circuit and the second sub-operation circuit respectively comprise: a plurality of high-order arithmetic circuits, a lowest-order arithmetic circuit, and a first adder. The high-order operation circuits are respectively configured to selectively shift the multiplicand left by different digits according to the displacement control signals determined by the multipliers to generate displacement multiplicands, output the displacement multiplicands according to the effective levels of the bit effective control signals determined by the multipliers, determine the signs of the displacement multiplicands according to the bit sign control signals determined by the multipliers, and shift the displacement multiplicands by higher numbers without taking the left shift of the complementary codes when the corresponding bit of any high-order operation circuit is higher so as to generate high-order operation results. The least significant bit operation circuit is configured to output the multiplicand only according to the significance level of the least significant bit control signal determined by the multiplier, and determine the sign of the multiplicand according to the least significant bit sign control signal determined by the multiplier, so as to generate a least significant bit operation result. The first adder is configured to add the total bit operation result and the lowest bit operation result as the polynomial operation result. The third sub-operation circuit is configured to output an addend according to the effective level of the sub-effective control signal, determine the sign of the addend according to the sub-symbol control signal, and sum the sign of the addend with the two-complement sum to generate a third sub-operation result. The two-complement arithmetic circuit is configured to perform a preset logic operation on the sign control signals of all bits in the first sub-arithmetic circuit and the second sub-arithmetic circuit and the sign control signal of the lowest bit to generate two-complement codes. The second adder is configured to sum the first and second sub-operation results and the third sub-operation result to generate a total operation result.

The preferred embodiments are described in detail below with reference to the accompanying drawings.

Drawings

FIG. 1 is a block diagram of an arithmetic circuit for discrete and inverse discrete sine-cosine transform according to an embodiment of the present invention;

FIG. 2A is a more detailed block diagram of the first sub-operation circuit according to an embodiment of the present invention;

FIG. 2B is a more detailed block diagram of the second sub-operation circuit according to an embodiment of the present invention; and

FIG. 3 is a block diagram showing a two's complement arithmetic circuit in more detail according to an embodiment of the invention.

Detailed Description

An objective of the present invention is to provide an arithmetic circuit for discrete and inverse discrete sine and cosine transform, which is easy to simplify, is beneficial to circuit synthesis, and has the advantages of reduced time delay caused by two-complement arithmetic, reduced winding complexity, low delay and small area. In addition, the operation circuit avoids extra operation amount caused by zero multiplicand by a zero detection mechanism, and further reduces the power consumption of operation.

Please refer to fig. 1. Fig. 1 shows a block diagram of an arithmetic circuit 1 for discrete and inverse discrete cosine transform according to an embodiment of the present invention. In more detail, the operation circuit 1 may be applied to perform Discrete Sine Transformation (DST), discrete Cosine Transformation (DCT), inverse Discrete Sine Transformation (IDST), and Inverse Discrete Cosine Transformation (IDCT).

The arithmetic circuit 1 includes: a first sub-operation circuit 100, a second sub-operation circuit 120, a third sub-operation circuit 140, a two's complement operation circuit 145, and a second adder 160.

In one embodiment, the video encoding and decoding process often requires computation using discrete and inverse discrete sine-cosine transforms. In the method of performing the above transformation, the following calculation is often required: y= ±x0×a±x1×b±c. Where X0 is the multiplicand of the first order, A is the multiplier of the first order, which is a constant. X1 is the multiplicand of the second term, and B is the multiplier of the second term, which is a constant. C is the input value to be added and subtracted in the previous stage.

Accordingly, the first, second and third sub-operations 100, 120 and 140 respectively correspond to the first, second and third sub-operations (±x0×a), (±x1×b) and (C) of the above expression.

Please refer to fig. 2A at the same time. Fig. 2A shows a more detailed block diagram of the first sub-operation circuit 100 according to an embodiment of the present invention. As described above, the first sub-operation circuit 100 is configured to calculate the first sub ± x0×a, and includes: the high-order arithmetic circuits 102A-102F, the low-order arithmetic circuit 104, and the first adder 106.

The number of the high-order arithmetic circuits 102A-102F in the present embodiment is six, and the structures are different. For example, the high-order arithmetic circuit 102A includes a bit left shift multiplexer 110, a bit output unit 112, a bit exclusive OR gate 114, and a bit left shift unit 116.

The bit left shift multiplexer 110 is configured to selectively shift the multiplicand X0 left by different bits according to the shift control signal SHA0 determined by the multiplier a to generate a shift multiplicand X00.

In one embodiment, the bit left shift multiplexer 110 selectively shifts the multiplicand X0 by 0,1, 2, or 3 bits according to the shift control signal SHA 0. Thus, the shift control signal SHA0 is effectively a two-bit control signal. For example, when the shift control signal SHA0 is 00, 01, 10, and 11, the bit left shift multiplexer 110 shifts the multiplicand X0 by 0,1, 2, or 3 bits, respectively, to output the shift multiplicand X00.

The bit output unit 112 is configured to determine the output of the shift multiplicand X00 according to the bit active control signal SEA0 determined by the multiplier a. In one embodiment, the bit output unit 112 is implemented by an AND gate, and the bit valid control signal SEA0 may have a valid level and a valid level of 0 and 1, respectively.

When the bit active control signal SEA0 is at the inactive level 0, the bit output unit 112 will output the displacement multiplicand X00 as 0 regardless of the value of the displacement multiplicand X00. When the bit-valid control signal SEA0 is at the valid level 1, the bit output unit 112 outputs the value of the shift multiplicand X00.

The bit exclusive-OR gate 114 is configured to determine the sign of the shift multiplicand X00 according to the bit sign control signal SSA0. In one embodiment, the bit sign control signal SSA0 may have a negative sign level and a positive sign level of 1 and 0, respectively.

In one embodiment, the bit sign control signal SSA0 is generated by the bit sign control signal SSA0 'with the original value, AND the bit sign control signal SSA0' is generated by performing exclusive or logic operation with the bit valid control signal SEA0 according to the high-order sign signal SA0 AND the sub-order sign signal SH0 determined by the multiplier a. The sign of the first sub-symbol SH0 is determined. When the first term is positive, the term symbol signal SH0 will be 0, and when the first term is negative, the term symbol signal SH0 will be 1.

In one embodiment, each of the high-order arithmetic circuits 102A-102F further includes a zero detection unit 118. Taking the high-order arithmetic circuit 102A as an example, the zero detection unit 118 is configured to maintain the bit symbol control signal SSA0 at an original value and operate the high-order arithmetic circuit 102A when the zero detection signal ZD is at a non-zero level, and to make the bit symbol control signal SSA0 zero and operate the high-order arithmetic circuit 102A when the zero detection signal ZD is at a zero level. In fig. 2A, the bit symbol control signal SSA0 outputted after being adjusted by the zero detection unit 118 is marked with an asterisk.

In one embodiment, the zero detection signal ZD is generated by performing an or operation on the multiplicand X0 and the multiplicand X0. In more detail, the first sub-operation circuit 100 may further include an or gate 108, and the input ends of the or gates 108 each receive the multiplicand X0 to generate the zero detection signal ZD. When the multiplicand X0 is a non-zero value, the zero detection signal ZD will also be a non-zero value and be at a non-zero level. When the multiplicand X0 is zero, the zero detection signal ZD will be zero and be at zero level.

When the bit sign control signal SSA0 is at the negative level 1, the bit exclusive or gate 114 performs exclusive or logic operation on the displacement multiplicand X00 to output the displacement multiplicand X00 as a negative number. When the bit sign control signal SSA0 is positive level 0, the bit exclusive or gate 114 performs exclusive or logic operation on the displacement multiplicand X00 to output the displacement multiplicand X00 as a positive number. The bit sign control signal SSA0 is further applied by the two-complement computing circuit 145 to compute two-complement.

Since the multiplicand X0 is zero in some cases, it may be necessary to perform a two-by-two complement operation because it is a negative number, resulting in an excessive amount of unnecessary computation and a similar result. Therefore, the zero detection unit 118 sets the bit sign control signal SSA0 to be positive under the condition that the multiplicand X0 is zero, so that the unnecessary calculation amount of the bit exclusive or gate 114 is greatly reduced.

In contrast, if the multiplicand X0 is not zero, the zero detection unit 118 outputs the sign of the multiplicand X0, i.e. the bit sign control signal SSA0, which is one of the positive level 0 or the negative level 1.

The bit left shift unit 116 is configured to shift the bit multiplicand X00 higher by higher numbers at the corresponding bit of the higher order operation circuit 102A without taking the left shift of the complement to generate the higher order operation result XS00. In one embodiment, the high-order arithmetic circuit 102A corresponds to the highest order bit and shifts the shift multiplicand X00 left by 11 bits.

Similarly, the bit left shift multiplexers 110 included in the high-order computing circuits 102B-102F selectively shift the multiplicand X0 by 0,1, 2, or 3 bits according to the shift control signals SHA1-SHA5, respectively, to output the shift multiplicands X01-X05. The bit output units 112 included in the high-order arithmetic circuits 102B-102F determine whether the shift multiplicands X01-X05 are valid for output according to the bit valid control signals SEA1-SEA5, respectively.

The bit exclusive OR gates 114 included in the high-order operation circuits 102B-102F determine the signs of the shift multiplicands X01-X05 according to the bit sign control signals SSA1-SSA5, respectively. The zero detection unit 118 included in the high-order arithmetic circuits 102B-102F determines whether the multiplicand X01-X05 is zero, and further determines whether to output the bit sign control signals SSA1-SSA5 as the original value or zero and operate accordingly.

The higher-order left shift units 116 included in the higher-order arithmetic circuits 102B-102F shift the higher-order shift multiplicand X01-X05 by the higher-order bits corresponding to the higher-order arithmetic circuits 102B-102F, for example, shift the higher-order bits by 9, 7, 5, 3, and 1, respectively, to generate higher-order arithmetic results XS01-XS05.

The lowest-order arithmetic circuit 104 includes: the lowest bit output unit 111 and the lowest bit exclusive-or gate 113.

The least significant bit output unit 111 is configured to determine the output of the multiplicand X0 at the least significant bit control signal SEA6 determined by the multiplier a. In one embodiment, the minimum output unit 111 is implemented by an and gate, and the minimum valid control signal SEA6 may have invalid levels and valid levels of 0 and 1, respectively.

When the least significant control signal SEA6 is at the inactive level 0, the least significant output unit 111 will output the displacement multiplicand X00 as 0 regardless of the value of the displacement multiplicand X0. When the least significant control signal SEA6 is at the significant level 1, the least significant output unit 111 outputs the multiplicand X0.

The lowest exclusive or gate 113 is configured to determine the sign of the multiplicand X0 according to the lowest sign control signal SSA 6. In one embodiment, the lowest-order sign control signal SSA6 may have positive and negative sign levels of 0 and 1, respectively.

In one embodiment, the least significant symbol control signal SSA6 is generated by performing exclusive or logic operation on the least significant symbol signal SA6 and the polynomial symbol signal SH0 determined by the multiplier a.

Therefore, when the lowest sign control signal SSA6 is at the negative level 1, the lowest exclusive or gate 113 performs exclusive or logic operation on the multiplicand X0 to output the multiplicand X0 as a negative number. When the lowest symbol control signal SSA6 is positive 0, the lowest exclusive or gate 113 performs exclusive or logic operation on the multiplicand X0 to output the multiplicand X0 as a positive number. Wherein the least significant sign control signal SSA6 is further applied by the two-complement computing circuit 145 to compute two-complement. The multiplicand X0 with sign output by the least significant exclusive-or gate 113 is used as the least significant operation result XS06.

In one embodiment, the minimum level computing circuit 104 includes a minimum level zero detection unit 109 configured to maintain the minimum level symbol control signal SSA6 at an original value when the zero detection signal ZD is at a non-zero level, and to make the minimum level symbol control signal SSA6 zero and operate accordingly when the zero detection signal ZD is at the zero level.

The first adder 106 is configured to add the total bit operation result XS01-XS05 and the lowest bit operation result XS06 as the term operation result XTA.

In one embodiment, the shift control signals SHA0-SHA5, the bit valid control signals SEA0-SEA5, the high bit sign signals SA0-SA5, the low bit valid control signal SEA6 and the low bit sign signal SA6 are determined by looking up the multiplier table by the multiplier A.

Please refer to table 1. Table 1 shows the contents of the multiplier correspondence table according to an embodiment of the present invention.

TABLE 1

Multiplier A	SEA0-SEA6	SA0-SA6	SHA0-SHA5
				0	0000000	0000000	000000000000
2	0000010	0000000	000000000000
				4	0000010	0000000	000000000001
64	0000100	0000000	000000001100
				87	0001111	0000001	000000010110
75	0001111	0000000	000000010000
				83	0001111	0000001	000000010101
18	0000110	0000000	000000000100
				-83	0001111	0001110	000000010101
36	0000110	0000000	000000001001
				90	0011110	0001100	000000000000

In one embodiment, the multiplier correspondence table shown in Table 1 may be applied to the video coding standard of HEVC/AVS2/VVC/AVS 3. It should be noted that table 1 only lists some values by way of example. In practical applications, the multiplier correspondence table may include more values corresponding to each other, and is not limited to the values listed in table 1.

The first column field corresponds to a value of multiplier a, such as 83 for the seventh row field of the first column. The contents corresponding to the second column field are the contents of the bit valid control signals SEA0-SEA5 and the least significant control signal SEA6, and the number of each field, for example 0001111 corresponding to the fifth row field of the second column, corresponds to the most significant bits to the least significant bits in sequence.

The contents corresponding to the third column field are the contents of the high-order sign signals SA0-SA5 and the low-order sign signal SA6, and the number of each field, for example 0000001 corresponding to the fifth row field of the third column, sequentially corresponds to the signal values from the highest order to the lowest order. The content corresponding to the fourth column field is the content of the shift control signals SHA0-SHA5, and the number of each field, for example 000000010100 corresponding to the fifth row field of the fourth column, corresponds to the signal value from the highest bit to the lowest bit in order every two bits.

Thus, for the example of multiplier A being 83, when X0 is 1, represented as 16 is 0X0001, the bit left shift multiplexers 110 included in the high-order computing circuits 102A-102F are configured to respectively look up the values of the shift control signals SHA0-SHA5 (000000010101), respectively performing displacement of 0,1 and 1 bit, the displacement multiplicand X00-X05 is respectively 0X0001, 0X0002 and 0X0002.

Next, the bit output unit 112 included in the high-order arithmetic circuits 102A to 102F and the low-order output unit 111 included in the low-order arithmetic circuit 104 determine that the displacement multiplicand X00 to X02 is invalid and output 0, and determine that the displacement multiplicand X03 to X06 are valid, based on the values (0001111) of the bit valid control signals SEA0 to SEA5 and the low-order valid control signal SEA6 obtained by table lookup, respectively. Therefore, the bit output units 112 included in the high-order arithmetic circuits 102A to 102F and the low-order output units 111 included in the low-order arithmetic circuit 104 output 0x0000, 0x0002, and 0x0002 and 0x0001, respectively.

Since the multiplicand X0 is not 0, the zero detection unit 118 outputs the bit sign control signals SSA0 to SSA5 maintaining the original values according to the zero detection signal ZD at the non-zero level and causes the high-order arithmetic circuits 102A to 102F to operate accordingly.

The bit exclusive OR gate 114 included in the high-order arithmetic circuits 102A-102F and the least significant exclusive OR gate 113 included in the least significant arithmetic circuit 104 determine the signs of the shift multiplicand X00-X05 and the multiplicand X0 according to the values of the bit symbol control signals SSA0-SSA5 and the least significant symbol control signal SSA6 obtained by table lookup, respectively. More specifically, the values of the bit sign control signals SSA0-SSA5 and the least significant bit sign control signal SSA6 are generated by performing exclusive OR logic operation with the sub-symbol signal SH0 according to the values (0000001) of the high-order sign signals SA0-SA5 and the least significant bit sign signal SA6 obtained by looking up the table.

In the present embodiment, the first term of positive sign makes the term symbol signal SH0 to be 0. Therefore, the values of the bit sign control signals SSA0-SSA5 and the least significant bit sign control signal SSA6 will be (0000001), respectively. The bit exclusive OR gates 114 included in the high-order arithmetic circuits 102A-102F output signed shift multiplicands X00-X05, respectively, of 0X0000, 0X0002, and 0X0002, respectively. The least significant exclusive OR gate 113 included in the least significant arithmetic circuit 104 outputs the multiplicand X0 having a sign to generate the least significant arithmetic result XS06 of 0 xFFFE.

Then, the bit left shifting units 116 included in the high-order computing circuits 102A-102F shift left 11, 9, 7, 5, 3 and 1 bits of the signed shift multiplicand X00-X05, respectively, to generate the high-order computing result XS00-XS05. Since the displacement multiplicand X00-X02 is 0, the high-order operation result XS00-XS02 after the bit left shift is still 0. The displacement multiplicand X03-X05 is 0X0002, 0X0002 and 0X0002 respectively, and the high-order operation result XS03-XS05 generated after the left shift of 5, 3 and 1 bits is 0X0040, 0X0010 and 0X0004 respectively.

The first adder 106 adds the high-order operation result XS00 to XS05 and the low-order operation result XS06 to the term operation result XTA corresponding to ±x0×a. Thus, the term operation result XTA will be 0x0040+0x0010+0x0004+0xfffe=0x0052.

Therefore, the first-term arithmetic circuit 100 can calculate the first term ± x0×a according to the above-described procedure.

Please refer to fig. 2B. FIG. 2B shows a more detailed block diagram of the second sub-operation circuit 120 in an embodiment of the invention.

Similarly, the second sub-operation circuit 120 may have the same structure as the first sub-operation circuit 100, including: the high-order arithmetic circuits 102A-102F, the low-order arithmetic circuit 104, and the first adder 106. Since the structures and the calculation modes of the second sub-operation circuit 120 and the first sub-operation circuit 100 are different, details of the second sub-operation circuit 120 will not be described again.

When the multiplier B is-83, the relevant data is also searched by referring to the numerical value corresponding to 83 in the table 1. If the multiplicand X1 is 1, expressed as 0X0001 in 16 scale, the bit left shift multiplexer 110 included in the high-order arithmetic circuits 102A-102F generates the shift multiplicands X10-X15 of 0X0000, 0X0002, and 0X0002 according to the shift control signals SHB0-SHB5 obtained by table lookup. The bit output units 112 included in the high-order arithmetic circuits 102A-102F and the low-order output units 111 included in the low-order arithmetic circuit 104 output 0x0000, 0x0002, and 0x0002 and 0x0001, respectively.

Since the multiplicand X1 is not 0, the zero detection unit 118 keeps the bit symbol control signals SSB0 to SSB5 at the original value and operates the high-order arithmetic circuits 102A to 102F according to the zero detection signal ZD at the non-zero level. The bit exclusive OR gate 114 included in the high-order arithmetic circuits 102A-102F and the least significant exclusive OR gate 113 included in the least significant arithmetic circuit 104 determine the signs of the shift multiplicands X10-X15 and the multiplicand X1 according to the values of the bit symbol control signals SSB0-SSB5 and the least significant symbol control signal SSB6 obtained by table look-up, respectively. More specifically, the values of the bit sign control signals SSB0-SSB5 and the least significant bit sign control signal SSB6 are generated by performing exclusive OR logic operation with the secondary sign signal SH1 according to the values (0001110) of the high-order sign signals SB0-SB5 and the least significant bit sign signal SB6 obtained by looking up the table.

In the present embodiment, the second term, which is negative, makes the term symbol signal SH1, and the values of the bit symbol control signals SSB0-SSB5 and the least significant bit symbol control signal SSB6 are (1110001), respectively. The bit exclusive OR gates 114 included in the high-order operation circuits 102A-102F output the signed shift multiplicand X10-X15, respectively, 0X0000, 0xFFFD, and 0xFFFD, respectively. The least significant exclusive or gate 113 included in the least significant arithmetic circuit 104 outputs the multiplicand X1 having a sign to generate the least significant arithmetic result XS16 of 0X0001.

Then, the bit left shifting units 116 included in the high-order computing circuits 102A-102F shift left by 11, 9, 7, 5, 3 and 1 bits, respectively, the signed shift multiplicand X10-X15 to generate high-order computing results XS10-XS15, which are 0X0000, 0xFFA0, 0xFFE8 and 0xFFFA, respectively.

The first adder 106 adds the high-order operation results XS10 to XS15 and the low-order operation result XS16 to the term operation result XTB corresponding to ±x1×b. Thus, the term operation result XTB will be: 0x0000+0x0000+0x0000+0xffa0+0xffe8+0xfffa+0x0001=0xff 83= -125.

The third sub-operation circuit 140 includes a sub-output unit 150, a sub-exclusive-OR gate 152, and a third adder 154.

The sub-output unit 150 is configured to determine whether the addend C is valid for output according to the sub-valid control signal SEC. When the term valid control signal SEC is at the invalid level 0, the term output unit 150 will output the addend C as 0 regardless of the value of the addend C. When the term valid control signal SEC is at the valid level 1, the term output unit 150 outputs the value of the addend C.

The term exclusive-OR gate 152 determines the sign of the addend C according to the term sign control signal SSC. In this embodiment, the third term with positive sign makes the term sign control signal SSC be 0, and makes the term exclusive or gate 152 perform exclusive or logic operation, and then outputs the positive addend C. The third term, which is negative, makes the term sign control signal SSC 1, and makes the term exclusive or gate 152 perform exclusive or logic operation, and then outputs the negative addend C.

In one embodiment, the addend C is 0 and the secondary symbol control signal SSC is 0.

The third adder 154 is configured to add the signed addend C to the two-complement sum TC to generate a third term operation result XTC.

Please refer to fig. 3. FIG. 3 shows a more detailed block diagram of the two's complement arithmetic circuit 145 in an embodiment of the invention. The two's complement arithmetic circuit 145 includes a plurality of first logic arithmetic circuits 300A to 300E, a second logic arithmetic circuit 310, and an output circuit 320.

In one embodiment, when the number of high-order arithmetic circuits is N, the number of first logic arithmetic circuits is N-1 to correspond to N-1 high-order arithmetic circuits with the highest order. Taking the embodiment of FIG. 2 as an example, the number of high-order arithmetic circuits 102A-102F is 6. Therefore, the number of the first logic circuits 300A-300E is 5, so as to operate with the higher-order operation circuits 102A-102E corresponding to the 5 highest bits.

Taking the first logic operation circuit 300A as an example, it includes: complement AND gate 330 and complement exclusive OR gate 340. The complement and gate 330 is configured to operate on the bit sign control signals SSA0 and SSB0 corresponding to the high-order operation circuit 102A in the first sub-operation circuit 100 and the second sub-operation circuit 120 to generate an and gate output signal AO0. The complement xor gate 340 is configured to operate on the bit symbol control signals SSA0 and SSB0 corresponding to the high-order operation circuit 102A in the first sub-operation circuit 100 and the second sub-operation circuit 120 to generate the xor gate output signal XO0.

Similarly, the first logic circuits 300B to 300E perform logic operations corresponding to the bit symbol control signals SSA1 to SSA4 and SSB1 to SSB4 corresponding to the high-order operation circuits 102B to 102E, respectively, and generate and gate output signals AO1 to AO4 and exclusive or gate output signals XO1 to XO4, respectively.

In the above example, since the bit sign control signals SSA0 to SSA4 are all 0 and the bit sign control signals SSB0 to SSB4 are 00011, the and gate output signals AO1 to AO4 are all 0 and the exclusive or gate output signals XO1 to XO4 are 00011.

The second logic operation circuit 310 is configured to perform operations corresponding to the upper level operation circuit 102F and the lower level operation circuit 104 having the lowest level in the first sub-operation circuit 100 and the second sub-operation circuit 120, so as to select one of a plurality of preset logic expressions according to the sub-symbol control signal SSC and the lower level symbol control signals SSA6, SSB6, and perform logic operations on the bit symbol control signals SSA5, SSB5 to generate the complement output signal CO.

In one embodiment, the predetermined logic expression is as shown in Table 2:

TABLE 2

SSC、SSA6、SSB6	CO
		000	SSA5&SSB5,SSA5^SSB5,0
001	SSA5&SSB5,SSA5^SSB5,1
		010	SSA5&SSB5,SSA5^SSB5,1
011	SSA5|SSB5,～(SSA5^SSB5),0
		100	SSA5&SSB5,SSA5^SSB5,1
101	SSA5|SSB5,～(SSA5^SSB5),0
		110	SSA5|SSB5,～(SSA5^SSB5),0
111	SSA5|SSB5,～(SSA5^SSB5),1

Wherein the symbol @ is AND logic, the symbol @ is exclusive OR logic, the symbol @ is OR logic, and the symbols @ to @ are NOT logic.

In the above embodiment, the secondary symbol control signal SSC is 0, and the least significant symbol control signals SSA6 and SSB6 are 1 and 0, respectively. Thus, the logic expressions "SSA 5& SSB5, SSA5 SSB5, 1" in Table 2 will be selected to calculate the 3-bit and (0, 1) complement output signal CO.

The output circuit 320 is configured to sum the and gate output signals AO0 to AO4 and the exclusive or gate output signals XO0 to XO4 of the first logic operation circuits 300A to 300E to a value of 2' b0101000, and then add (0, 1) the sum of two complementary codes TC with a value of 0 x2b=43. The third adder 154 is configured to add the signed addend C to the two-complement sum TC to generate a third term operation result XTC. So the equation y= +83×1-83×1+0, scc0=0, tc=gives xtc=43.

The second adder 160 is configured to add the first sub-operation result XTA, the second sub-operation result XTB, and the third sub-operation result XTC of the first sub-operation circuit 100 and the second sub-operation circuit 120 to generate a total operation result Y. It should be noted that, in fig. 1, the second adder 160 is illustrated as a single adder. However, in practical operation, the second adder 160 may be implemented by two adders, one of which sums the first-term operation result XTA and XTB, and the other of which sums the result of the previous adder with the third-term operation result XTC to generate the total operation result Y. The present invention is not limited thereto. Let example y= ±x0×a±x1×b±c= +1×83-1x83+0=0. Wherein xta=0x0052; xtb=0xff 83; xtc=0x2b; y=xta+xtb+xtc=0x0052+0xff83+0x2b=0x0000.

It should be noted that the above embodiments are exemplified by multiplier mapping tables applied to HEVC/AVS2/VVC/AVS3 video coding standards. In other embodiments, the operation circuit 1 of the present invention can also be implemented by using multiplier correspondence tables applied to, for example, but not limited to, VP9 and AV1 video coding standards.

It should be noted that the above embodiment is only an example. In other embodiments, modifications may be made by one of ordinary skill in the art without departing from the spirit of the invention.

In summary, the arithmetic circuit applied to discrete and inverse discrete sine and cosine transformation in the invention is beneficial to circuit synthesis by means of easy simplification, can reduce time delay brought by two-complement arithmetic, can also reduce winding complexity, and has the advantages of low delay and small area. In addition, the operation circuit avoids extra operation amount caused by zero multiplicand by a zero detection mechanism, and further reduces the power consumption of operation.

Although the embodiments of the present disclosure have been described above, these embodiments are not limited thereto, and those skilled in the art can apply the variations of the technical features of the present disclosure according to the explicit or implicit disclosure, and any such variations may fall within the scope of patent protection sought herein, in other words, the scope of patent protection shall be defined by the claims of the present disclosure.

[ symbolic description ]

1: arithmetic circuit

100: first term arithmetic circuit

102A-102F: high-order arithmetic circuit

104: least significant arithmetic circuit

106: first adder

108: OR gate

110: bit left shift multiplexer

111: least significant output unit

112: bit output unit

113: least significant exclusive OR gate

114: bit exclusive OR gate

116: bit left shift unit

118: zero detection unit

120: second term operation circuit

140: third term arithmetic circuit

145: two's complement arithmetic circuit

150: item output unit

152: term-wise exclusive OR gate

154: third adder

160: second adder

300A-300E: first logic operation circuit

310: second logic operation circuit

320: output circuit

330: complement and gate

340: complementary code exclusive OR gate

AO 0-AO 4: and gate output signal

C: additive number

CO: complement output signal

SHA0-SHA5, SHB0-SHB5: displacement control signal

SA0-SA5, SB0-SB5: high-order symbol signal

SA6, SB6: least significant sign signal

SEA0-SEA5, SEB0-SEB5: bit valid control signal

SEA6, SEB6: least significant control signal

SEC: term valid control signal

SH0, SH1: top-order sign signal

SSA0-SSA5, SSB0-SSB5, SSA0'-SSA5', SSB0'-SSB5': bit sign control signal

SSA6, SSB6, SSA6', SSB6': least significant sign control signal

SSC: term sign control signal

TC: taking the sum of two complementary codes

X0, X1: multiplicand

X00-X05, X10-X15: displacement multiplicand

XS00-XS05, XS10-XS15: high-order operation result

XS06, XS16: least significant operation result

XTA, XTB: results of the term operations

XTC: the third operation result

XO0 to XO4: exclusive OR gate output signal

Y: total operation result

ZD: zero detection signal.

Claims (10)

1. An arithmetic circuit for discrete and inverse discrete sine-cosine transform, comprising:

a first sub-operation circuit and a second sub-operation circuit, respectively comprising:

the high-order operation circuits are respectively configured to selectively shift left of different digits on a multiplicand according to a displacement control signal determined by a multiplier to generate a displacement multiplicand, output the displacement multiplicand only according to an effective level of a bit effective control signal determined by the multiplier, determine the sign of the displacement multiplicand according to a bit sign control signal determined by the multiplier, and carry out higher number and left shift without taking a complement on the displacement multiplicand when the corresponding bit of any one of the high-order operation circuits is higher so as to generate a high-order operation result;

a least significant bit operation circuit configured to output the multiplicand based only on the significance level of a least significant bit control signal determined by the multiplier, and to determine the sign of the multiplicand based on a least significant bit sign control signal determined by the multiplier, to generate a least significant bit operation result; and

a first adder configured to sum the high-order operation result and the low-order operation result to be a single operation result;

a third sub-operation circuit configured to output an addend according to the effective level of a sub-effective control signal, determine the sign of the addend according to a sub-symbol control signal, and sum the sign of the addend with a two-complement sum to generate a third sub-operation result;

the two-complement arithmetic circuit is configured to perform a preset logic operation on the sign control signals of all bits in the first sub-arithmetic circuit and the second sub-arithmetic circuit and the lowest bit sign control signal to generate the two-complement; and

and a second adder configured to sum the first sub-operation result and the third sub-operation result of the first sub-operation circuit and the second sub-operation circuit to generate a total operation result.

2. The arithmetic circuit of claim 1, wherein the high-order arithmetic circuits each comprise:

a bit left shift multiplexer configured to selectively shift left the multiplicand by different bits according to the shift control signal to generate the shift multiplicand;

a bit output unit configured to output the displacement multiplicand when the bit valid control signal is at the valid level, and to make the displacement multiplicand output zero when the bit valid control signal is at an invalid level;

a bit exclusive-OR gate configured to output the displacement multiplicand as a positive number when the bit symbol control signal is at a positive level, and to output the displacement multiplicand as a negative number when the bit symbol control signal is at a negative level; and

a bit left shift unit configured to shift the displacement multiplicand by a higher number of bits without taking the complement left shift for generating the high-order operation result.

3. The circuit of claim 2, wherein the number of high-order circuits is six, and the bit left shifting units of each high-order circuit respectively shift left 11, 9, 7, 5, 3 and 1 bits, the bit left shifting multiplexer selectively shifts left 0,1, 2 or 3 bits of the multiplicand according to the shift control signal to generate the shift multiplicand.

4. The arithmetic circuit of claim 2, wherein the least significant bit arithmetic circuit comprises:

a least significant bit output unit configured to output the multiplicand when the least significant bit control signal is at the significant bit and to zero the multiplicand when the least significant bit control signal is at the ineffective bit; and

the least significant exclusive OR gate is configured to output the multiplicand with a positive number when the least significant sign control signal is at the positive sign level, and output the multiplicand with a negative number when the least significant sign control signal is at the negative sign level, so as to generate the least significant operation result.

5. The arithmetic circuit of claim 1, wherein the third sub-arithmetic circuit further comprises:

a sub-output unit configured to output the addend when the sub-effective control signal is at the effective level, and to make the addend output zero when the sub-effective control signal is at an ineffective level;

a secondary exclusive OR gate configured to output the addend as a positive number when the secondary symbol control signal is at a positive level, and to output the addend as a negative number when the secondary symbol control signal is at a negative level; and

a third adder configured to sum the addend and the two-complement sum to generate the third operation result.

6. The circuit of claim 1, wherein the shift control signal, the bit-valid control signal, the bit-sign control signal, the least-significant control signal, and the least-significant control signal are determined by looking up a multiplier table from the multiplier.

7. The circuit of claim 6, wherein the multiplier table corresponds to one of HEVC, AVS2, VP9, AV1, VVC, and AVS3 standard.

8. The circuit of claim 1, wherein the number of high-order circuits is N, the two-complement circuit comprising:

a plurality of first logic circuits configured to operate in correspondence with the higher-order operation circuits having N-1 highest order bits of the first sub-operation circuit and the second sub-operation circuit, each of the first logic circuits comprising:

a complement AND gate configured to operate the bit symbol control signal corresponding to the higher bit operation circuit in the first sub operation circuit and the second sub operation circuit to generate an AND gate output signal;

a complement exclusive OR gate configured to operate the bit symbol control signal corresponding to the higher bit operation circuit in the first sub operation circuit and the second sub operation circuit to generate an exclusive OR gate output signal;

a second logic operation circuit configured to perform operations corresponding to one of the higher order operation circuits and the lower order operation circuits having the lowest order bits in the first term operation circuit and the second term operation circuit, so as to select one of a plurality of preset logic expressions according to the term sign control signal and the lowest order sign control signal, and perform logic operations on the bit sign control signal to generate a complement output signal; and

and the output circuit is configured to sum the AND gate output signals and the exclusive OR gate output signals of the first logic operation circuits and then add the sum with the complementary code output signals to generate the two-complement code.

9. The circuit of claim 1 wherein the bit symbol control signal is generated by exclusive-OR logic operation based on a high bit symbol signal and a sub-symbol signal determined by the multiplier, and the low bit symbol control signal is generated by exclusive-OR logic operation based on a low bit symbol signal and the sub-symbol determined by the multiplier.

10. The circuit of claim 9, wherein the high-level circuits further comprise a zero detection unit configured to maintain an original value of the bit symbol control signal and operate the high-level circuits when a zero detection signal is at a non-zero level, and to zero the bit symbol control signal and operate the high-level circuits when the zero detection signal is at a zero level, respectively; and

the lowest level operation circuit comprises a lowest level zero detection unit, which is configured to maintain the lowest level symbol control signal at an original value and enable the lowest level operation circuit to operate when the zero detection signal is at the non-zero level, and to enable the lowest level symbol control signal to be zero and enable the lowest level operation circuit to operate when the zero detection signal is at the zero level;

wherein the zero detection signal is generated by performing an OR logic operation on the multiplicand and the multiplicand.