CN117395434B - Hardware encoding and decoding debugging method, device, equipment and storage medium - Google Patents
Hardware encoding and decoding debugging method, device, equipment and storage medium Download PDFInfo
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Abstract
The embodiment of the application discloses a method, a device, equipment and a storage medium for debugging hardware encoding and decoding, wherein the method comprises the following steps: acquiring an actual register value issued by a user state driver to a video processing unit in the process of video acceleration of an application program by the video processing unit; obtaining a debugging result by comparing the actual register value with a preset register value; and performing program logic reverse pushing based on the debugging result to realize the encoding and decoding debugging process of the application program. Thus, the debugging process is more convenient, compared with the method only in the user mode, compared with all the encoding and decoding parameters, the method has the advantages of smaller debugging error and quicker obtained result.
Description
Technical Field
The present application relates to the field of computer graphics programming technology, and relates to, but is not limited to, hardware codec debugging methods, devices, apparatuses, and storage media.
Background
With the coming of the tide of domestic, the personal computers with domestic operating systems, domestic CPUs (Central Processing Unit, central processing units) and GPUs (Graph Process Unit, graphic processing units) are deployed in a large number, and the requirements of personal entertainment video and audio are met on machines for building the domestic GPUs. At present, the demands for video hardware encoding and decoding by using VPU (Video Processing Unit ) proprietary components are increasing, however, domestic GPU and VPU manufacturers are very painful when performing hardware encoding and decoding debugging in the early stage, and no effective debugging means can rapidly locate the hardware encoding and decoding problem. Therefore, it is desirable to provide a device and method for debugging a hardware codec.
Disclosure of Invention
In view of this, embodiments of the present application provide a method, apparatus, device, and storage medium for debugging a hardware codec, which at least solve the problems of complex debugging process and incomplete debugging result in the related art.
The technical scheme of the embodiment of the application is realized as follows:
in a first aspect, an embodiment of the present application provides a method for debugging a hardware codec, including:
acquiring an actual register value issued by a user state driver to a video processing unit in the process of video acceleration of an application program by the video processing unit; obtaining a debugging result by comparing the actual register value with a preset register value; and performing program logic reverse pushing based on the debugging result to realize the encoding and decoding debugging process of the application program.
In a second aspect, an embodiment of the present application provides a hardware codec debugging apparatus, including:
the data acquisition part is configured to acquire an actual register value issued by a user state driver to the video processing unit in the process of video acceleration of the application program by the video processing unit;
the data comparison part is configured to obtain a debugging result by comparing the actual register value with a preset register value;
and the debugging optimization module is configured to perform program logic reverse pushing based on the debugging result so as to realize the encoding and decoding debugging process of the application program.
In a third aspect, embodiments of the present application provide a computer device, including a memory and a processor, where the memory stores a computer program executable on the processor, and the processor implements the steps in the above-described hardware codec debugging method when executing the program.
In a fourth aspect, embodiments of the present application provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the hardware codec debugging method described above.
The beneficial effects that technical scheme that this application embodiment provided include at least:
in the embodiment of the application, firstly, acquiring all register values issued by a driver to VPU hardware in the acceleration process of an application program, and then comparing all actual register values with preset register values to obtain a debugging result; therefore, the purpose of easily debugging the VPU unit is achieved, the VPU debugging process is more convenient, compared with the method only in a user mode, compared with all encoding and decoding parameters, the method has the advantages that the debugging error is smaller, and the result is faster.
Drawings
For a clearer description of the technical solutions in the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art, wherein:
FIG. 1 is a schematic diagram of a computer system according to an embodiment of the present disclosure;
fig. 2 is a flow chart of a hardware codec debugging method according to an embodiment of the present application;
fig. 3 is a schematic diagram of a composition structure of a hardware codec debugging device according to an embodiment of the present application;
fig. 4 is a schematic hardware entity diagram of a computer device according to an embodiment of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. The following examples are illustrative of the present application, but are not intended to limit the scope of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.
It should be noted that the term "first\second\third" in relation to the embodiments of the present application is merely to distinguish similar objects and does not represent a specific ordering for the objects, it being understood that the "first\second\third" may be interchanged in a specific order or sequence, where allowed, to enable the embodiments of the present application described herein to be practiced in an order other than that illustrated or described herein.
It will be understood by those skilled in the art that all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of this application belong unless defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
And (3) decoding the software: the traditional video frame data decoding mode is based on software program operation and algorithm operation, and needs to occupy a large amount of system resources.
And (3) hardware decoding: in contrast to soft decoding, the hardware processing capacity of the VPU can be fully utilized by invoking the VPU to decode video frame data. The hardware decoding is to decode the high-definition video through the video acceleration function of the display card, so that the CPU can be released from heavy video decoding operation, and the computer has the capability of smoothly playing the high-definition video.
The VPU is a brand new core engine of the video processing platform, and has the functions of hard decoding and capability of reducing CPU load. In addition, the VPU can reduce server load and consumption of network bandwidth. The VPU is proposed by the ATI to distinguish from the traditional GPU. The graphic processing unit comprises three main modules, namely a video processing unit, an external video module and a post-processing module.
For simple and efficient control of the host processor, the VPU provides a set of registers called a host interface. Communication between the host processor and the VPU is via host interface registers through which the host processor can simply and efficiently control the VPU. The stream data and some of the output image data are accessed directly by the host processor and the VPU. To more fully and flexibly control the VPU, a set of API interface functions is provided that contain all the required operations so that the VPU is fully transparent to the developer.
In the conventional debugging method of the hardware encoding and decoding processing unit, the VPU is generally regarded as a black box, then parameters and data of encoding and decoding are obtained in a user mode through a debug method, and debugging is carried out by comparing the correctness of the parameters and the correctness of the data address which are set before encoding and decoding.
The method has more defects: firstly, only the user state can be debugged, and if the kernel state is in error, the kernel state cannot be debugged. Secondly, the parameters of the comparison user mode have certain misleading property, and the parameters and data sent to the VPU need to be deeply compared. Thirdly, the debugging method is easy to make mistakes, because the hardware encoding and decoding needs more parameters.
The application aims at providing a VPU debugging program, which can acquire all register parameters issued to VPU hardware by a driver, achieves the aim of easily debugging a VPU unit by comparing the set register parameters, and can grasp the using method of the debugging program by slightly training anyone without development experience.
Referring to fig. 1, which shows a component framework 100 of a computer system capable of implementing the embodiments of the present application, it is noted that the illustrated system is merely one example of a possible system, and that embodiments of the present application may be implemented in any of a variety of systems as desired. The computer system framework 100 may be any type of computing device including, but not limited to, a desktop computer, a server, a workstation, a laptop computer, a computer-based emulator, a wireless device, a mobile or cellular telephone (including so-called smart phones), a Personal Digital Assistant (PDA), a video game console (including a video display, a mobile video game device, a mobile video conferencing unit), a laptop computer, a desktop computer, a television set-top box, a tablet computing device, an electronic book reader, a fixed or mobile media player, and the like. As shown in fig. 1, computer system frame 100 may include a CPU10, a GPU20, a memory 30, and further includes a display processor 40, a display 41, and a communication interface 50. Display processor 40 may be part of the same integrated circuit (Integrated Circuit, IC) as GPU20, may be external to one or more ICs comprising GPU20, or may be formed in an IC external to an IC comprising GPU 20.
In particular, the CPU10 may comprise a general-purpose or special-purpose processor that controls the operation of the computer system framework 100, configured to process instructions of a computer program for execution. A user may communicate via the communication interface 50 with another input device (not shown) coupled to the computer system frame 100, such as: a trackball, keyboard, mouse, microphone, touch pad, touch screen, and other types of devices provide input to CPU10 in computer system frame 100 to cause CPU10 to execute instructions of one or more software applications. Applications executing on CPU10 may include graphical user interface (Graphic User Interface, GUI) applications, operating systems, portable graphics applications, computer-aided design applications for engineering or artistic applications, video game applications, word processor applications, email applications, spreadsheet applications, media player applications, or rendering applications using 2D, 3D graphics, etc., the embodiments of the present application exemplify executing graphics rendering applications. Further, the rendering application executing on the CPU10 may include one or more graphics rendering instructions (which may also be understood as including one or more of the graphics in the frame of the picture to be rendered) that may conform to a graphics API, such as an open graphics library API (OpenGL API), an open graphics library embedded system (OpenGLES) API, a Direct3D API, an X3D API, a renderMan API, a WebGL API, an open computing language (OpenCLTM), a renderScript, or any other heterogeneous computing API, or any other public or proprietary standard graphics or computing API.
GPU20 may be configured to perform graphics operations to render one or more graphics primitives to display 41 for presentation. It will be appreciated that CPU10 translates graphics rendering instructions defined by OpenGL into graphics rendering commands readable by GPU20 by controlling GPU driver 14, and then GPU20 renders and presents one or more graphics primitives on display 41 based on the received one or more graphics rendering commands, including, but not limited to, graphics commands and graphics data (e.g., drawing commands, state information, primitive information, texture information, etc.), such that GPU20 executes some or all of the graphics rendering commands.
Memory 30 is configured to store application instructions capable of running on CPU10, graphics data required for execution by GPU20, and execution result data thereof. For example, GPU20 may store the fully formed image in memory 30. Memory 30 may include one or more volatile or nonvolatile memory or storage devices such as Random Access Memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), erasable Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), flash memory, magnetic data media, or optical storage media. Display processor 40 may retrieve the image from memory 30 and output values that illuminate pixels of display 41 to display the image. Display 41 may be a display of computer system 100 that displays graphical image content generated by GPU 20. The display 41 may be a Liquid Crystal Display (LCD), an organic light emitting diode display (OLED), a Cathode Ray Tube (CRT) display, a plasma display, or another type of display device.
The host application sends commands and corresponding parameters to the VPU through the APIs to control the VPU. After receiving an interrupt from the VPU, information is sent that the requested operation has been completed. The definition of each API includes a request command and an input-output data structure. Commands given from the API are often written into a dedicated I/O register, but the input and output data structures are transferred through a set of I/O command registers that include input parameters and output results.
Based on the above computer system and examples, fig. 2 is a flow chart of a hardware codec debugging method according to an embodiment of the present application, as shown in fig. 2, where the method at least includes the following steps:
step S210, obtaining an actual register value issued by a user mode driver to a video processing unit in the process of utilizing the video processing unit to accelerate video of an application program.
Here, the application program is a program capable of providing rich video functions and user experiences, such as a video player, video editing software, and the like. The video acceleration of the application program is understood as the compression coding of each frame of image in the application program, and the user mode driver is responsible for converting the video coding and decoding technology into specific instructions and operations. The driver can optimize performance and efficiency in the video encoding and decoding process, and better user experience is improved. At the driver level, the hardware acceleration interface may be enabled through a related API. For example, in a camera driver, the v4l2 interface may be used to access the VPU and submit a portion of the computing task to the VPU process.
It should be noted that, in the process of encoding and decoding by using the video processing unit in the display card, the user mode driver firstly analyzes the encoding parameters and then issues the encoding parameters to the hardware IP, that is, the register value of the hardware IP is set based on the analyzed encoding parameters, so the application aims to read the actual register value of the hardware IP and verify whether the encoding and decoding process is correct to determine whether an error exists or not, so as to facilitate subsequent debugging.
Step S220, obtaining a debugging result by comparing the actual register value with a preset register value.
Here, the preset register value is a value stored in the code stream information stored when decoding a certain video, and is typically a value specified in the H264 or H265 video protocol standard.
Step S230, performing program logic reverse thrust based on the debug result to implement the codec debugging process of the application program.
In the embodiment of the application, firstly, acquiring all register values issued by a driver to VPU hardware in the acceleration process of an application program, and then comparing all actual register values with preset register values to obtain a debugging result; therefore, the purpose of easily debugging the VPU unit is achieved, the VPU debugging process is more convenient, compared with the method only in a user mode, compared with all encoding and decoding parameters, the method has the advantages that the debugging error is smaller, and the result is faster.
In some possible embodiments, the obtaining the actual register value issued by the user mode driver to the video processing unit during the video acceleration of the application program by the video processing unit includes: invoking a specific acceleration interface in the process of running the application program, and carrying out video acceleration through the video processing unit; wherein the specific acceleration interface is provided for the user mode driver; when the application program runs to a target frame image with errors, outputting a hardware register address corresponding to the target frame image through the user mode driver; based on the hardware register address, acquiring an actual register value corresponding to the hardware coding and decoding parameters in the video acceleration process.
Here, each frame of the application acceleration run may be extracted by the FFmpeg tool, and then the target frame image in which an error exists may be determined by analysis and comparison. The hardware register address is a Cmdbuf address, and can be directly output by a user mode driver, so that subsequent rapid debugging is facilitated.
FFmpeg is a set of open source code engineering that can be used to convert digital audio, video, and can be compiled into SDKs and command line tools. A user can use the SDK development program to realize the audio and video operation, and can also use the command line tool FFmpeg to realize the audio and video operation.
In some possible embodiments, the method further comprises: in the video acceleration process, comparing a first PSNR value of data decoded by using hardware and a second PSNR value of data decoded by using a central processing unit frame by frame aiming at the application program; and under the condition that the first PSNR value is inconsistent with the second PSNR value, determining the target frame image with errors in the running process of the application program.
The PSNR is herein referred to as "Peak Signal-to-Noise Ratio", and Chinese meaning Peak Signal-to-Noise Ratio is one of indexes for measuring image quality. The peak signal-to-noise ratio is often used as a measure of the quality of the signal reconstruction in the field of image compression etc., which is often defined simply by means of the Mean Square Error (MSE).
In some possible embodiments, the obtaining, based on the hardware register address, an actual register value corresponding to a hardware codec parameter in a video acceleration process includes: mapping the hardware register address to a virtual address through a first operating system interface; and reading the virtual address through a second operating system interface to obtain an actual register value corresponding to the hardware encoding and decoding parameters.
Here, the first operating system interface may be a mmap command, by which a physical address, which is a hardware register address, is mapped to a virtual address space; the second operating system interface may be a read command.
In some possible embodiments, the obtaining the debug result by comparing the actual register value with a preset register value includes: decoding and obtaining decoding parameters and data required by decoding all hardware by utilizing a central processing unit; setting the preset register value based on decoding parameters and data required by decoding of all hardware; and synchronously displaying the actual register value and the preset register value in a graphical interface for comparison analysis to obtain the debugging result.
Here, the decoding parameters required for the hardware decoding include, but are not limited to, a target frame rate (targetFps) of the encoder in a current time period, a target coding rate (targetbit), an actual total data amount (acturalSize) of the coded image, an actual frame number (frameCount) of the coded image, and the like.
According to the embodiment of the application, whether all actual register values and preset register values issued to VPU hardware by a driver are consistent or not can be visually compared through the image interface, and compared with the method of comparing the encoding and decoding parameters through a debug method, the method is more direct and effective, and errors are not easy to occur.
The above-mentioned hardware codec debugging method is described below with reference to a specific embodiment, however, it should be noted that this specific embodiment is only for better explaining the present application, and does not constitute an undue limitation on the present application.
The embodiment of the application provides a method for debugging domestic hardware coding and decoding equipment on a domestic system, which comprises the following specific steps:
s1, an application program calls an acceleration interface provided by a user mode driver to accelerate video by using the VPU.
S2, comparing whether the PSNR value of the data decoded by the hardware decoding and the PSNR value decoded by the CPU are consistent, if not, the hardware decoding has an error, and the user mode driver outputs the cmdbuf address of the error.
S3, mapping the cmdbuf physical address through an operating system interface mmap to obtain the virtual address. Where cmdbuf represents the register address of the hardware IP.
S4, reading the cmdbuf virtual address through the operating system interface read to obtain an actual register value which is issued to the hardware IP by the driver, and displaying the actual register value to the graphical interface.
S5, obtaining a debugging result by comparing the obtained actual register values corresponding to all hardware encoding and decoding parameters with preset register values (parameters and data needed by all hardware IP decoding are obtained through CPU decoding for setting).
S6, the program logic can be conveniently reversely pushed according to the debugging result, and therefore the logic loophole is obtained.
The embodiment of the application aims to provide a VPU debugging program, which can acquire all register parameters issued to VPU hardware by a driver, achieves the aim of easily debugging a VPU unit by comparing the set register parameters, and can grasp the using method of the debugging program even if people without development experience are slightly trained.
Compared with the prior art that the VPU is regarded as a black box, and then parameters and data of the encoding and decoding are obtained in a user mode through a debug method, the hardware encoding and decoding debugging method provided by the embodiment of the application, namely the VPU debugging program, has the following advantages that: the debugging is more convenient, and the operation can be performed only by being familiar with the debugging method; compared with all the encoding and decoding parameters, the debugging method has small error; the result is faster, and only the cmdbuf address is needed to be obtained for debugging.
Fig. 3 shows a hardware codec debugging apparatus provided in an embodiment of the present application, as shown in fig. 3, the hardware codec debugging apparatus 300 includes: a data acquisition section 310, a data comparison section 320, and a debug optimization section 330, wherein:
the data obtaining part 310 is configured to obtain an actual register value issued by a user state driver to the video processing unit in the process of performing video acceleration on an application program by using the video processing unit;
the data comparing part 320 is configured to obtain a debug result by comparing the actual register value with a preset register value;
the debug optimization portion 330 is configured to perform program logic back-pushing based on the debug results to implement a codec debugging process of the application.
In some possible embodiments, the data acquisition portion 310 includes: an acceleration unit configured to invoke a specific acceleration interface in the process of running the application program, and perform video acceleration through the video processing unit; wherein the specific acceleration interface is provided for the user mode driver; the address recording unit is configured to output a hardware register address corresponding to a target frame image through the user mode driver when the application program runs to the target frame image with errors; the first acquisition unit is configured to acquire an actual register value corresponding to the hardware encoding and decoding parameters in the video acceleration process based on the hardware register address.
In some possible embodiments, the method further comprises: a comparison analysis section configured to compare, for the application program, a first PSNR value of data decoded using hardware and a second PSNR value of data decoded using a central processor, frame by frame in a video acceleration process; and a determining section configured to determine the target frame image in which an error exists during the running of the application program, in a case where the first PSNR value does not coincide with the second PSNR value.
In some possible embodiments, the first fetch unit is further configured to map the hardware register address to a virtual address through a first operating system interface; and reading the virtual address through a second operating system interface to obtain an actual register value corresponding to the hardware encoding and decoding parameters.
In some possible embodiments, the data comparison portion 320 includes: the third acquisition unit is configured to decode and acquire decoding parameters and data required by decoding of all hardware by utilizing the central processing unit; a parameter setting unit configured to set the preset register value based on decoding parameters and data required for decoding of the all hardware; and the display comparison unit is configured to synchronously display the actual register value and the preset register value into a graphical interface for comparison analysis, so as to obtain the debugging result.
Correspondingly, the embodiment of the application provides a computer readable storage medium, on which a computer program is stored, which when being executed by a processor, implements the steps of the hardware codec debugging method of any of the above embodiments.
Correspondingly, in an embodiment of the present application, there is also provided a computer program product for implementing the steps of the hardware codec debugging method of any of the above embodiments, when the computer program product is executed by a processor of an electronic device.
Based on the same technical concept, fig. 4 is a specific hardware structure of a computer device 400 provided in an embodiment of the present application to implement the debugging method provided in the embodiment of the present application, as shown in fig. 4, the computer device 400 may include: a communication interface 401, a memory 402, a processor 403 and a display 405; the various components are coupled together by a bus system 404. It is appreciated that the bus system 404 serves to facilitate connected communications between these components. The bus system 404 includes a power bus, a control bus, and a status signal bus in addition to the data bus. But for clarity of illustration the various buses are labeled as bus system 404 in fig. 4. The communication interface 401 is configured to receive and send signals in a process of receiving and sending information with other external network elements;
the memory 402 is configured to store a computer program capable of running on the processor 403;
the processor 403 is configured to perform the following steps when running the computer program: acquiring an actual register value issued by a user state driver to a video processing unit in the process of video acceleration of an application program by the video processing unit; obtaining a debugging result by comparing the actual register value with a preset register value; and performing program logic reverse pushing based on the debugging result to realize the encoding and decoding debugging process of the application program.
The display 405 is configured to display a video image, and display an actual register value and a preset register value corresponding to all the acquired hardware encoding and decoding parameters.
It is to be appreciated that the memory 402 in embodiments of the present application may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The nonvolatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable EPROM (EEPROM), or a flash Memory. The volatile memory may be random access memory (Random Access Memory, RAM) which acts as an external cache. By way of example, and not limitation, many forms of RAM are available, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (Double data rate SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), and Direct RAM (DRRAM). The memory 402 of the systems and methods described herein is intended to comprise, without being limited to, these and any other suitable types of memory.
While processor 403 may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in the processor 403 or by instructions in the form of software. The processor 403 may be a general purpose processor, a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. The disclosed methods, steps, and logic blocks in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the embodiments of the present application may be embodied directly in hardware, in a decoded processor, or in a combination of hardware and software components in a decoded processor. The software portion may be located in a state-of-the-art storage medium such as random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, registers, etc. The storage medium is located in the memory 402, and the processor 403 reads the information in the memory 402 and performs the steps of the method in combination with its hardware.
It is to be understood that the embodiments described herein may be implemented in hardware, software, firmware, middleware, microcode, or a combination thereof. For a hardware implementation, the processing units may be implemented within one or more application specific integrated circuits (Application Specific Integrated Circuits, ASIC), digital signal processors (Digital Signal Processing, DSP), digital signal processing devices (DSP devices, DSPD), programmable logic devices (Programmable Logic Device, PLD), field programmable gate arrays (Field-Programmable Gate Array, FPGA), general purpose processors, controllers, microcontrollers, microprocessors, other electronic units configured to perform the functions described herein, or a combination thereof.
For a software implementation, the techniques described herein may be implemented with parts (e.g., procedures, functions, and so on) that perform the functions described herein. The software codes may be stored in a memory and executed by a processor. The memory may be implemented within the processor or external to the processor.
Specifically, the processor 403 is further configured to execute the steps of the hardware codec debugging method in the foregoing technical solution when running the computer program, which is not described herein.
It should be understood that the above exemplary technical solution of the computer device 400 belongs to the same concept as the technical solution of the above hardware codec debugging method, and therefore, for details of the above technical solution of the computer device 400 that are not described in detail, reference may be made to the description of the technical solution of the above hardware codec debugging method. This embodiment of the present application will not be described in detail.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present application, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by the functions and internal logic thereof, and should not constitute any limitation on the implementation process of the embodiments of the present application. The foregoing embodiment numbers of the present application are merely for describing, and do not represent advantages or disadvantages of the embodiments.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above described device embodiments are only illustrative, e.g. the division of the units is only one logical function division, and there may be other divisions in practice, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the various components shown or discussed may be coupled or directly coupled or communicatively coupled to each other via some interface, whether indirectly coupled or communicatively coupled to devices or units, whether electrically, mechanically, or otherwise.
The units described above as separate components may or may not be physically separate, and components shown as units may or may not be physical units; can be located in one place or distributed to a plurality of network units; some or all of the units may be selected according to actual needs to achieve the purposes of the embodiments of the present application.
In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may be separately used as one unit, or two or more units may be integrated in one unit; the integrated units may be implemented in hardware or in hardware plus software functional units.
Alternatively, the integrated units described above may be stored in a computer readable storage medium if implemented in the form of software functional modules and sold or used as a stand-alone product. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially or partly contributing to the related art, embodied in the form of a software product stored in a storage medium, including several instructions for causing an apparatus automatic test line to perform all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a removable storage device, a ROM, a magnetic disk, or an optical disk.
The methods disclosed in the several method embodiments provided in the present application may be arbitrarily combined without collision to obtain a new method embodiment. The features disclosed in the several method or apparatus embodiments provided in the present application may be arbitrarily combined without conflict to obtain new method embodiments or apparatus embodiments.
The foregoing is merely an embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (8)
1. A method for debugging a hardware codec, the method comprising:
invoking a specific acceleration interface in the process of running the application program, and carrying out video acceleration through a video processing unit; the specific acceleration interface is provided for a user mode driver;
when the application program runs to a target frame image with errors, outputting a hardware register address corresponding to the target frame image through the user mode driver;
based on the hardware register address, acquiring an actual register value corresponding to a hardware encoding and decoding parameter in the video acceleration process;
obtaining a debugging result by comparing the actual register value with a preset register value;
and performing program logic reverse pushing based on the debugging result to realize the encoding and decoding debugging process of the application program.
2. The method according to claim 1, wherein the method further comprises:
in the video acceleration process, comparing a first PSNR value of data decoded by using hardware and a second PSNR value of data decoded by using a central processing unit frame by frame aiming at the application program;
and under the condition that the first PSNR value is inconsistent with the second PSNR value, determining the target frame image with errors in the running process of the application program.
3. The method according to claim 1, wherein the obtaining, based on the hardware register address, an actual register value corresponding to a hardware codec parameter in a video acceleration process includes:
mapping the hardware register address to a virtual address through a first operating system interface;
and reading the virtual address through a second operating system interface to obtain an actual register value corresponding to the hardware encoding and decoding parameters.
4. A method according to any one of claims 1 to 3, wherein said obtaining a debug result by comparing said actual register value with a preset register value comprises:
decoding and obtaining decoding parameters and data required by decoding all hardware by utilizing a central processing unit;
setting the preset register value based on decoding parameters and data required by decoding of all hardware;
and synchronously displaying the actual register value and the preset register value in a graphical interface for comparison analysis to obtain the debugging result.
5. A hardware codec debugging device, comprising a data acquisition part, a data comparison part and a debugging optimization part, wherein:
the data acquisition part is configured to call a specific acceleration interface in the process of running the application program, and video acceleration is carried out through the video processing unit; the specific acceleration interface is provided for a user mode driver; when the application program runs to a target frame image with errors, outputting a hardware register address corresponding to the target frame image through the user mode driver; based on the hardware register address, acquiring an actual register value corresponding to a hardware encoding and decoding parameter in the video acceleration process;
the data comparison part is configured to obtain a debugging result by comparing the actual register value with a preset register value;
the debugging optimizing part is configured to perform program logic back-pushing based on the debugging result so as to realize the encoding and decoding debugging process of the application program.
6. The apparatus of claim 5, wherein the debug optimization section comprises:
the second acquisition unit is configured to decode and acquire decoding parameters and data required by decoding of all hardware by utilizing the central processing unit;
a setting unit configured to set the preset register value based on decoding parameters and data required for decoding of the all hardware;
and the comparison analysis unit is configured to synchronously display the actual register value and the preset register value into a graphical interface for comparison analysis to obtain the debugging result.
7. A computer device comprising a memory and a processor, the memory storing a computer program executable on the processor, characterized in that the processor implements the steps of the hardware codec debugging method of any of claims 1 to 4 when the program is executed.
8. A computer storage medium storing a computer program or instructions which, when executed by at least one processor, implement the steps of the hardware codec debugging method of any of claims 1 to 4.
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