CN117394800A - Power amplifier, bias circuit thereof and radio frequency front end module - Google Patents

Power amplifier, bias circuit thereof and radio frequency front end module Download PDF

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Publication number
CN117394800A
CN117394800A CN202311205000.0A CN202311205000A CN117394800A CN 117394800 A CN117394800 A CN 117394800A CN 202311205000 A CN202311205000 A CN 202311205000A CN 117394800 A CN117394800 A CN 117394800A
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CN
China
Prior art keywords
circuit
bias
transistor
power
control
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Pending
Application number
CN202311205000.0A
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Chinese (zh)
Inventor
张滔
赖晓蕾
倪建兴
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Radrock Shenzhen Technology Co Ltd
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Radrock Shenzhen Technology Co Ltd
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Priority to CN202311205000.0A priority Critical patent/CN117394800A/en
Publication of CN117394800A publication Critical patent/CN117394800A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/52—Circuit arrangements for protecting such amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/447—Indexing scheme relating to amplifiers the amplifier being protected to temperature influence
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier

Abstract

The embodiment of the application provides a power amplifier and bias circuit thereof, radio frequency front end module, bias circuit includes: a bias subcircuit, a first shunt subcircuit, or a second shunt subcircuit; the bias sub-circuit comprises a bias transistor, a first end of the bias transistor is coupled with a bias control end, a second end of the bias transistor is coupled with a power supply end, and a third end of the bias transistor is used for providing bias current for the power amplifying circuit; the first end of the first shunt subcircuit is coupled with the second end of the bias transistor in the bias subcircuit and is used for shunting the current output by the power supply end; the first terminal of the second shunt sub-circuit is coupled to the third terminal of the bias transistor in the bias sub-circuit for shunting the current output by the third terminal of the bias transistor. The bias current provided to the power amplifier circuit is reduced by the first shunt sub-circuit or the second shunt sub-circuit, so that the power amplifier is prevented from being over-heated.

Description

Power amplifier, bias circuit thereof and radio frequency front end module
Technical Field
The application relates to the technical field of radio frequency communication, in particular to a power amplifier, a bias circuit thereof and a radio frequency front-end module.
Background
The power amplifier is a very critical module in the radio frequency communication system, and is mainly used for amplifying low-power radio frequency signals and then radiating out through an antenna so as to carry out information communication. The power amplifier can generate heat when working, generally, the larger the output power is, the more serious the heat is, and when the temperature is too high, the damage to components can be caused.
Disclosure of Invention
The application provides a power amplifier, a bias circuit thereof and a radio frequency front end module, which can prevent the power amplifier from being over-high in temperature.
In a first aspect, embodiments of the present application provide a bias circuit of a power amplifier, the bias circuit including:
a bias sub-circuit comprising a bias transistor, a first terminal of the bias transistor being coupled to a bias control terminal, a second terminal of the bias transistor being coupled to a power supply terminal, a third terminal of the bias transistor being for providing a bias current to the power amplifying circuit;
and the first end of the first shunt subcircuit is coupled with the second end of the bias transistor in the bias subcircuit, the second end of the first shunt subcircuit is grounded, and the first shunt subcircuit is used for shunting the current output by the power supply end.
In a second aspect, embodiments of the present application provide a bias circuit of a power amplifier, the bias circuit including:
a bias sub-circuit comprising a bias transistor, a first terminal of the bias transistor being coupled to a bias control terminal, a second terminal of the bias transistor being coupled to a power supply terminal, a third terminal of the bias transistor being for providing a bias current to the power amplifying circuit;
and the second shunt sub-circuit is used for shunting the current output by the third end of the bias transistor.
In a third aspect, embodiments of the present application provide a power amplifier, including: the power amplifier comprises a power amplifying circuit and the biasing circuit, wherein the biasing circuit is used for providing biasing current for the power amplifying circuit.
In a fourth aspect, an embodiment of the present application provides a radio frequency front end module, including the bias circuit of the power amplifier, or including the power amplifier.
The embodiment of the application provides a power amplifier, a bias circuit thereof and a radio frequency front end module, wherein the bias circuit comprises: a bias sub-circuit comprising a bias transistor having a first terminal coupled to a bias control terminal, a second terminal coupled to a power supply terminal, and a third terminal for providing a bias current to the power amplifying circuit; the first end of the first shunt subcircuit is coupled with the second end of the bias transistor in the bias subcircuit, the second end of the first shunt subcircuit is grounded, and the first shunt subcircuit is used for shunting current output by the power supply end; the first end of the second shunt subcircuit is coupled with the third end of the bias transistor in the bias subcircuit, the second end of the second shunt subcircuit is grounded, and the second shunt subcircuit is used for shunting current output by the third end of the bias transistor. The bias current provided to the power amplifier circuit is reduced by the first shunt subcircuit and/or the second shunt subcircuit, preventing the power amplifier from being over-heated.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure of embodiments of the present application.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic block diagram of a bias circuit provided by an embodiment of the present application;
FIG. 2 is a circuit schematic of one embodiment of the biasing circuit of FIG. 1;
FIG. 3 is a schematic block diagram of control circuitry in one embodiment;
FIG. 4 is a schematic block diagram of a bias circuit provided in another embodiment of the present application;
FIG. 5 is a circuit schematic of an embodiment of the biasing circuit of FIG. 4;
FIG. 6 is a circuit schematic of a bias circuit provided in accordance with yet another embodiment of the present application;
FIG. 7 is a schematic block diagram of a power amplifier provided by an embodiment of the present application;
fig. 8 is a schematic block diagram of a radio frequency front end module according to an embodiment of the present application.
Reference numerals illustrate:
101. a bias control terminal; 102. a power supply end;
100. a bias circuit; 110. a bias subcircuit; 111. a bias transistor; 120. a first shunt subcircuit; 121. a first resistor circuit; 122. a first transistor; 123. a first diode; 130. a control circuit; 131a, a first primary inductance; 132a, a first secondary inductance; 133a, a first rectifying and filtering circuit; 131b, a second primary inductance; 132b, a second secondary inductance; 133b, a second rectifying and filtering circuit; 140. a second shunt subcircuit; 141. a second resistor circuit; 142. a second transistor;
200. and a power amplifying circuit.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
It should be understood that the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for the same elements throughout for clarity.
In the following description, for the purpose of providing a thorough understanding of the present invention, detailed structures and steps are presented in order to illustrate the technical solution presented by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments in addition to these detailed descriptions.
Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.
Referring to fig. 1, fig. 1 is a schematic block diagram of a bias circuit 100 of a power amplifier according to an embodiment of the present application.
The power amplifier can be applied to a radio frequency front end module, and the radio frequency front end module is an element which integrates two or more than two discrete devices such as a radio frequency switch, a low noise amplifier, a filter, a duplexer, a power amplifier and the like into a single module, thereby improving the integration level and the hardware performance and miniaturizing the volume. Specifically, the radio frequency front end module can be applied to 4G and 5G communication equipment such as smart phones, tablet computers, smart watches and the like.
The bias circuit 100 is configured to provide a bias current to the power amplification circuit 200, and the power amplification circuit 200 may amplify a low-power radio frequency signal based on the bias current, and the amplified radio frequency signal may be radiated through an antenna, for example, for information communication.
The power amplification circuit 200 generates heat when amplifying signals, and generally, the heat generation is more serious as the output power of the power amplification circuit 200 is larger. Overheating and damage of components can be prevented by controlling the output power of the power amplification circuit 200. The output power of the power amplification circuit 200 is related to the magnitude of the bias current provided by the bias circuit 100, and the embodiment of the present application can control the output power of the power amplification circuit 200 by controlling the magnitude of the bias current.
As shown in fig. 1, the bias circuit 100 includes: a bias subcircuit 110 and a first shunt subcircuit 120.
The bias subcircuit 110 comprises a bias transistor 111, a first terminal of the bias transistor 111 being coupled to the bias control terminal 101, a second terminal of the bias transistor 111 being coupled to the supply terminal 102, a third terminal of the bias transistor 111 being for providing a bias current to the power amplifying circuit 200.
In some embodiments, the device including the bias circuit 100 and the power amplifier circuit 200 may be referred to as a power amplifier. For example, the power amplifying circuit 200 includes transistors, and each stage of the power amplifying circuit 200 may include a transistor array including a plurality of transistors connected in parallel. The transistors in the power amplifier circuit 200 are, for example, heterojunction Bipolar Transistors (HBTs) or normal bipolar junction transistors, and the bias current provided by the bias sub-circuit 110 is input to the base of the transistor.
The bias control terminal 101 and the power supply terminal 102 may be corresponding nodes on a CMOS (Complementary Metal Oxide Semiconductor ) chip in the rf front-end module, and optionally, the bias circuit 100 may be integrated on the CMOS chip. For ease of illustration, the bias circuit 100 is shown separately from the CMOS chip as shown in fig. 2.
Illustratively, the CMOS chip includes a current source therein, which can output a fixed current through the power supply terminal 102 to the second terminal of the bias transistor 111. For example, the current source may include a current-mode digital-to-analog converter (IDAC), a code value is input to the current-mode digital-to-analog converter through a digital circuit or a logic circuit, and the current-mode digital-to-analog converter is capable of outputting a current Io corresponding to the code value, that is, a total current output by the power supply terminal 102 may be denoted as Io.
The current Iref output by the bias control terminal 101 is at least used to maintain the conduction of the bias transistor 111, for example, as shown in fig. 2, the first terminal of the bias transistor 111 is grounded through one or more diodes, so that the voltage of the first terminal of the bias transistor 111 is greater than or equal to the conduction voltage of the bias transistor 111 under the action of the current Iref, so as to make the bias transistor 111 conductive. The current output from the power supply terminal 102 may be applied to the power amplifying circuit 200 through the turned-on bias transistor 111, and the current applied to the power amplifying circuit 200 by the third terminal of the bias transistor 111 is referred to as the bias current of the power amplifying circuit 200. In some embodiments, the degree of conduction of the bias transistor 111 may also be adjusted by adjusting the current Iref of the bias control terminal 101 to adjust the bias current output by the bias transistor 111.
As shown in fig. 1, a first terminal of the first shunt sub-circuit 120 is coupled to a second terminal of the bias transistor 111 in the bias sub-circuit 110, that is, to the power supply terminal 102, a second terminal of the first shunt sub-circuit 120 is grounded, and the first shunt sub-circuit 120 is used to shunt the current output by the power supply terminal 102.
In the case that the total current Io output by the power supply terminal 102 is fixed, the first shunt sub-circuit 120 shunts the current Id from the total current Io, so that the current provided by the power supply terminal 102 to the second terminal of the bias transistor 111 in the bias sub-circuit 110 becomes smaller, and the current at the third terminal of the bias transistor 111 also becomes smaller, that is, the bias current provided by the bias transistor 111 to the power amplifying circuit 200 decreases; the output power of the power amplifier circuit 200 is also reduced when the bias current is reduced, and the amount of heat generated is reduced, so that the power amplifier can be prevented from becoming excessively high.
In some embodiments, the bias circuit 100 includes N bias sub-circuits 110, where N is a natural number greater than or equal to 1. As shown in fig. 2, the bias circuit 100 includes 3 bias sub-circuits 110, i.e., N is equal to 3. Optionally, different bias sub-circuits 110 are used to provide bias currents to different power amplification circuits 200, or different bias sub-circuits 110 are used to provide bias currents to different bias terminals of the same power amplification circuit 200. For example, when the power amplifier includes multiple stages of power amplifying circuits 200, different bias sub-circuits 110 are used to boost bias currents to the power amplifying circuits 200 of different stages, or to provide bias currents to different bias terminals of the power amplifying circuits 200 of the same stage.
Referring to fig. 2, taking bias transistor 111 as an NPN triode as an example, io=n×ic+id, for each NPN triode, ie=ib+ic, since Ib is small, ie≡ic, where Ie, ib and Ic are the currents of the emitter, base and collector of the NPN triode, respectively. It is determined that, in the case where the total current Io output from the power supply terminal 102 is fixed, the current Id output from the power supply terminal 102 is split by the first splitter circuit 120, so that the bias current provided by each bias sub-circuit 110 to the power amplifier circuit 200 can be reduced, and the power amplifier temperature is prevented from being excessively high.
In some embodiments, referring to fig. 2, in some embodiments, the first shunt sub-circuit 120 may include a first transistor 122, where a control terminal of the first transistor 122 is configured to receive a control signal to control the first transistor 122 to be turned on or off according to the control signal. The other two ends of the first transistor 122 are connected between the power supply terminal and the ground terminal, so that the current output by the power supply terminal is split to the ground when the first transistor is turned on.
Illustratively, the first shunt sub-circuit 120 is capable of switching to an on state or an off state. The first shunt sub-circuit 120 may be switched to the on state by controlling the first transistor 122 to be on, for example, and the first transistor 122 to be off may be controlled to be switched to the off state by controlling the first transistor 122 to be off. For example, the bias circuit 100 further includes a control circuit 130, and the control circuit 130 is coupled to the control terminal of the first transistor 122 to control the first transistor 122 to be turned on or off. When the first shunt sub-circuit 120 is capable of switching to the on state, the first shunt sub-circuit 120 shunts the current output from the power supply terminal 102, the bias current supplied from the bias sub-circuit 110 to the power amplifying circuit 200 decreases, and the output power of the power amplifying circuit 200 also decreases.
Illustratively, the first shunt subcircuit 120 is configured to: the power amplifier circuit 200 switches to the on state or the off state according to the output power. For example, the first shunt subcircuit 120 is configured to: when the output power of the power amplification circuit 200 is greater than the first power threshold, it is switched to the connected state. When the output power of the power amplification circuit 200 is large, the amount of heat generated is also large, and when the output power of the power amplification circuit 200 is larger than the first power threshold, the bias current supplied to the power amplification circuit 200 by the bias sub-circuit 110 can be reduced by controlling the first shunt sub-circuit 120 to switch to the on state so as to reduce the output power of the power amplification circuit 200, thereby preventing overheating.
Alternatively, the current level of the first shunt sub-circuit 120 shunted from the power supply terminal 102 may be fixed or may be adjustable.
In some embodiments, the magnitude of the current shunted from the power supply terminal 102 by the first shunt sub-circuit 120 is fixed. For example, when the first shunt sub-circuit 120 includes only the first transistor 122, and the control voltage Vpro1 received by the control terminal of the first transistor 122 is constant on the premise of satisfying the on condition of the first transistor 122, the first shunt sub-circuit may shunt a fixed magnitude of current from the power supply terminal 102.
Illustratively, a control terminal of the first transistor 122 may be connected to the control circuit to receive the control voltage Vpro1 provided by the control circuit.
In some embodiments, when the control voltage provided by the control circuit is relatively large, in order to prevent the first transistor 122 from being broken down, one or more diodes may be connected in series to the control terminal of the first transistor 122, where the anode of the diode is connected to the control circuit, the cathode is connected to the control terminal of the first transistor 122, and a fixed voltage difference exists between the cathode and the anode after the diode is turned on, so that the voltage of the control terminal of the first transistor 122 can be reduced, and the first transistor 122 is ensured not to be broken down.
In some embodiments, the magnitude of the current that the first shunt sub-circuit 120 shunts from the power supply terminal 102 is adjustable. By adjusting the current Id split by the first split sub-circuit 120, the bias current provided by each bias sub-circuit 110 to the power amplifying circuit 200 can be changed correspondingly, i.e. the bias current output to the power amplifying circuit 200 can be flexibly adjusted.
Optionally, the first shunt sub-circuit 120 is further configured to: the magnitude of the current diverted from the power supply terminal 102 is adjusted according to the output power of the power amplifying circuit 200. Illustratively, the first shunt subcircuit 120 is further configured to: when the output power of the power amplifying circuit 200 is greater than the first power threshold, the current level shunted from the power supply terminal 102 is adjusted according to the level of the output power. For example, when the output power of the power amplifying circuit 200 exceeds the first power threshold by more, the first shunt sub-circuit 120 can be adjusted to shunt more current; when the output power exceeds the first power threshold by less, the first shunt sub-circuit 120 can be adjusted to shunt less current, and the output power of the power amplifier can be accurately adjusted.
Optionally, the first power threshold is determined according to a rated power corresponding to an operation mode of the power amplifier. The first power threshold corresponding to each operating mode may be greater than or equal to the power rating of the power amplifier in that power mode. The different requirements of the power amplifier are related to the operation modes of the power amplifier, which may exhibit different performances due to the different operation modes of the power amplifier. By setting the first power threshold according to the rated power corresponding to the working mode, the power amplifier can be ensured to be in a normal working state in different working modes.
In some embodiments, the voltage Vpro1 applied to the control terminal of the first transistor 122 may be adjustable, and the magnitude of the current shunted from the power supply terminal 102 by the first shunt sub-circuit 120 may be adjusted by adjusting the voltage of the control terminal of the first transistor 122.
Illustratively, the control circuit 130 is also configured to regulate the voltage applied to the control terminal of the first transistor 122. For example, the control circuit 130 may adjust the voltage applied to the control terminal of the first transistor 122 according to the output power of the power amplifying circuit 200 to adjust the magnitude of the current shunted from the power supply terminal 102. For example, the larger the output power of the power amplifying circuit 200, the larger the voltage applied to the control terminal of the first transistor 122, the larger the current that the first shunt sub-circuit 120 shunts from the power supply terminal 102, and the more the bias current that each bias sub-circuit 110 provides to the power amplifying circuit 200 decreases, the more the output power of the power amplifying circuit 200 decreases to prevent overheating.
In some embodiments, as shown in fig. 2, the first shunt sub-circuit 120 may further include a first resistance circuit 121, the first resistance circuit 121 including at least one resistance. Illustratively, as shown in FIG. 2, the first shunt sub-circuit 120 includes a first resistor circuit 121 and a first transistor 122, the first resistor circuit 121 being in series with the first transistor 122.
The first resistor circuit 121 prevents the current in the first shunt sub-circuit 120 from being excessively large, and ensures that the bias current supplied from each bias sub-circuit 110 to the power amplifying circuit 200 is sufficient. Alternatively, the resistance value of the first resistor circuit 121 may be fixed or may be adjustable. When the voltage applied to the control terminal of the first transistor 122 is a fixed voltage and the resistance value of the first resistor circuit 121 is fixed, the current Id shunted by the first shunt sub-circuit 120 is a fixed current. When any one of the voltage applied to the control terminal of the first transistor 122 and the resistance value of the first resistor circuit 121 is adjustable, the current shunted from the power supply terminal 102 by the first shunt sub-circuit 120 is adjustable.
In some embodiments, referring to fig. 3, the control circuit 130 includes at least a first primary inductor 131a, a first secondary inductor 132a, and a first rectifying and filtering circuit 133a; the first primary inductor 131a is used to connect with the power amplifying circuit 200 to couple the energy obtained from the power amplifying circuit 200 to the first secondary inductor 132a; the first rectifying and filtering circuit 133a rectifies and filters the energy coupled to the first secondary inductor 132a to obtain a dc voltage, and the first rectifying and filtering circuit 133a applies the dc voltage to the control terminal of the first transistor 122. The first primary inductor 131a and the first secondary inductor 132a form a coupling circuit, and the larger the output power of the power amplifying circuit 200 is, the higher the energy coupled to the first secondary inductor 132a is; isolation from the power amplifying circuit 200 may also be achieved, for example, to prevent interference of the first shunt sub-circuit 120 with the power amplifying circuit 200. The dc voltage obtained by the first rectifying and filtering circuit 133a is related to the energy coupled to the first secondary inductor 132a, and generates a dc voltage related to the output power of the power amplifying circuit 200; for example, the larger the output power of the power amplifying circuit 200, the higher the energy coupled to the first secondary inductor 132a, and the higher the dc voltage obtained by the first rectifying and filtering circuit 133 a. For example, the first rectifying and filtering circuit 133a may include: the rectification circuit rectifies the sine wave output by the first secondary inductor 132a into a half wave (only half period is reserved), the amplification circuit amplifies the half wave, and the RC filter circuit converts the amplified half wave into the direct current voltage.
In other embodiments, the control circuit 130 may include other forms of voltage detection circuits and/or current detection circuits to determine the output power of the power amplification circuit 200 based on the detected voltage and/or current, and to adjust the current Id split by the first splitter circuit 120, such as adjusting the voltage Vpro1 applied to the control terminal of the first transistor 122.
Illustratively, the first transistor 122 is a PNP transistor (e.g., a PNP transistor) or a P-type field effect transistor, and the control circuit 130 further includes a first voltage conversion circuit; the first voltage conversion circuit is configured to convert the dc voltage output by the first rectifying and filtering circuit 133a into a low level and apply the low level to the control terminal of the first transistor 122. For example, in fig. 3, the first rectifying and filtering circuit 133a is further connected to the first voltage converting circuit, and the voltage rectified by the first rectifying and filtering circuit 133a is at a high level, and the first voltage converting circuit converts the high level into a low level, so that it is ensured that the PNP transistor or the P-type field effect transistor can be controlled to be turned on.
Illustratively, the first transistor 122 is an NPN transistor, and the control circuit 130 further includes a second voltage conversion circuit; the dc voltage output by the first rectifying and filtering circuit 133a is lower than the on voltage of the first transistor 122, and the second voltage converting circuit is configured to increase the dc voltage output by the first rectifying and filtering circuit 133a, and the increased dc voltage is applied to the control terminal of the first transistor 122. For example, in fig. 3, the second voltage conversion circuit is further connected after the first rectifying and filtering circuit 133a, and when the dc voltage output by the first rectifying and filtering circuit 133a is lower than the turn-on voltage of the NPN transistor, the second voltage conversion circuit applies the increased dc voltage to the control terminal of the NPN transistor, so that the turn-on of the NPN transistor can be controlled.
The first transistor 122 is an N-type field effect transistor, and the control circuit 130 further includes a third voltage conversion circuit. The dc voltage output by the first rectifying and filtering circuit 133a is higher than the breakdown voltage of the first transistor 122, and the third voltage converting circuit is configured to reduce the dc voltage output by the first rectifying and filtering circuit 133a, and the reduced dc voltage is applied to the control terminal (e.g., the gate) of the first transistor 122. For example, in fig. 3, the third voltage converting circuit is further connected after the first rectifying and filtering circuit 133a,when the dc voltage outputted from the first rectifying and filtering circuit 133a is higher than the breakdown voltage of the first transistor 122,the direct current voltage output from the first rectifying and filtering circuit 133a can be prevented from breaking down the N-type field effect transistor.
The first transistor 122 is an N-type field effect transistor, and the control circuit 130 further includes a third voltage conversion circuit. The dc voltage output by the first rectifying and filtering circuit 133a is lower than the on voltage of the first transistor 122, and the third voltage converting circuit is configured to increase the dc voltage output by the first rectifying and filtering circuit 133a, and the increased dc voltage is applied to the control terminal of the first transistor 122. For example, in fig. 3, the third voltage conversion circuit is further connected after the first rectifying and filtering circuit 133a, and when the dc voltage output by the first rectifying and filtering circuit 133a is lower than the on voltage of the N-type field effect transistor, the third voltage conversion circuit applies the increased dc voltage to the control terminal (such as the gate) of the N-type field effect transistor, so that the N-type field effect transistor can be controlled to be turned on.
Illustratively, the control circuit 130 further includes a fourth voltage conversion circuit for regulating and controlling the magnitude of the voltage applied to the control terminal of the first transistor 122. For example, in fig. 3, the fourth voltage conversion circuit is further connected after the first rectifying and filtering circuit 133a, for example, the voltage obtained by the first rectifying and filtering circuit 133a may be shifted by a fixed amplitude to adjust the magnitude of the voltage Vpro1 applied to the control terminal of the first transistor 122 by the control circuit 130, so as to control the magnitude of the current shunted from the power supply terminal 102 by the first shunt sub-circuit 120.
In some embodiments, the resistance of the first resistor circuit 121 is adjustable, and the magnitude of the current that the first shunt sub-circuit 120 shunts from the power supply terminal 102 can be adjusted by adjusting the resistance of the first resistor circuit 121; for example, the smaller the resistance value of the first resistance circuit 121, the larger the current to be split. For example, the first resistor circuit 121 includes an adjustable resistor.
Illustratively, the control circuit 130 is coupled to the first resistive circuit 121 to control a resistance value of the first resistive circuit 121. For example, the first resistor circuit 121 is implemented by a resistor-switch network, and the control circuit 130 changes the number of resistors connected to the first shunt sub-circuit 120 by controlling a switch connected in series or parallel with the resistor to change the resistance of the first resistor circuit 121. It will be appreciated that in other embodiments, the control circuit 130 may adjust the voltage applied to the control terminal of the first transistor 122, or may adjust the resistance of the first resistor circuit 121.
Illustratively, the control circuit 130 is configured to adjust the resistance of the first resistor circuit 121 according to the output power of the power amplifying circuit 200, so as to adjust the magnitude of the current that is shunted from the power supply terminal 102. For example, the larger the output power of the power amplifying circuit 200, the smaller the resistance value of the first resistor circuit 121, the larger the current that the first shunt sub-circuit 120 shunts from the power supply terminal 102, and the more the bias current that each bias sub-circuit 110 provides to the power amplifying circuit 200 decreases, the more the output power of the power amplifying circuit 200 decreases to prevent overheating.
Optionally, as shown in fig. 2, the first shunt sub-circuit 120 further includes a first diode 123, and the first diode 123 is connected in series with the first transistor 122. For example, the anode of the first diode 123 is coupled to the second terminal of the bias transistor 111, the cathode of the first diode 123 is coupled to ground, the first diode 123 is capable of providing a certain voltage drop and preventing other currents from flowing back into the bias sub-circuit 110 through the first shunt sub-circuit 120.
For example, the first diode 123 may be a separate diode, or may be a diode-connected transistor (i.e., a transistor with a short circuit between the base and the collector/emitter). Alternatively, the number of the first diodes 123 may be one or more, and the sum of the turn-on voltage of the plurality of first diodes 123, the turn-on voltage of the first transistor 122, and the voltages across the first resistor circuit 121 may not exceed the potential of the power supply terminal 102. The current-voltage curve of the diode/triode is nonlinear, and the Gain curve (Gain-Pout curve) of the power amplifier circuit 200 can be changed by adding the first diode 123, unlike the resistor, where Pout is the output power of the power amplifier. Alternatively, the first diode 123 may be replaced by a resistor if only to provide a voltage drop; the same voltage drop can be achieved with a smaller area than with a diode or diode-connected transistor instead of a resistor, so that the first shunt sub-circuit 120 does not need a too large resistor and can be reduced in area.
The bias circuit 100 provided in the embodiment of the present application includes: a bias sub-circuit 110, the bias sub-circuit 110 comprising a bias transistor 111, a first terminal of the bias transistor 111 being coupled to the bias control terminal 101, a second terminal of the bias transistor 111 being coupled to the power supply terminal 102, a third terminal of the bias transistor 111 being for providing a bias current to the power amplifying circuit 200; a first shunt sub-circuit 120, a first end of the first shunt sub-circuit 120 is coupled to a second end of the bias transistor 111 in the bias sub-circuit 110, a second end of the first shunt sub-circuit 120 is grounded, and the first shunt sub-circuit 120 is used for shunting current output by the power supply terminal 102; the bias current provided to the power amplifier circuit 200 is reduced by the first shunt sub-circuit 120, preventing the power amplifier from being over-heated.
The bias circuit 100 provided in the embodiment of the present application can reduce the bias current provided by the bias sub-circuit 110 to the power amplification circuit 200 from the source, and the saturation power of the power amplification circuit 200 can also be controlled, for example, when the output power of the power amplification circuit 200 is greater than the first power threshold, the output power of the power amplification circuit 200 can be reduced, so as to prevent the power amplifier from having too high temperature. In the related art, the voltage or current of the first terminal (base or gate) of the bias transistor 111 is controlled to change the bias current output from the third terminal of the bias transistor 111, so that the gain of the power amplifying circuit 200 can be reduced only, and the saturated power of the power amplifying circuit 200 cannot be controlled.
Referring to fig. 4 in combination with the foregoing embodiments, a schematic block diagram of a bias circuit 100 according to another embodiment of the present application is shown in fig. 4.
The bias circuit 100 shown in fig. 4 comprises a bias subcircuit 110 and a second shunt subcircuit 140, wherein the bias subcircuit 110 comprises a bias transistor 111, a first terminal of the bias transistor 111 being coupled to the bias control terminal 101, a second terminal of the bias transistor 111 being coupled to the supply terminal 102, a third terminal of the bias transistor 111 being for providing a bias current to the power amplifying circuit 200. The first terminal of the second shunt sub-circuit 140 is coupled to the third terminal of the bias transistor 111 in the bias sub-circuit 110, the second terminal of the second shunt sub-circuit 140 is grounded, and the second shunt sub-circuit 140 is used for shunting the current output by the third terminal of the bias transistor 111. By shunting the current output from the third terminal of the bias transistor 111, the bias current supplied from the third terminal of the bias transistor 111 to the power amplifier circuit 200 can be reduced, the output power of the power amplifier circuit 200 when the bias current is reduced can be reduced, the heat generation amount can be reduced, and the power amplifier temperature can be prevented from being excessively high.
In at least one embodiment, the power amplifier includes a multi-stage power amplification circuit 200. The bias currents of the power amplifying circuits 200 of different stages may be different; the bias currents at different bias terminals (e.g., P-terminal and N-terminal) of the same level differential power amplifier circuit 200 may also be different. The bias circuit 100 comprises a plurality of bias sub-circuits 110, at least two bias sub-circuits 110 being arranged to provide bias currents to different power amplifying circuits 200, such as power amplifying circuits 200 of different stages, or at least two bias sub-circuits 110 being arranged to provide bias currents to different bias terminals of the same power amplifying circuit 200. Different bias subcircuits 110 are used to provide bias currents to different power amplification circuits 200, or different bias subcircuits 110 are used to provide bias currents to different bias terminals of the same power amplification circuit 200. For example, referring to fig. 5, the circuit includes a two-stage power amplifying circuit 200, wherein the first-stage power amplifying circuit 200 is a differential power amplifying circuit and has two bias terminals, and the bias currents are respectively provided to the two bias terminals of the first-stage power amplifying circuit 200 by two different bias sub-circuits 110, and the second-stage power amplifying circuit is a single-ended power amplifying circuit and has one bias terminal, and the bias currents are provided to the second-stage power amplifying circuit by another bias sub-circuit 110. It should be appreciated that in other embodiments, the front stage power amplifying circuit of the power amplifier may be a single-ended power amplifying circuit, and the rear stage power amplifying circuit may be a differential power amplifying circuit.
In some embodiments, the bias circuit 100 includes a plurality of bias subcircuits 110, wherein at least a portion of the bias subcircuits 110 have third terminals of bias transistors 111 coupled with first terminals of respective second shunt subcircuits 140. As shown in fig. 5, the bias circuit 100 includes 3 bias sub-circuits 110, with two bias sub-circuits 110 coupled with a second shunt sub-circuit 140. The bias current provided by the bias sub-circuit 110 without the second shunt sub-circuit 140 shunting current is greater than the bias current provided by the bias sub-circuit 110 with the second shunt sub-circuit 140 shunting current. It may be determined whether the second shunt sub-circuit 140 is connected to the bias sub-circuit 110 according to a bias current required for the power amplifying circuit 200 to which the bias sub-circuit 110 is connected.
Illustratively, the currents that at least two second shunt subcircuits 140 each shunt from a corresponding bias transistor 111 are different. For example, the current that the different second shunt sub-circuit 140 shunts from the corresponding bias transistor 111 may also be more flexibly set according to the bias current required by the power amplifying circuit 200 to which the bias sub-circuit 110 is connected.
In some embodiments, referring to fig. 5, the second shunt sub-circuit 140 may include a second transistor 142, where a control terminal of the second transistor 142 is configured to receive a control signal to control the second transistor 142 to be turned on or off according to the control signal. The other two ends of the second transistor 142 are connected between the third end of the bias transistor 111 and the ground, so as to shunt the current output by the third end of the bias transistor 111 to the ground when being conducted.
Illustratively, the second shunt subcircuit 140 is capable of switching to an on state or an off state. The second shunt sub-circuit 140 may be switched to the on state by controlling the second transistor 142 to be on, and the second transistor 142 to be off may be controlled to be switched to the off state, for example. For example, the bias circuit 100 further includes a control circuit 130, and the control circuit 130 is coupled to the control terminal of the second transistor 142 to control the second transistor 142 to be turned on or off. When the second shunt sub-circuit 140 is capable of switching to the on state, the second shunt sub-circuit 140 shunts the current output from the third terminal of the bias transistor 111, the bias current supplied from the bias sub-circuit 110 to the power amplifying circuit 200 decreases, and the output power of the power amplifying circuit 200 also decreases.
Illustratively, the second shunt subcircuit 140 is configured to: the power amplifier circuit 200 switches to the on state or the off state according to the output power. For example, the second shunt subcircuit 140 is configured to: when the output power of the power amplification circuit 200 is greater than the second power threshold, it is switched to the connected state. When the output power of the power amplification circuit 200 is large, the amount of heat generated is also large, and when the output power of the power amplification circuit 200 is larger than the second power threshold value, the second shunt sub-circuit 140 is controlled to switch to the on state to reduce the bias current supplied from the bias sub-circuit 110 to the power amplification circuit 200, so that the output power of the power amplification circuit 200 can be reduced, and overheating can be prevented.
Alternatively, the magnitude of the current shunted from the third terminal of the bias transistor 111 by the second shunt subcircuit 140 may be fixed or may be adjustable.
In some embodiments, the magnitude of the current shunted from the third terminal of the bias transistor 111 by the second shunt subcircuit 140 is fixed. For example, when the second shunt sub-circuit 140 includes only the second transistor 142, and the control voltage Vpro2 received by the control terminal of the second transistor 142 is fixed on the premise that the on condition of the second transistor 142 is satisfied, the second shunt sub-circuit 140 may shunt a current of a fixed magnitude from the third terminal of the bias transistor 111.
Illustratively, a control terminal of the second transistor 142 may be connected to the control circuit to receive the control voltage Vpro2 provided by the control circuit.
In some embodiments, when the control voltage provided by the control circuit is relatively large, in order to prevent the second transistor 142 from being broken down, one or more diodes may be connected in series to the control terminal of the second transistor 142, where the anode of the diode is connected to the control circuit, the cathode is connected to the control terminal of the second transistor 142, and a fixed voltage difference is provided between the cathode and the anode after the diode is turned on, so that the voltage of the control terminal of the second transistor 142 can be reduced, and the second transistor 142 is ensured not to be broken down.
In some embodiments, the magnitude of the current shunted from bias transistor 111 by second shunt subcircuit 140 is adjustable. By adjusting the current split by the second split sub-circuit 140, the bias current provided by the bias sub-circuit 110 corresponding to the second split sub-circuit 140 to the power amplifying circuit 200 can be changed correspondingly, that is, the bias current output to the power amplifying circuit 200 can be flexibly adjusted. In the case that the currents respectively shunted from the corresponding bias transistors 111 are different in the different second shunt sub-circuits 140, the bias currents supplied by the different bias sub-circuits 110 may also be different; for example, the current that the different second shunt sub-circuits 140 shunt from the corresponding bias transistors 111 may be more flexibly set according to the bias current required by the power amplifying circuit 200 to which the bias sub-circuits 110 are connected.
Optionally, the second shunt sub-circuit 140 is further configured to: the magnitude of the current shunted from the bias transistor 111 is adjusted according to the output power of the power amplifying circuit 200. Illustratively, the second shunt subcircuit 140 is configured to: when the output power of the power amplifying circuit 200 is greater than the second power threshold, the magnitude of the current shunted from the bias transistor 111 is adjusted according to the magnitude of the output power. For example, when the output power of the power amplifying circuit 200 exceeds the second power threshold by more, the second current splitting sub-circuit 140 can be adjusted to split more current; when the output power exceeds the second power threshold by a small amount, the second shunt sub-circuit 140 can be adjusted to shunt less current, and the output power of the power amplifier can be accurately adjusted.
Optionally, the second power threshold is determined according to a rated power corresponding to an operation mode of the power amplifier. The second power threshold corresponding to each operating mode may be greater than or equal to the power rating of the power amplifier in that power mode. The different requirements of the power amplifier are related to the operation modes of the power amplifier, which may exhibit different performances due to the different operation modes of the power amplifier. By setting the second power threshold according to the rated power corresponding to the working mode, the power amplifier can be ensured to be in a normal working state in different working modes. The second power threshold may be the same as or different from the first power described above.
In some embodiments, the voltage Vpro2 applied to the control terminal of the second transistor 142 may be adjustable, and the magnitude of the current shunted from the bias transistor 111 by the second shunt sub-circuit 140 may be adjusted by adjusting the voltage of the control terminal of the second transistor 142.
Illustratively, the control circuit 130 is also configured to regulate the voltage applied to the control terminal of the second transistor 142. For example, the control circuit 130 may adjust the voltage applied to the control terminal of the second transistor 142 according to the output power of the power amplifying circuit 200 to adjust the magnitude of the current split from the bias transistor 111 by the second split sub-circuit 140. For example, the larger the output power of the power amplifying circuit 200, the larger the voltage applied to the control terminal of the second transistor 142, the larger the current that the second shunt sub-circuit 140 shunts from the bias transistor 111, and the more the bias current that the corresponding bias sub-circuit 110 provides to the power amplifying circuit 200 decreases, the more the output power of the power amplifying circuit 200 decreases to prevent overheating.
In some embodiments, the second shunt sub-circuit 140 may further include a second resistance circuit 141, the second resistance circuit 141 including at least one resistance. Illustratively, as shown in FIG. 4, the second shunt sub-circuit 140 may further include a second resistive circuit 141, the second resistive circuit 141 including at least one resistor. Illustratively, as shown in fig. 5, the second shunt sub-circuit 140 includes a second resistor circuit 141 and a second transistor 142, the second resistor circuit 141 being connected in series with the second transistor 142.
The second resistor circuit 141 can prevent the current on the second shunt sub-circuit 140 from being excessively large, and can ensure that the bias current provided to the power amplifying circuit 200 by the bias sub-circuit 110 corresponding to the second shunt sub-circuit 140 is sufficient. Alternatively, the resistance value of the second resistor circuit 141 may be fixed or may be adjustable. When the voltage applied to the control terminal of the second transistor 142 is a fixed voltage and the resistance value of the second resistance circuit 141 is fixed, the current split by the second split sub-circuit 140 is a fixed current. When any one of the voltage applied to the control terminal of the second transistor 142 and the resistance value of the second resistance circuit 141 is adjustable, the current shunted from the bias transistor 111 by the second shunt sub-circuit 140 is adjustable.
In some embodiments, referring to fig. 3, the control circuit 130 includes at least a second primary inductor 131b, a second secondary inductor 132b, and a second rectifying and filtering circuit 133b; the second primary inductor 131b is used to connect with the power amplifying circuit 200 to couple the energy obtained from the power amplifying circuit 200 to the second secondary inductor 132b; the second rectifying and filtering circuit 133b rectifies and filters the energy coupled to the second secondary inductor 132b to obtain a dc voltage, and the second rectifying and filtering circuit 133b applies the dc voltage Vpro2 to the control terminal of the second transistor 142 in the second shunt sub-circuit 140. The second primary inductor 131b, the second secondary inductor 132b and the second rectifying and filtering circuit 133b may be separately provided from the first primary inductor 131a, the first secondary inductor 132a and the first rectifying and filtering circuit 133a, or may be the same primary inductor, the secondary inductor and the rectifying and filtering circuit.
The second primary inductor 131b and the second secondary inductor 132b form a coupling circuit, and the larger the output power of the power amplifying circuit 200 is, the higher the energy coupled to the second secondary inductor 132b is; isolation from the power amplifying circuit 200 may also be achieved, for example, to prevent interference of the second shunt sub-circuit 140 with the power amplifying circuit 200. The dc voltage obtained by the second rectifying and filtering circuit 133b is related to the energy coupled to the second secondary inductor 132b, and generates a dc voltage related to the output power of the power amplifying circuit 200; for example, the larger the output power of the power amplifying circuit 200, the higher the energy coupled to the second secondary inductor 132b, and the higher the dc voltage obtained by the second rectifying and filtering circuit 133 b. For example, the second rectifying and filtering circuit 133b may include: the rectifying circuit rectifies the sine wave output by the second secondary inductor 132b into a half wave (only half period is reserved), the amplifying circuit amplifies the half wave, and the RC filter circuit converts the amplified half wave into the direct current voltage.
In other embodiments, the control circuit 130 may include other forms of voltage detection circuits and/or current detection circuits to determine the output power of the power amplification circuit 200 based on the detected voltage and/or current, and to adjust the current split by the second split sub-circuit 140, such as adjusting the voltage Vpro2 applied to the control terminal of the second transistor 142.
Illustratively, the second transistor 142 is a PNP transistor (e.g., a PNP transistor) or a P-type field effect transistor, and the control circuit 130 further includes a fifth voltage conversion circuit; the fifth voltage conversion circuit is configured to convert the dc voltage output from the second rectifying and filtering circuit 133b into a low level and apply the low level to the control terminal of the second transistor 142. For example, in fig. 3, the fifth voltage converting circuit is further connected after the second rectifying and filtering circuit 133b, the voltage rectified and output by the second rectifying and filtering circuit 133b is at a high level, and the fifth voltage converting circuit converts the high level into a low level, so that it is ensured that the PNP type transistor or the P type field effect transistor can be controlled to be turned on.
Illustratively, the second transistor 142 is an NPN transistor, and the control circuit 130 further includes a sixth voltage converting circuit; the dc voltage output by the second rectifying and filtering circuit 133b is lower than the on voltage of the second transistor 142, and the sixth voltage converting circuit is configured to increase the dc voltage output by the second rectifying and filtering circuit 133b, and the increased dc voltage is applied to the control terminal of the second transistor 142. For example, in fig. 3, the second rectifying and filtering circuit 133b is further connected to the sixth voltage converting circuit, and when the dc voltage output by the second rectifying and filtering circuit 133b is lower than the turn-on voltage of the NPN transistor, the sixth voltage converting circuit applies the increased dc voltage to the control terminal of the NPN transistor, so that the NPN transistor can be controlled to be turned on.
Illustratively, the second transistor 142 is an N-type field effect transistor, and the control circuit 130 further includes a seventh voltage conversion circuit. The dc voltage output by the second rectifying and filtering circuit 133b is higher than the breakdown voltage of the second transistor 142, and the seventh voltage converting circuit is configured to reduce the dc voltage output by the second rectifying and filtering circuit 133b, and the reduced dc voltage is applied to the control terminal (e.g., the gate) of the second transistor 142. For example, in fig. 3, the seventh voltage conversion circuit is further connected after the second rectifying and filtering circuit 133b, so that the dc voltage output by the second rectifying and filtering circuit 133b can be prevented from breaking down the N-type field effect transistor.
Illustratively, the second transistor 142 is an N-type field effect transistor, and the control circuit 130 further includes a seventh voltage conversion circuit. The dc voltage output by the second rectifying and filtering circuit 133b is lower than the on voltage of the second transistor 142, and the seventh voltage converting circuit is configured to increase the dc voltage output by the second rectifying and filtering circuit 133b, and the increased dc voltage is applied to the control terminal of the second transistor 142. For example, in fig. 3, the seventh voltage converting circuit is further connected after the second rectifying and filtering circuit 133b, and when the dc voltage output by the second rectifying and filtering circuit 133b is lower than the on voltage of the N-type field effect transistor, the seventh voltage converting circuit applies the increased dc voltage to the control terminal (such as the gate) of the N-type field effect transistor, so that the N-type field effect transistor can be controlled to be turned on.
Illustratively, the control circuit 130 further includes an eighth voltage conversion circuit for regulating and controlling the magnitude of the voltage applied to the control terminal of the second transistor 142. For example, in fig. 3, the eighth voltage conversion circuit is further connected after the second rectifying and filtering circuit 133b, for example, the voltage obtained by the second rectifying and filtering circuit 133b may be shifted by a fixed amplitude to adjust the magnitude of the voltage Vpro2 applied to the control terminal of the second transistor 142 by the control circuit 130, so as to control the magnitude of the current shunted by the bias transistor 111 by the second shunt sub-circuit 140.
In some embodiments, the resistance of the second resistor circuit 141 is adjustable, and the magnitude of the current shunted from the bias transistor 111 by the second shunt sub-circuit 140 can be adjusted by adjusting the resistance of the second resistor circuit 141; for example, the smaller the resistance value of the second resistance circuit 141, the larger the current to be split. For example, the second resistor circuit 141 includes an adjustable resistor.
Illustratively, the control circuit 130 is coupled to the second resistive circuit 141 to control the resistance of the second resistive circuit 141. For example, the second resistor circuit 141 is implemented by a resistor-switch network, and the control circuit 130 changes the number of resistors connected to the second shunt sub-circuit 140 by controlling a switch connected in series or parallel with the resistor to change the resistance of the second resistor circuit 141. It will be appreciated that in other embodiments, the control circuit 130 may adjust the voltage applied to the control terminal of the second transistor 142, as well as the resistance of the second resistor circuit 141.
Illustratively, the control circuit 130 is configured to adjust the resistance of the second resistor circuit 141 according to the output power of the power amplifying circuit 200, so as to adjust the magnitude of the current that is shunted from the bias transistor 111. For example, the larger the output power of the power amplifying circuit 200, the smaller the resistance value of the second resistor circuit 141, the larger the current that the second shunt sub-circuit 140 shunts from the bias transistor 111, and the more the bias current that the corresponding bias sub-circuit 110 provides to the power amplifying circuit 200 decreases, the more the output power of the power amplifying circuit 200 decreases to prevent overheating.
The bias circuit 100 provided in the embodiment of the present application includes: a bias sub-circuit 110, the bias sub-circuit 110 comprising a bias transistor 111, a first terminal of the bias transistor 111 being coupled to the bias control terminal 101, a second terminal of the bias transistor 111 being coupled to the power supply terminal 102, a third terminal of the bias transistor 111 being for providing a bias current to the power amplifying circuit 200; a second shunt sub-circuit 140, a first end of the second shunt sub-circuit 140 is coupled to a third end of the bias transistor 111 in the bias sub-circuit 110, a second end of the second shunt sub-circuit 140 is grounded, and the second shunt sub-circuit 140 is used for shunting current output by the third end of the bias transistor 111; the bias current provided to the power amplifier circuit 200 is reduced by the second shunt subcircuit 140, preventing the power amplifier from being too hot.
The bias circuit 100 provided in the embodiment of the present application can reduce the bias current provided by the bias sub-circuit 110 to the power amplification circuit 200 from the source, and the saturation power of the power amplification circuit 200 can also be controlled, for example, when the output power of the power amplification circuit 200 is greater than the first power threshold, the output power of the power amplification circuit 200 can be reduced, so as to prevent the power amplifier from having too high temperature. In the related art, by controlling the voltage or current of the first terminal (base or gate) of the bias transistor 111 to change the bias current output from the third terminal of the bias transistor 111, the real-time output power of the power amplifying circuit 200 can only be reduced, and the saturated power of the power amplifying circuit 200 cannot be controlled.
In some embodiments, the bias currents provided by different bias subcircuits 110 to different power amplification circuits 200 may be flexibly controlled by different second shunt subcircuits 140, or the bias currents provided by different bias subcircuits 110 to different bias terminals of the same power amplification circuit 200 may be flexibly controlled.
In other embodiments of the present application, referring to fig. 6 in combination with the previous embodiments, the bias circuit 100 includes the bias sub-circuit 110 and the first and second shunt sub-circuits 120 and 140; wherein the bias subcircuit 110 comprises a bias transistor 111, a first terminal of the bias transistor 111 being coupled to the bias control terminal 101, a second terminal of the bias transistor 111 being coupled to the power supply terminal 102, a third terminal of the bias transistor 111 being for providing a bias current to the power amplifying circuit 200; a first end of the first shunt sub-circuit 120 is coupled to the power supply end 102, a second end of the first shunt sub-circuit 120 is grounded, and the first shunt sub-circuit 120 is used for shunting current output by the power supply end 102; the first terminal of the second shunt sub-circuit 140 is coupled to the third terminal of the bias transistor 111 in the bias sub-circuit 110, the second terminal of the second shunt sub-circuit 140 is grounded, and the second shunt sub-circuit 140 is used for shunting the current output by the third terminal of the bias transistor 111.
The bias current provided by the bias sub-circuit 110 to the power amplifying circuit 200 can be adjusted more flexibly by the first shunt sub-circuit 120 shunting the current output by the power supply terminal 102 and the second shunt sub-circuit 140 shunting the current output by the third terminal of the bias transistor 111.
Optionally, the first shunt subcircuit 120 is configured to: the power amplifier circuit 200 switches to the on state or the off state according to the output power.
Optionally, the first shunt sub-circuit 120 is further configured to: the magnitude of the current diverted from the power supply terminal 102 is adjusted according to the output power of the power amplifying circuit 200.
Optionally, the first shunt subcircuit 120 is configured to: when the output power of the power amplification circuit 200 is greater than the first power threshold, it is switched to the connected state.
Optionally, the first shunt sub-circuit 120 is further configured to: when the output power of the power amplifying circuit 200 is greater than the first power threshold, the current level shunted from the power supply terminal 102 is adjusted according to the level of the output power.
Optionally, the first power threshold is determined according to a rated power corresponding to an operation mode of the power amplifier.
Optionally, the first shunt sub-circuit 120 includes a first resistor circuit 121 and a first transistor 122, and the first resistor circuit 121 is connected in series with the first transistor 122.
Optionally, the bias circuit 100 further includes a control circuit 130, and the control circuit 130 is coupled to the control terminal of the first transistor 122 to control the first transistor 122 to be turned on or off.
Optionally, the control circuit 130 is further configured to adjust the voltage applied to the control terminal of the first transistor 122 according to the output power of the power amplifying circuit.
Optionally, the control circuit 130 includes at least a first primary inductor 131a, a first secondary inductor 132a, and a first rectifying and filtering circuit 133a;
the first primary inductor 131a is used to connect with the power amplifying circuit 200 to couple the energy obtained from the power amplifying circuit 200 to the first secondary inductor 132a;
the first rectifying and filtering circuit 133a rectifies and filters the energy coupled to the first secondary inductor 132a to obtain a dc voltage, and the first rectifying and filtering circuit 133a applies the dc voltage to the control terminal of the first transistor 122.
Optionally, the first transistor 122 is a PNP transistor or a P-type field effect transistor, and the control circuit 130 further includes a first voltage conversion circuit;
the first voltage conversion circuit is configured to convert the dc voltage output by the first rectifying and filtering circuit 133a into a low level and apply the low level to the control terminal of the first transistor 122.
Optionally, the first transistor 122 is an NPN transistor, and the control circuit 130 further includes a second voltage conversion circuit;
the dc voltage output by the first rectifying and filtering circuit 133a is lower than the on voltage of the first transistor 122, and the second voltage converting circuit is configured to increase the dc voltage output by the first rectifying and filtering circuit 133a, and the increased dc voltage is applied to the control terminal of the first transistor 122.
Optionally, the first transistor 122 is an N-type field effect transistor, and the control circuit 130 further includes a third voltage conversion circuit;
the dc voltage output by the first rectifying and filtering circuit 133a is higher than the breakdown voltage of the first transistor 122, and the third voltage converting circuit is configured to reduce the dc voltage output by the first rectifying and filtering circuit 133a, and the reduced dc voltage is applied to the control terminal of the first transistor 122; or,
the dc voltage output by the first rectifying and filtering circuit 133a is lower than the on voltage of the first transistor 122, and the third voltage converting circuit is configured to increase the dc voltage output by the first rectifying and filtering circuit 133a, and the increased dc voltage is applied to the control terminal of the first transistor 122.
Optionally, the control circuit 130 further includes a fourth voltage conversion circuit for adjusting and controlling the magnitude of the voltage applied to the control terminal of the first transistor 122.
Optionally, the bias circuit 100 further includes a control circuit 130, where the control circuit 130 is coupled to the first resistor circuit 121 to control a resistance value of the first resistor circuit 121.
Optionally, the control circuit 130 is configured to adjust the resistance of the first resistor circuit 121 according to the output power of the power amplifying circuit 200.
Optionally, the first shunt sub-circuit 120 further includes a first diode 123, and the first diode 123 is connected in series with the first resistor circuit 121 and the first transistor 122.
The bias current supplied to the power amplifying circuit 200 is reduced by the first shunt sub-circuit 120, and at the same time, the bias current supplied to the power amplifying circuit 200 is reduced by the second shunt sub-circuit 140, so that the power amplifier temperature can be prevented from being excessively high. The bias current supplied from the bias sub-circuit 110 to the power amplifying circuit 200 can be reduced from the source, and the saturation power of the power amplifying circuit 200 can be controlled. The bias currents provided by different bias sub-circuits 110 to different power amplifying circuits 200 may also be flexibly controlled by different second shunt sub-circuits 140, or the bias currents provided by different bias sub-circuits 110 to different bias terminals of the same power amplifying circuit 200 may be flexibly controlled.
Referring to fig. 7 in combination with the foregoing embodiments, a schematic block diagram of a power amplifier according to some embodiments of the present application is provided. The power amplifier includes: the power amplification circuit 200 and the bias circuit 100 described above, the bias circuit 100 is configured to supply a bias current to the power amplification circuit 200.
In some embodiments, the bias circuit 100 includes a plurality of bias subcircuits 110, at least two bias subcircuits 110 for providing bias currents to different power amplification circuits 200, or at least two bias subcircuits 110 for providing bias currents to different bias terminals of the same power amplification circuit 200.
The specific principles and implementation of the power amplifier provided in the embodiments of the present application are similar to those of the bias circuit 100 in the foregoing embodiments, and are not repeated here.
Referring to fig. 8 in combination with the foregoing embodiment, a schematic block diagram of a radio frequency front end module is also provided in an embodiment of the present application. The rf front-end module includes the bias circuit 100 of the power amplifier or the power amplifier.
As an embodiment, the radio frequency front end module may include a first chip and a second chip, where the first chip is integrated with the power amplifier; the second chip is a control chip of the power amplifier, is internally integrated with a control circuit of the power amplifier, and is electrically connected with the first chip. Alternatively, the bias circuit 100 of the power amplifier may be integrated in the first chip or may be integrated in the second chip.
For example, the first chip and the second chip may be in different processes, for example, the first chip is in HBT process, also called HBT chip, and the second chip is in CMOS process, also called CMOS chip.
In some embodiments, the rf front-end module may further include an rf switch, a low noise amplifier, a filter, a duplexer, etc., and may be integrated into one module, thereby improving integration and performance and miniaturizing the volume.
The specific principle and implementation manner of the rf front-end module provided in this embodiment are similar to those of the bias circuit or the power amplifier in the foregoing embodiment, and are not repeated here.
It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on" …, "" adjacent to "…," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" …, "" directly adjacent to "…," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under …," "under …," "below," "under …," "above …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under …" and "under …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
While the invention has been described with reference to certain preferred embodiments, it will be understood by those skilled in the art that various changes and substitutions of equivalents may be made and equivalents will be apparent to those skilled in the art without departing from the scope of the invention. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (33)

1. A bias circuit for a power amplifier, the bias circuit comprising:
a bias sub-circuit comprising a bias transistor, a first terminal of the bias transistor being coupled to a bias control terminal, a second terminal of the bias transistor being coupled to a power supply terminal, a third terminal of the bias transistor being for providing a bias current to the power amplifying circuit;
and the first end of the first shunt subcircuit is coupled with the second end of the bias transistor in the bias subcircuit, the second end of the first shunt subcircuit is grounded, and the first shunt subcircuit is used for shunting the current output by the power supply end.
2. The biasing circuit of claim 1, wherein the first shunt subcircuit is configured to: and switching to a connection state or a disconnection state according to the output power of the power amplification circuit.
3. The biasing circuit of claim 2, wherein the first shunt subcircuit is further configured to: and regulating the current which is shunted from the power supply end according to the output power of the power amplifying circuit.
4. The biasing circuit of claim 2, wherein the first shunt subcircuit is configured to: and when the output power of the power amplifying circuit is larger than a first power threshold value, switching to a communication state.
5. The bias circuit of claim 4 wherein said first shunt subcircuit is further configured to: when the output power of the power amplifying circuit is larger than a first power threshold value, the current which is shunted from the power supply end is adjusted according to the output power.
6. The bias circuit of claim 5 wherein said first power threshold is greater than or equal to a rated power corresponding to a mode of operation of said power amplifier.
7. The bias circuit of any one of claims 1-6 wherein the first shunt subcircuit includes a first transistor, a control terminal of the first transistor for receiving a control signal to control the first transistor to turn on or off in accordance with the control signal.
8. The bias circuit of claim 7 wherein said first shunt subcircuit further comprises a first resistive circuit, said first resistive circuit being in series with said first transistor.
9. The bias circuit of claim 7 further comprising a control circuit coupled to a control terminal of the first transistor to control the first transistor to turn on or off.
10. The bias circuit of claim 9 wherein said control circuit is further configured to adjust a voltage applied to a control terminal of said first transistor based on an output power of said power amplifying circuit.
11. The biasing circuit of claim 10, wherein the control circuit comprises at least a first primary inductor, a first secondary inductor, and a first rectifying and filtering circuit;
the first primary inductor is used for being connected with the power amplifying circuit so as to couple energy obtained from the power amplifying circuit to the first secondary inductor;
the first rectifying and filtering circuit performs rectifying and filtering on the energy coupled to the first secondary inductor to obtain a direct-current voltage, and the first rectifying and filtering circuit applies the direct-current voltage to a control end of the first transistor.
12. The bias circuit of claim 11 wherein said first transistor is a PNP transistor or a P-type field effect transistor, said control circuit further comprising a first voltage conversion circuit;
the first voltage conversion circuit is used for converting the direct current voltage output by the first rectifying and filtering circuit into a low level and applying the low level to the control end of the first transistor.
13. The bias circuit of claim 11 wherein said first transistor is an NPN transistor, said control circuit further comprising a second voltage conversion circuit;
the direct current voltage output by the first rectifying and filtering circuit is lower than the conducting voltage of the first transistor, the second voltage conversion circuit is used for increasing the direct current voltage output by the first rectifying and filtering circuit, and the increased direct current voltage is applied to the control end of the first transistor.
14. The bias circuit of claim 11 wherein said first transistor is an N-type field effect transistor, said control circuit further comprising a third voltage conversion circuit;
the direct-current voltage output by the first rectifying and filtering circuit is higher than the breakdown voltage of the first transistor, and the third voltage conversion circuit is used for reducing the direct-current voltage output by the first rectifying and filtering circuit, and the reduced direct-current voltage is applied to the control end of the first transistor; or,
The direct current voltage output by the first rectifying and filtering circuit is lower than the conducting voltage of the first transistor, the third voltage conversion circuit is used for increasing the direct current voltage output by the first rectifying and filtering circuit, and the increased direct current voltage is applied to the control end of the first transistor.
15. The bias circuit of claim 11 wherein said control circuit further comprises a fourth voltage conversion circuit for regulating and controlling the magnitude of a voltage applied to a control terminal of said first transistor.
16. The bias circuit of claim 8 further comprising a control circuit coupled with the first resistance circuit to control a resistance value of the first resistance circuit.
17. The bias circuit of claim 16 wherein said control circuit is configured to adjust a resistance of said first resistor circuit based on an output power of said power amplifier circuit.
18. The biasing circuit of claim 7, wherein the first shunt subcircuit further comprises a first diode connected in series with the first transistor.
19. A bias circuit for a power amplifier, the bias circuit comprising:
a bias sub-circuit comprising a bias transistor, a first terminal of the bias transistor being coupled to a bias control terminal, a second terminal of the bias transistor being coupled to a power supply terminal, a third terminal of the bias transistor being for providing a bias current to the power amplifying circuit;
and the second shunt sub-circuit is used for shunting the current output by the third end of the bias transistor.
20. The bias circuit of claim 19 wherein said bias circuit includes a plurality of said bias subcircuits, wherein a third terminal of a bias transistor in at least some of said bias subcircuits is coupled with a first terminal of a respective second shunt subcircuit.
21. The bias circuit of claim 20 wherein at least two of said second shunt subcircuits each have a different current shunted from a corresponding said bias transistor.
22. The biasing circuit of claim 19, wherein the second shunt subcircuit is configured to: and when the output power of the power amplifying circuit is larger than a second power threshold value, switching to a communication state.
23. The biasing circuit of claim 22, wherein the second shunt subcircuit is further configured to: and when the output power of the power amplifying circuit is larger than a second power threshold value, regulating the current size shunted from the bias transistor according to the output power.
24. The bias circuit of any one of claims 19-23 wherein the second shunt subcircuit comprises a second transistor, a control terminal of the second transistor being configured to receive a control signal to control the second transistor to be turned on or off in accordance with the control signal.
25. The bias circuit of claim 24 wherein said second shunt subcircuit further comprises a second resistive circuit, said second resistive circuit being in series with said second transistor.
26. The bias circuit of claim 25 further comprising a control circuit coupled to a control terminal of the second transistor to control the second transistor to turn on or off.
27. The bias circuit of claim 26 wherein said control circuit is further configured to adjust a voltage applied to a control terminal of said second transistor based on an output power of said power amplifying circuit.
28. The bias circuit of claim 25 further comprising a control circuit coupled with the second resistance circuit to control a resistance value of the second resistance circuit.
29. The bias circuit of claim 28 wherein said control circuit is configured to adjust a resistance of said second resistor circuit based on an output power of said power amplifier circuit.
30. The bias circuit of any one of claims 19-23, wherein the bias circuit further comprises:
the first end of the first shunt sub-circuit is coupled with the power supply end, the second end of the first shunt sub-circuit is grounded, and the first shunt sub-circuit is used for shunting current output by the power supply end.
31. A power amplifier, comprising: a power amplifying circuit and the bias circuit of any one of claims 1-30 for providing a bias current to the power amplifying circuit.
32. The power amplifier of claim 31, wherein the bias circuit comprises a plurality of bias subcircuits, at least two of the bias subcircuits being configured to provide bias currents to different ones of the power amplification circuits, or at least two of the bias subcircuits being configured to provide bias currents to different bias terminals of the same power amplification circuit.
33. A radio frequency front end module comprising the bias circuit of the power amplifier of any one of claims 1-30 or comprising the power amplifier of any one of claims 31-32.
CN202311205000.0A 2023-09-18 2023-09-18 Power amplifier, bias circuit thereof and radio frequency front end module Pending CN117394800A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311205000.0A CN117394800A (en) 2023-09-18 2023-09-18 Power amplifier, bias circuit thereof and radio frequency front end module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311205000.0A CN117394800A (en) 2023-09-18 2023-09-18 Power amplifier, bias circuit thereof and radio frequency front end module

Publications (1)

Publication Number Publication Date
CN117394800A true CN117394800A (en) 2024-01-12

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