CN117393596A - Semiconductor device and method of manufacturing semiconductor device - Google Patents
Semiconductor device and method of manufacturing semiconductor device Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 287
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 38
- 150000004767 nitrides Chemical class 0.000 claims abstract description 192
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 229910002601 GaN Inorganic materials 0.000 claims description 23
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical group [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 18
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical group [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 269
- 239000000463 material Substances 0.000 description 16
- 150000001875 compounds Chemical class 0.000 description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 239000011231 conductive filler Substances 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- AJGDITRVXRPLBY-UHFFFAOYSA-N aluminum indium Chemical compound [Al].[In] AJGDITRVXRPLBY-UHFFFAOYSA-N 0.000 description 2
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910021480 group 4 element Inorganic materials 0.000 description 2
- 229910021478 group 5 element Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
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- 238000011161 development Methods 0.000 description 1
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
- H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
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- Junction Field-Effect Transistors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本发明提供一种半导体器件以及半导体器件的制造方法，半导体器件包括：半导体衬底；第一氮化物半导体层，设置于半导体衬底上；第二氮化物半导体层，设置于所述第一氮化物半导体层上；第三氮化物半导体层，设置于所述第二氮化物半导体层上；栅极电极，设置于所述第三氮化物半导体层上；源极电极和漏极电极，所述源极电极和所述漏极电极均设置于所述第二氮化物半导体层上；其中，所述第二氮化物半导体层开设有凹槽，所述凹槽与所述栅极电极之间的距离小于所述凹槽与所述漏极电极之间的距离，通过在第二氮化物半导体层开设凹槽，可以降低第二氮化物半导体层在凹槽区域的氮化物浓度，从而降低尖端电势，提高耐压强度。
The invention provides a semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device includes: a semiconductor substrate; a first nitride semiconductor layer disposed on the semiconductor substrate; a second nitride semiconductor layer disposed on the first nitride semiconductor layer. on the nitride semiconductor layer; a third nitride semiconductor layer disposed on the second nitride semiconductor layer; a gate electrode disposed on the third nitride semiconductor layer; a source electrode and a drain electrode, The source electrode and the drain electrode are both disposed on the second nitride semiconductor layer; wherein the second nitride semiconductor layer has a groove, and the gap between the groove and the gate electrode The distance is smaller than the distance between the groove and the drain electrode. By forming a groove in the second nitride semiconductor layer, the nitride concentration of the second nitride semiconductor layer in the groove area can be reduced, thereby reducing the tip potential. , improve the compressive strength.
Description
技术领域Technical field
本发明涉及半导体技术领域，尤其涉及一种半导体器件以及半导体器件的制造方法。The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor device and a manufacturing method of the semiconductor device.
背景技术Background technique
近年来，对高电子迁移率晶体管(high-electron-mobility transistors，HEMTs)的深入研究非常普遍，尤其是在大功率开关和高频应用方面。对HEMT功率器件而言，击穿电压是一项非常关键的性能参数。In recent years, in-depth research on high-electron-mobility transistors (HEMTs) has been very common, especially in high-power switching and high-frequency applications. For HEMT power devices, breakdown voltage is a very critical performance parameter.
因此，如何提高HEMT功率器件的耐压强度十分重要。Therefore, how to improve the withstand voltage strength of HEMT power devices is very important.
发明内容Contents of the invention
针对现有技术存在的问题，本发明提供一种半导体器件以及半导体器件的制造方法，能够提高HEMT功率器件的耐压强度。In view of the problems existing in the prior art, the present invention provides a semiconductor device and a manufacturing method of the semiconductor device, which can improve the withstand voltage strength of the HEMT power device.
本发明提供一种半导体器件，包括：The invention provides a semiconductor device, including:
半导体衬底；semiconductor substrate;
第一氮化物半导体层，设置于半导体衬底上；A first nitride semiconductor layer is provided on the semiconductor substrate;
第二氮化物半导体层，设置于所述第一氮化物半导体层上；A second nitride semiconductor layer is provided on the first nitride semiconductor layer;
第三氮化物半导体层，设置于所述第二氮化物半导体层上；A third nitride semiconductor layer is provided on the second nitride semiconductor layer;
栅极电极，设置于所述第三氮化物半导体层上；A gate electrode disposed on the third nitride semiconductor layer;
源极电极和漏极电极，所述源极电极和所述漏极电极均设置于所述第二氮化物半导体层上；A source electrode and a drain electrode, both of which are disposed on the second nitride semiconductor layer;
其中，所述第二氮化物半导体层开设有凹槽，所述凹槽与所述栅极电极之间的距离小于所述凹槽与所述漏极电极之间的距离。Wherein, the second nitride semiconductor layer is provided with a groove, and the distance between the groove and the gate electrode is smaller than the distance between the groove and the drain electrode.
根据本发明提供的一种半导体器件，所述凹槽开设于所述第二氮化物半导体层的第一部分和第二部分之间，所述第一部分为所述第三氮化物半导体层覆盖所述第二氮化物半导体层的部分，所述第二部分为所述漏极电极覆盖所述第二氮化物半导体层的部分。According to a semiconductor device provided by the present invention, the groove is opened between a first part and a second part of the second nitride semiconductor layer, and the first part covers the third nitride semiconductor layer. A portion of the second nitride semiconductor layer, the second portion being a portion of the drain electrode covering the second nitride semiconductor layer.
根据本发明提供的一种半导体器件，所述凹槽开设于所述第一部分和所述第二部分之间靠近所述第一部分的一侧。According to a semiconductor device provided by the present invention, the groove is opened between the first part and the second part on a side close to the first part.
根据本发明提供的一种半导体器件，所述凹槽的边缘与所述第一部分的边缘邻接。According to a semiconductor device provided by the present invention, an edge of the groove is adjacent to an edge of the first part.
根据本发明提供的一种半导体器件，所述第一氮化物半导体层为氮化镓层。According to a semiconductor device provided by the present invention, the first nitride semiconductor layer is a gallium nitride layer.
根据本发明提供的一种半导体器件，所述第二氮化物半导体层为氮化铝镓层。According to a semiconductor device provided by the present invention, the second nitride semiconductor layer is an aluminum gallium nitride layer.
根据本发明提供的一种半导体器件，所述第三氮化物半导体层为P型氮化镓层。According to a semiconductor device provided by the present invention, the third nitride semiconductor layer is a P-type gallium nitride layer.
根据本发明提供的一种半导体器件，所述凹槽的深度小于所述第二氮化物半导体层的厚度。According to a semiconductor device provided by the present invention, the depth of the groove is smaller than the thickness of the second nitride semiconductor layer.
根据本发明提供的一种半导体器件，还包括：A semiconductor device provided according to the invention also includes:
第三介电层，所述第三介电层覆盖所述栅极电极、所述源极电极、所述漏极电极和所述第二氮化物半导体层。A third dielectric layer covering the gate electrode, the source electrode, the drain electrode and the second nitride semiconductor layer.
本发明还提供了一种半导体器件的制造方法，包括：The invention also provides a method for manufacturing a semiconductor device, including:
形成半导体衬底；forming a semiconductor substrate;
在半导体衬底上形成第一氮化物半导体层；forming a first nitride semiconductor layer on the semiconductor substrate;
在所述第一氮化物半导体层上形成第二氮化物半导体层；forming a second nitride semiconductor layer on the first nitride semiconductor layer;
在所述第二氮化物半导体层上形成第三氮化物半导体层；forming a third nitride semiconductor layer on the second nitride semiconductor layer;
在所述第三氮化物半导体层上形成栅极电极；forming a gate electrode on the third nitride semiconductor layer;
在所述第二氮化物半导体层开设凹槽；Create a groove in the second nitride semiconductor layer;
在所述第二氮化物半导体层上形成源极电极和漏极电极，其中，所述凹槽与所述栅极电极之间的距离小于所述凹槽与所述漏极电极之间的距离。A source electrode and a drain electrode are formed on the second nitride semiconductor layer, wherein a distance between the groove and the gate electrode is smaller than a distance between the groove and the drain electrode .
根据本发明提供的一种半导体器件的制造方法，所述在所述第三氮化物半导体层上形成栅极电极，包括：According to a method of manufacturing a semiconductor device provided by the present invention, forming a gate electrode on the third nitride semiconductor layer includes:
在所述第三氮化物半导体层上形成栅极层；forming a gate layer on the third nitride semiconductor layer;
在所述栅极层上形成第一介电层；forming a first dielectric layer on the gate layer;
在所述第一介电层上形成第一光罩层；forming a first photomask layer on the first dielectric layer;
对所述第一光罩层进行图形化处理，以得到第一图形化光罩层；Perform patterning processing on the first mask layer to obtain a first patterned mask layer;
基于所述第一图形化光罩层对所述第一介电层和所述栅极层进行刻蚀，以得到所述栅极电极和刻蚀后的第一介电层；Etching the first dielectric layer and the gate layer based on the first patterned photomask layer to obtain the gate electrode and the etched first dielectric layer;
去除所述第一图形化光罩层。The first patterned mask layer is removed.
根据本发明提供的一种半导体器件的制造方法，所述在所述第二氮化物半导体层开设凹槽，包括：According to a method for manufacturing a semiconductor device provided by the present invention, forming a groove in the second nitride semiconductor layer includes:
在所述刻蚀后的第一介电层上形成第二介电层，所述第二介电层覆盖所述栅极电极和所述刻蚀后的第一介电层；forming a second dielectric layer on the etched first dielectric layer, the second dielectric layer covering the gate electrode and the etched first dielectric layer;
对所述第二介电层进行刻蚀，得到刻蚀后的第二介电层；Etch the second dielectric layer to obtain an etched second dielectric layer;
对所述第三氮化物半导体层进行刻蚀，得到刻蚀后的第三氮化物半导体层；Etch the third nitride semiconductor layer to obtain an etched third nitride semiconductor layer;
在所述刻蚀后的第二介电层上形成第二光罩层，以及在所述第二氮化物半导体层上形成第三光罩层，其中，所述第二氮化物半导体层的部分区域未被所述第二光罩层和所述第三光罩层覆盖；A second photomask layer is formed on the etched second dielectric layer, and a third photomask layer is formed on the second nitride semiconductor layer, wherein a portion of the second nitride semiconductor layer The area is not covered by the second photomask layer and the third photomask layer;
对所述第二光罩层和所述第三光罩层进行图形化处理，以得到第二图形化光罩层和第三图形化光罩层；Perform patterning processing on the second mask layer and the third mask layer to obtain a second patterned mask layer and a third patterned mask layer;
基于所述第二图形化光罩层和所述第三图形化光罩层对所述第二氮化物半导体层进行刻蚀，以得到所述凹槽；Etching the second nitride semiconductor layer based on the second patterned mask layer and the third patterned mask layer to obtain the groove;
去除所述第二图形化光罩层和所述第三图形化光罩层。The second patterned mask layer and the third patterned mask layer are removed.
根据本发明提供的一种半导体器件的制造方法，在所述去除所述第二图形化光罩层和所述第三图形化光罩层之后，所述方法还包括：According to a method for manufacturing a semiconductor device provided by the present invention, after removing the second patterned mask layer and the third patterned mask layer, the method further includes:
去除所述刻蚀后的第一介电层和所述刻蚀后的第二介电层。The etched first dielectric layer and the etched second dielectric layer are removed.
根据本发明提供的一种半导体器件的制造方法，所述第一氮化物半导体层为氮化镓层。According to a method of manufacturing a semiconductor device provided by the present invention, the first nitride semiconductor layer is a gallium nitride layer.
根据本发明提供的一种半导体器件的制造方法，所述第二氮化物半导体层为氮化铝镓层。According to a method for manufacturing a semiconductor device provided by the present invention, the second nitride semiconductor layer is an aluminum gallium nitride layer.
根据本发明提供的一种半导体器件的制造方法，所述第三氮化物半导体层为P型氮化镓层。According to a method for manufacturing a semiconductor device provided by the present invention, the third nitride semiconductor layer is a P-type gallium nitride layer.
根据本发明提供的一种半导体器件的制造方法，所述方法还包括：According to a method for manufacturing a semiconductor device provided by the present invention, the method further includes:
在所述第二氮化物半导体层上形成第三介电层，所述第三介电层覆盖所述栅极电极、所述源极电极、所述漏极电极和所述第二氮化物半导体层。A third dielectric layer is formed on the second nitride semiconductor layer, and the third dielectric layer covers the gate electrode, the source electrode, the drain electrode and the second nitride semiconductor layer. layer.
本发明实施例的半导体器件以及半导体器件的制造方法，半导体器件包括：半导体衬底；第一氮化物半导体层，设置于半导体衬底上；第二氮化物半导体层，设置于所述第一氮化物半导体层上；第三氮化物半导体层，设置于所述第二氮化物半导体层上；栅极电极，设置于所述第三氮化物半导体层上；源极电极和漏极电极，所述源极电极和所述漏极电极均设置于所述第二氮化物半导体层上；其中，所述第二氮化物半导体层开设有凹槽，所述凹槽与所述栅极电极之间的距离小于所述凹槽与所述漏极电极之间的距离，通过在第二氮化物半导体层开设凹槽，可以降低第二氮化物半导体层在凹槽区域的氮化物浓度，从而降低尖端电势，提高耐压强度。According to the semiconductor device and the manufacturing method of the semiconductor device according to the embodiment of the present invention, the semiconductor device includes: a semiconductor substrate; a first nitride semiconductor layer disposed on the semiconductor substrate; a second nitride semiconductor layer disposed on the first nitride semiconductor layer. on the nitride semiconductor layer; a third nitride semiconductor layer disposed on the second nitride semiconductor layer; a gate electrode disposed on the third nitride semiconductor layer; a source electrode and a drain electrode, The source electrode and the drain electrode are both disposed on the second nitride semiconductor layer; wherein the second nitride semiconductor layer has a groove, and the gap between the groove and the gate electrode The distance is smaller than the distance between the groove and the drain electrode. By forming a groove in the second nitride semiconductor layer, the nitride concentration of the second nitride semiconductor layer in the groove area can be reduced, thereby reducing the tip potential. , improve the compressive strength.
附图说明Description of drawings
为了更清楚地说明本发明或现有技术中的技术方案，下面将对发明实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本发明的一些发明实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments of the invention or the prior art. Obviously, the drawings in the following description are: For some invention embodiments of the present invention, those of ordinary skill in the art can also obtain other drawings based on these drawings without exerting creative efforts.
图1是本发明实施例提供的半导体器件的垂直截面图；Figure 1 is a vertical cross-sectional view of a semiconductor device provided by an embodiment of the present invention;
图2是本发明实施例提供的半导体器件的制造方法的流程示意图；Figure 2 is a schematic flowchart of a manufacturing method of a semiconductor device provided by an embodiment of the present invention;
图3是本发明实施例提供的半导体器件制造过程中的中间结构的垂直截面图之一；Figure 3 is one of the vertical cross-sectional views of an intermediate structure during the manufacturing process of a semiconductor device provided by an embodiment of the present invention;
图4是本发明实施例提供的半导体器件制造过程中的中间结构的垂直截面图之二；Figure 4 is the second vertical cross-sectional view of an intermediate structure during the manufacturing process of a semiconductor device provided by an embodiment of the present invention;
图5是本发明实施例提供的半导体器件制造过程中的中间结构的垂直截面图之三；Figure 5 is the third vertical cross-sectional view of the intermediate structure during the manufacturing process of the semiconductor device provided by the embodiment of the present invention;
图6是本发明实施例提供的半导体器件制造过程中的中间结构的垂直截面图之四；Figure 6 is the fourth vertical cross-sectional view of an intermediate structure during the manufacturing process of a semiconductor device provided by an embodiment of the present invention;
图7是本发明实施例提供的半导体器件制造过程中的中间结构的垂直截面图之五；7 is a fifth vertical cross-sectional view of an intermediate structure during the manufacturing process of a semiconductor device provided by an embodiment of the present invention;
图8是本发明实施例提供的半导体器件制造过程中的中间结构的垂直截面图之六；Figure 8 is a sixth vertical cross-sectional view of an intermediate structure during the manufacturing process of a semiconductor device provided by an embodiment of the present invention;
图9是本发明实施例提供的半导体器件制造过程中的中间结构的垂直截面图之七；Figure 9 is a seventh vertical cross-sectional view of an intermediate structure during the manufacturing process of a semiconductor device provided by an embodiment of the present invention;
图10是本发明实施例提供的半导体器件制造过程中的中间结构的垂直截面图之八；Figure 10 is an eighth vertical cross-sectional view of an intermediate structure during the manufacturing process of a semiconductor device provided by an embodiment of the present invention;
图11是本发明实施例提供的半导体器件制造过程中的中间结构的垂直截面图之九；Figure 11 is a ninth vertical cross-sectional view of an intermediate structure during the manufacturing process of a semiconductor device provided by an embodiment of the present invention;
图12是本发明实施例提供的半导体器件制造过程中的中间结构的垂直截面图之十。FIG. 12 is a tenth vertical cross-sectional view of an intermediate structure during the manufacturing process of a semiconductor device provided by an embodiment of the present invention.
具体实施方式Detailed ways
为使本发明的目的、技术方案和优点更加清楚，下面将结合本发明中的附图，对本发明中的技术方案进行清楚、完整地描述，显然，所描述的发明实施例是本发明一部分发明实施例，而不是全部的发明实施例。基于本发明中的发明实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他发明实施例，都属于本发明保护的范围。In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the present invention. Obviously, the described embodiments of the invention are part of the present invention. Examples, not all examples of the invention. Based on the inventive embodiments of the present invention, all other inventive embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of the present invention.
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层、掺杂类型和/或部分，这些元件、部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分；举例来说，可以将第一掺杂类型成为第二掺杂类型，且类似地，可以将第二掺杂类型成为第一掺杂类型；第一掺杂类型与第二掺杂类型为不同的掺杂类型，譬如，第一掺杂类型可以为P型且第二掺杂类型可以为N型，或第一掺杂类型可以为N型且第二掺杂类型可以为P型。It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer. A layer may be on, adjacent to, connected to, or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. layer. It will be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or Sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the invention; for example, a first element, component, region, layer, doping type or section could be termed a second element, component, region, layer or section without departing from the teachings of the present invention; The first doping type becomes the second doping type, and similarly, the second doping type can become the first doping type; the first doping type and the second doping type are different doping types, for example, The first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。Spatial relational terms such as "under", "under", "under", "under", "on", "above", etc., in This may be used to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "under" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" may include both upper and lower orientations. Additionally, the device may be otherwise oriented (eg, rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应当理解的是，术语“包括/包含”或“具有”等指定所陈述的特征、整体、步骤、操作、组件、部分或它们的组合的存在，但是不排除存在或添加一个或更多个其他特征、整体、步骤、操作、组件、部分或它们的组合的可能性。同时，在本说明书中，术语“和/或”包括相关所列项目的任何及所有组合。As used herein, the singular forms "a," "an," and "the" may include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the terms "comprising" or "having" and the like specify the presence of stated features, integers, steps, operations, components, parts or combinations thereof, but do not exclude the presence or addition of one or more Possibility of other features, integers, steps, operations, components, parts or combinations thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.
请参阅图1，图1是本发明实施例提供的半导体器件的垂直截面图。如图1所述，本发明实施例的半导体器件包括半导体衬底110、第一氮化物半导体层120、第二氮化物半导体层130、第三氮化物半导体层140、栅极电极150、源极电极(图中未示出)和漏极电极(图中未示出)，其中：Please refer to FIG. 1 , which is a vertical cross-sectional view of a semiconductor device provided by an embodiment of the present invention. As shown in FIG. 1 , the semiconductor device according to the embodiment of the present invention includes a semiconductor substrate 110 , a first nitride semiconductor layer 120 , a second nitride semiconductor layer 130 , a third nitride semiconductor layer 140 , a gate electrode 150 , and a source electrode. electrode (not shown in the figure) and drain electrode (not shown in the figure), where:
第一氮化物半导体层120设置于半导体衬底110上。第二氮化物半导体层130设置于所述第一氮化物半导体层120上。第三氮化物半导体层140设置于所述第二氮化物半导体层130上。栅极电极150设置于所述第三氮化物半导体层140上。所述源极电极和所述漏极电极均设置于所述第二氮化物半导体层130上。所述第二氮化物半导体层130开设有凹槽131，所述凹槽131与所述栅极电极之间的距离小于所述凹槽131与所述漏极电极之间的距离。The first nitride semiconductor layer 120 is provided on the semiconductor substrate 110 . The second nitride semiconductor layer 130 is disposed on the first nitride semiconductor layer 120 . The third nitride semiconductor layer 140 is disposed on the second nitride semiconductor layer 130 . The gate electrode 150 is disposed on the third nitride semiconductor layer 140 . The source electrode and the drain electrode are both disposed on the second nitride semiconductor layer 130 . The second nitride semiconductor layer 130 is provided with a groove 131 , and the distance between the groove 131 and the gate electrode is smaller than the distance between the groove 131 and the drain electrode.
其中，半导体衬底110的示例性材料可包括，例如但不限于硅、硅锗(SiGe)、碳化硅(SiC)、砷化镓(GaAs)、p掺杂硅、n掺杂硅、蓝宝石、绝缘体上半导体(例如绝缘体上硅(silicon on insulator，SOI))或其他合适的半导体材料。在一些发明实施例中，半导体衬底110可包括例如但不限于第III族元素、第IV族元素、第V族元素或其组合(例如，III-V族化合物)。在其他发明实施例中，半导体衬底110可包括例如但不限于，一个或多个其他特征，例如掺杂区、埋层、外延(epitaxy)层或其组合等，在此不做限定。Wherein, exemplary materials of the semiconductor substrate 110 may include, for example but not limited to, silicon, silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), p-doped silicon, n-doped silicon, sapphire, Semiconductor on insulator (such as silicon on insulator (SOI)) or other suitable semiconductor material. In some inventive embodiments, the semiconductor substrate 110 may include, for example, but not limited to, Group III elements, Group IV elements, Group V elements, or combinations thereof (eg, Group III-V compounds). In other invention embodiments, the semiconductor substrate 110 may include, for example, but not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial layer or a combination thereof, which are not limited here.
其中，第一氮化物半导体层120和第三氮化物半导体层140示例性材料可包括但不限于，氮化物或III-V族化合物，例如氮化镓(GaN)、氮化铝(AlN)、氮化铟(InN)、InxAlyGa(1–x–y)N(其中x+y≤1)、AlyGa(1–y)N(其中y≤1)。Exemplary materials of the first nitride semiconductor layer 120 and the third nitride semiconductor layer 140 may include, but are not limited to, nitride or III-V compounds, such as gallium nitride (GaN), aluminum nitride (AlN), Indium nitride (InN), InxAlyGa(1–x–y)N (where x+y≤1), AlyGa(1–y)N (where y≤1).
其中，第二氮化物半导体层130可以包括III-V族化合物。III-V族化合物可包括例如但不限于铝、镓、铟、氮或其组合。因此，第二氮化物半导体层130的示例性材料可进一步包括例如但不限于氮化镓(GaN)、氮化铝(AlN)、氮化铝镓(AlGaN)、氮化铝铟镓(AlInGaN)或其组合。Wherein, the second nitride semiconductor layer 130 may include a III-V group compound. Group III-V compounds may include, for example, but not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Therefore, exemplary materials of the second nitride semiconductor layer 130 may further include, for example, but not limited to, gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium gallium nitride (AlInGaN). or combination thereof.
在一种可能的实现中，第一氮化物半导体层120为氮化镓层。In a possible implementation, the first nitride semiconductor layer 120 is a gallium nitride layer.
在一种可能的实现中，第二氮化物半导体层130为氮化铝镓层。In a possible implementation, the second nitride semiconductor layer 130 is an aluminum gallium nitride layer.
在一种可能的实现中，第三氮化物半导体层140为P型氮化镓层。In one possible implementation, the third nitride semiconductor layer 140 is a P-type gallium nitride layer.
在本发明实施例中，具体的，第二氮化物半导体层130开设有凹槽131，则第二氮化物半导体层130在凹槽131区域的厚度是小于其他区域的厚度，由此凹槽131区域的氮化物浓度能够降低，从而降低尖端电势，提高耐压强度。In the embodiment of the present invention, specifically, the second nitride semiconductor layer 130 is provided with a groove 131, so the thickness of the second nitride semiconductor layer 130 in the groove 131 region is smaller than the thickness of other regions, so the groove 131 The nitride concentration in the area can be reduced, thereby reducing the tip potential and improving the withstand voltage strength.
可以理解的是，当第二氮化物半导体层130为氮化铝镓层，在第二氮化物半导体层130开设凹槽131能够降低第二氮化物半导体层130在凹槽131区域的AlGaN浓度。It can be understood that when the second nitride semiconductor layer 130 is an aluminum gallium nitride layer, opening the groove 131 in the second nitride semiconductor layer 130 can reduce the AlGaN concentration of the second nitride semiconductor layer 130 in the groove 131 region.
其中，栅极电极150、源极电极和漏极电极可以包括例如但不限于金属、合金、掺杂的半导体材料(例如掺杂晶体硅)、诸如硅化物以及氮化物等化合物、其他导体材料或其组合。每一个电极的示例性材料可以包括，例如，但不限于钛(Ti)、铝硅(AlSi)、氮化钛(TiN)或其组合。每一个电极可以是相同或不同组合物的单层或多个层。在一些实施例中，电极与氮化物半导体层形成欧姆接触。通过将钛(Ti)、铝(Al)或其他合适的材料应用到电极上，可以实现欧姆接触。在一些实施例中，每一个电极中由至少一个共形层以及导电填料构成。共形层可以包裹导电填料。共形层的示例性材料，例如但不限于钛(Ti)、钽(Ta)、氮化钛(TiN)、铝(Al)、金(Au)、铝硅(AlSi)、镍(Ni)、铂(Pt)或其组合。导电填料的示例性材料可以包括例如但不限于，铝硅(AlSi)、铝铜(AlCu)或其组合，在此不做限定。Wherein, the gate electrode 150, the source electrode and the drain electrode may include, for example but not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon), compounds such as silicides and nitrides, other conductor materials, or its combination. Exemplary materials for each electrode may include, for example, but not limited to, titanium (Ti), aluminum silicon (AlSi), titanium nitride (TiN), or combinations thereof. Each electrode may be a single layer or multiple layers of the same or different compositions. In some embodiments, the electrode forms an ohmic contact with the nitride semiconductor layer. Ohmic contact can be achieved by applying titanium (Ti), aluminum (Al) or other suitable materials to the electrodes. In some embodiments, each electrode is composed of at least one conformal layer and conductive filler. The conformal layer can wrap the conductive filler. Exemplary materials of the conformal layer include, but are not limited to, titanium (Ti), tantalum (Ta), titanium nitride (TiN), aluminum (Al), gold (Au), aluminum silicon (AlSi), nickel (Ni), Platinum (Pt) or combinations thereof. Exemplary materials of the conductive filler may include, but are not limited to, aluminum silicon (AlSi), aluminum copper (AlCu), or combinations thereof, which are not limited here.
本发明实施例的半导体器件，半导体衬底110；第一氮化物半导体层120，设置于半导体衬底110上；第二氮化物半导体层130，设置于所述第一氮化物半导体层120上；第三氮化物半导体层140，设置于所述第二氮化物半导体层130上；栅极电极150，设置于所述第三氮化物半导体层140上；源极电极和漏极电极，所述源极电极和所述漏极电极均设置于所述第二氮化物半导体层130上；其中，所述第二氮化物半导体层130开设有凹槽131，所述凹槽131与所述栅极电极之间的距离小于所述凹槽131与所述漏极电极之间的距离，通过在第二氮化物半导体层130开设凹槽131，可以降低第二氮化物半导体层130在凹槽131区域的氮化物浓度，从而降低尖端电势，提高耐压强度。The semiconductor device according to the embodiment of the present invention includes a semiconductor substrate 110; a first nitride semiconductor layer 120 disposed on the semiconductor substrate 110; a second nitride semiconductor layer 130 disposed on the first nitride semiconductor layer 120; The third nitride semiconductor layer 140 is provided on the second nitride semiconductor layer 130; the gate electrode 150 is provided on the third nitride semiconductor layer 140; the source electrode and the drain electrode, the source electrode 150 is provided on the third nitride semiconductor layer 140. The electrode electrode and the drain electrode are both disposed on the second nitride semiconductor layer 130; wherein the second nitride semiconductor layer 130 is provided with a groove 131, and the groove 131 is connected to the gate electrode. The distance between the groove 131 and the drain electrode is smaller than the distance between the groove 131 and the drain electrode. By forming the groove 131 in the second nitride semiconductor layer 130, the resistance of the second nitride semiconductor layer 130 in the groove 131 region can be reduced. nitride concentration, thereby reducing the tip potential and improving the withstand voltage strength.
请继续参考图1。在一种可能的实现中，本发明实施例的半导体器件还包括：Please continue to refer to Figure 1. In a possible implementation, the semiconductor device according to the embodiment of the present invention further includes:
第三介电层190，所述第三介电层190覆盖所述栅极电极150、所述源极电极、所述漏极电极和所述第二氮化物半导体层130。A third dielectric layer 190 covers the gate electrode 150 , the source electrode, the drain electrode and the second nitride semiconductor layer 130 .
其中，介电层材料可以包括，例如但不限于，介电材料。例如，介电层可包括至少一种氮基介电材料，例如氮化硅(Si3N4)。The dielectric layer material may include, for example, but not limited to, dielectric materials. For example, the dielectric layer may include at least one nitrogen-based dielectric material, such as silicon nitride (Si3N4).
需要说明的是，所述凹槽131与所述栅极电极之间的距离小于所述凹槽131与所述漏极电极之间的距离，可以是凹槽131设置在漏极电极与源极电极之间的连线上靠近所述漏极电极的一侧，也可以是凹槽131设置在漏极电极与源极电极之间的连线的延长线上，在此不做限定。It should be noted that the distance between the groove 131 and the gate electrode is smaller than the distance between the groove 131 and the drain electrode. The groove 131 may be disposed between the drain electrode and the source electrode. On the side of the connection between the electrodes that is close to the drain electrode, the groove 131 may also be provided on an extension of the connection between the drain electrode and the source electrode, which is not limited here.
在一种可能的实现中，所述凹槽131开设于所述第二氮化物半导体层130的第一部分和第二部分之间。所述第一部分为所述第三氮化物半导体层140覆盖所述第二氮化物半导体层130的部分，所述第二部分为所述漏极电极覆盖所述第二氮化物半导体层130的部分。In a possible implementation, the groove 131 is opened between the first part and the second part of the second nitride semiconductor layer 130 . The first part is the part where the third nitride semiconductor layer 140 covers the second nitride semiconductor layer 130 , and the second part is the part where the drain electrode covers the second nitride semiconductor layer 130 .
其中，覆盖可以是指俯视该半导体器件时，处于上层的元件所遮挡的下层元件的部分。在本发明实施例中，第一部分可以是指俯视该半导体器件时，第三氮化物半导体层140所遮挡的第二氮化物半导体层130的部分。第二部分可以是指俯视该半导体器件时，漏极电极覆盖所述第二氮化物半导体层130的部分。The coverage may refer to the portion of the lower-layer component that is blocked by the upper-layer component when the semiconductor device is viewed from above. In the embodiment of the present invention, the first part may refer to the part of the second nitride semiconductor layer 130 that is blocked by the third nitride semiconductor layer 140 when the semiconductor device is viewed from above. The second part may refer to the part where the drain electrode covers the second nitride semiconductor layer 130 when the semiconductor device is viewed from above.
本发明实施例的技术方案，通过在第二氮化物半导体层130的第一部分和第二部分之间开设凹槽131，能够实现降低第二氮化物半导体层130在凹槽131区域的氮化物浓度。According to the technical solution of the embodiment of the present invention, by opening a groove 131 between the first part and the second part of the second nitride semiconductor layer 130, the nitride concentration of the second nitride semiconductor layer 130 in the groove 131 region can be reduced. .
在一种可能的实现中，所述凹槽131开设于所述第一部分和所述第二部分之间靠近所述第一部分的一侧。In a possible implementation, the groove 131 is opened between the first part and the second part on a side close to the first part.
由于凹槽131距离第一部分越近，则耐压强度的提升效果越佳，因此本实施例通过在第一部分和所述第二部分之间靠近所述第一部分的一侧开设凹槽131，可以提高耐压强度。Since the closer the groove 131 is to the first part, the better the effect of improving the compressive strength is. Therefore, in this embodiment, the groove 131 is provided between the first part and the second part on one side close to the first part. Improve compressive strength.
在一种可能的实现中，所述凹槽131的边缘与所述第一部分的边缘邻接。In one possible implementation, the edge of the groove 131 abuts the edge of the first part.
本发明实施例的技术方案，通过将凹槽131开设于第一部分的边缘，可以最大化耐压强度的提升。The technical solution of the embodiment of the present invention can maximize the improvement of the compressive strength by opening the groove 131 at the edge of the first part.
在一种可能的实现中，所述凹槽131的深度小于所述第二氮化物半导体层130的厚度。In a possible implementation, the depth of the groove 131 is smaller than the thickness of the second nitride semiconductor layer 130 .
本实施例的技术方案，通过将凹槽131的深度设置为小于第二氮化物半导体层130的厚度，可以使得第二氮化物半导体层130是导通的。In the technical solution of this embodiment, by setting the depth of the groove 131 to be smaller than the thickness of the second nitride semiconductor layer 130, the second nitride semiconductor layer 130 can be made conductive.
以下对于上述发明实施例的半导体器件的制造方法进行说明。The manufacturing method of the semiconductor device according to the embodiment of the invention will be described below.
请参阅图2-12。其中，图2是本发明实施例提供的半导体器件的制造方法的流程示意图。如图3-12是本发明实施例提供的半导体器件制造过程中的中间结构的垂直截面图。See Figure 2-12. 2 is a schematic flowchart of a manufacturing method of a semiconductor device provided by an embodiment of the present invention. 3-12 is a vertical cross-sectional view of an intermediate structure during the manufacturing process of a semiconductor device provided by an embodiment of the present invention.
如图2所示的半导体器件的制造方法包括：The manufacturing method of the semiconductor device shown in Figure 2 includes:
210、形成半导体衬底110。210. Form the semiconductor substrate 110.
其中，半导体衬底110的示例性材料可包括，例如但不限于硅、硅锗(SiGe)、碳化硅(SiC)、砷化镓(GaAs)、p掺杂硅、n掺杂硅、蓝宝石、绝缘体上半导体(例如绝缘体上硅(silicon on insulator，SOI))或其他合适的半导体材料。在一些发明实施例中，半导体衬底110可包括例如但不限于第III族元素、第IV族元素、第V族元素或其组合(例如，III-V族化合物)。在其他发明实施例中，半导体衬底110可包括例如但不限于，一个或多个其他特征，例如掺杂区、埋层、外延(epitaxy)层或其组合等，在此不做限定。Wherein, exemplary materials of the semiconductor substrate 110 may include, for example but not limited to, silicon, silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), p-doped silicon, n-doped silicon, sapphire, Semiconductor on insulator (such as silicon on insulator (SOI)) or other suitable semiconductor material. In some inventive embodiments, the semiconductor substrate 110 may include, for example, but not limited to, Group III elements, Group IV elements, Group V elements, or combinations thereof (eg, Group III-V compounds). In other invention embodiments, the semiconductor substrate 110 may include, for example, but not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial layer or a combination thereof, which are not limited here.
220、在半导体衬底110上形成第一氮化物半导体层120。220. Form the first nitride semiconductor layer 120 on the semiconductor substrate 110.
230、在所述第一氮化物半导体层120上形成第二氮化物半导体层130。230. Form a second nitride semiconductor layer 130 on the first nitride semiconductor layer 120.
240、在所述第二氮化物半导体层130上形成第三氮化物半导体层140。240. Form a third nitride semiconductor layer 140 on the second nitride semiconductor layer 130.
其中，第一氮化物半导体层120和第三氮化物半导体层140示例性材料可包括但不限于，氮化物或III-V族化合物，例如氮化镓(GaN)、氮化铝(AlN)、氮化铟(InN)、InxAlyGa(1–x–y)N(其中x+y≤1)、AlyGa(1–y)N(其中y≤1)。Exemplary materials of the first nitride semiconductor layer 120 and the third nitride semiconductor layer 140 may include, but are not limited to, nitride or III-V compounds, such as gallium nitride (GaN), aluminum nitride (AlN), Indium nitride (InN), InxAlyGa(1–x–y)N (where x+y≤1), AlyGa(1–y)N (where y≤1).
其中，第二氮化物半导体层130可以包括III-V族化合物。III-V族化合物可包括例如但不限于铝、镓、铟、氮或其组合。因此，第二氮化物半导体层130的示例性材料可进一步包括例如但不限于氮化镓(GaN)、氮化铝(AlN)、氮化铝镓(AlGaN)、氮化铝铟镓(AlInGaN)或其组合。Wherein, the second nitride semiconductor layer 130 may include a III-V group compound. Group III-V compounds may include, for example, but not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Therefore, exemplary materials of the second nitride semiconductor layer 130 may further include, for example, but not limited to, gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium gallium nitride (AlInGaN). or combination thereof.
250、在所述第三氮化物半导体层140上形成栅极电极150。250. Form a gate electrode 150 on the third nitride semiconductor layer 140.
在一种可能的实现中，在所述第三氮化物半导体层140上形成栅极电极150包括：In a possible implementation, forming the gate electrode 150 on the third nitride semiconductor layer 140 includes:
在所述第三氮化物半导体层140上形成栅极层160；forming a gate layer 160 on the third nitride semiconductor layer 140;
在所述栅极层160上形成第一介电层170；forming a first dielectric layer 170 on the gate layer 160;
在所述第一介电层170上形成第一光罩层；forming a first photomask layer on the first dielectric layer 170;
对所述第一光罩层进行图形化处理，以得到第一图形化光罩层；Perform patterning processing on the first mask layer to obtain a first patterned mask layer;
基于所述第一图形化光罩层对所述第一介电层170和所述栅极层160进行刻蚀，以得到所述栅极电极150和刻蚀后的第一介电层170；Etch the first dielectric layer 170 and the gate layer 160 based on the first patterned photomask layer to obtain the gate electrode 150 and the etched first dielectric layer 170;
去除所述第一图形化光罩层。The first patterned mask layer is removed.
其中，介电层的材料可以包括，例如但不限于，介电材料。例如，介电层可包括至少一种氮基介电材料，例如氮化硅(Si3N4)。光罩层可以是可以为光刻胶层或氮化硅层、碳层等硬掩膜层。具体的，图形化处理即为光刻，包括曝光显影。图形化光罩层是指对光罩层进行图形化处理得到的。The material of the dielectric layer may include, for example, but not limited to, dielectric materials. For example, the dielectric layer may include at least one nitrogen-based dielectric material, such as silicon nitride (Si3N4). The photomask layer may be a photoresist layer or a hard mask layer such as a silicon nitride layer or a carbon layer. Specifically, the patterning process is photolithography, including exposure and development. The patterned mask layer refers to the patterned mask layer.
260、在所述第二氮化物半导体层130开设凹槽131。260. Create a groove 131 in the second nitride semiconductor layer 130 .
在一种可能的实现中，在所述第二氮化物半导体层130开设凹槽131，包括：In a possible implementation, a groove 131 is opened in the second nitride semiconductor layer 130, including:
在所述刻蚀后的第一介电层170上形成第二介电层180，所述第二介电层180覆盖所述栅极电极150和所述刻蚀后的第一介电层170；A second dielectric layer 180 is formed on the etched first dielectric layer 170 , and the second dielectric layer 180 covers the gate electrode 150 and the etched first dielectric layer 170 ;
对所述第二介电层180进行刻蚀，得到刻蚀后的第二介电层180；Etch the second dielectric layer 180 to obtain the etched second dielectric layer 180;
对所述第三氮化物半导体层140进行刻蚀，得到刻蚀后的第三氮化物半导体层140；Etch the third nitride semiconductor layer 140 to obtain the etched third nitride semiconductor layer 140;
在所述刻蚀后的第二介电层180上形成第二光罩层，以及在所述第二氮化物半导体层130上形成第三光罩层，其中，所述第二氮化物半导体层130的部分区域未被所述第二光罩层和所述第三光罩层覆盖；A second photomask layer is formed on the etched second dielectric layer 180 , and a third photomask layer is formed on the second nitride semiconductor layer 130 , wherein the second nitride semiconductor layer Part of the area 130 is not covered by the second photomask layer and the third photomask layer;
对所述第二光罩层和所述第三光罩层进行图形化处理，以得到第二图形化光罩层和第三图形化光罩层；Perform patterning processing on the second mask layer and the third mask layer to obtain a second patterned mask layer and a third patterned mask layer;
基于所述第二图形化光罩层和所述第三图形化光罩层对所述第二氮化物半导体层130进行刻蚀，以得到所述凹槽131；Etch the second nitride semiconductor layer 130 based on the second patterned mask layer and the third patterned mask layer to obtain the groove 131;
去除所述第二图形化光罩层和所述第三图形化光罩层。The second patterned mask layer and the third patterned mask layer are removed.
在本实施例中，基于所述第二图形化光罩层和所述第三图形化光罩层对所述第二氮化物半导体层130进行刻蚀，则第二氮化物半导体层130未被第二光罩层和所述第三光罩层覆盖的部分区域会被刻蚀掉，从而在该区域形成凹槽131。In this embodiment, the second nitride semiconductor layer 130 is etched based on the second patterned mask layer and the third patterned mask layer, and the second nitride semiconductor layer 130 is not etched. Partial areas covered by the second mask layer and the third mask layer will be etched away, thereby forming grooves 131 in this area.
在一种可能的实现中，在所述去除所述第二图形化光罩层和所述第三图形化光罩层之后，所述方法还包括：In a possible implementation, after removing the second patterned mask layer and the third patterned mask layer, the method further includes:
去除所述刻蚀后的第一介电层170和所述刻蚀后的第二介电层180。The etched first dielectric layer 170 and the etched second dielectric layer 180 are removed.
在一种可能的实现中，该制造方法还包括：In a possible implementation, the manufacturing method further includes:
在所述第二氮化物半导体层130上形成第三介电层190，所述第三介电层190覆盖所述栅极电极150、所述源极电极、所述漏极电极和所述第二氮化物半导体层130。A third dielectric layer 190 is formed on the second nitride semiconductor layer 130 and covers the gate electrode 150 , the source electrode, the drain electrode and the third dielectric layer 190 . Dinitride semiconductor layer 130 .
本实施例的技术方案，通过在第二氮化物半导体层130上形成第三介电层190，而第三介电层190覆盖所述栅极电极150、所述源极电极、所述漏极电极和所述第二氮化物半导体层130，从而对半导体器件的内部进行保护。The technical solution of this embodiment is to form a third dielectric layer 190 on the second nitride semiconductor layer 130, and the third dielectric layer 190 covers the gate electrode 150, the source electrode, and the drain electrode. electrode and the second nitride semiconductor layer 130 to protect the interior of the semiconductor device.
270、在所述第二氮化物半导体层130上形成源极电极和漏极电极，其中，所述凹槽131与所述栅极电极之间的距离小于所述凹槽131与所述漏极电极之间的距离。270. Form a source electrode and a drain electrode on the second nitride semiconductor layer 130, wherein the distance between the groove 131 and the gate electrode is smaller than the distance between the groove 131 and the drain electrode. distance between electrodes.
在一种可能的实现中，所述第一氮化物半导体层120为氮化镓层。In a possible implementation, the first nitride semiconductor layer 120 is a gallium nitride layer.
在一种可能的实现中，所述第二氮化物半导体层130为氮化铝镓层。In one possible implementation, the second nitride semiconductor layer 130 is an aluminum gallium nitride layer.
在一种可能的实现中，所述第三氮化物半导体层140为P型氮化镓层。In one possible implementation, the third nitride semiconductor layer 140 is a P-type gallium nitride layer.
在本实施例中，通过在形成半导体衬底110；在半导体衬底110上形成第一氮化物半导体层120；在所述第一氮化物半导体层120上形成第二氮化物半导体层130；在所述第二氮化物半导体层130上形成第三氮化物半导体层140；在所述第三氮化物半导体层140上形成栅极电极150；在所述第二氮化物半导体层130开设凹槽131；在所述第二氮化物半导体层130上形成源极电极和漏极电极，其中，所述凹槽131与所述栅极电极之间的距离小于所述凹槽131与所述漏极电极之间的距离，则制造得到的半导体器件在第二氮化物半导体层130开设有凹槽131，可以降低第二氮化物半导体层130在凹槽131区域的氮化物浓度，从而降低尖端电势，提高耐压强度。In this embodiment, by forming the semiconductor substrate 110; forming the first nitride semiconductor layer 120 on the semiconductor substrate 110; forming the second nitride semiconductor layer 130 on the first nitride semiconductor layer 120; A third nitride semiconductor layer 140 is formed on the second nitride semiconductor layer 130; a gate electrode 150 is formed on the third nitride semiconductor layer 140; a groove 131 is formed in the second nitride semiconductor layer 130. ; Form a source electrode and a drain electrode on the second nitride semiconductor layer 130, wherein the distance between the groove 131 and the gate electrode is smaller than the distance between the groove 131 and the drain electrode distance between each other, the manufactured semiconductor device has grooves 131 in the second nitride semiconductor layer 130, which can reduce the nitride concentration of the second nitride semiconductor layer 130 in the groove 131 area, thereby reducing the tip potential and improving Compressive strength.
通过以上实施例的制造方法，可以制造得到如图1所示的半导体器件。Through the manufacturing method of the above embodiment, the semiconductor device shown in FIG. 1 can be manufactured.
应该理解的是，虽然图2的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图2中的至少一部分步骤可以包括多个步骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。It should be understood that although various steps in the flowchart of FIG. 2 are shown in sequence as indicated by arrows, these steps are not necessarily executed in the order indicated by arrows. Unless explicitly stated in this article, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in Figure 2 may include multiple steps or stages. These steps or stages are not necessarily executed at the same time, but may be executed at different times. The execution order of these steps or stages is also It does not necessarily need to be performed sequentially, but may be performed in turn or alternately with other steps or at least part of steps or stages in other steps.
最后应说明的是：以上发明实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述发明实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各发明实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各发明实施例技术方案的精神和范围。Finally, it should be noted that the above inventive embodiments are only used to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing inventive embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments of the invention, or to make equivalent substitutions for some of the technical features; and these modifications or substitutions do not deviate from the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present invention. spirit and scope.
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