CN117393533A - Laminated structure of chip substrate - Google Patents

Laminated structure of chip substrate Download PDF

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Publication number
CN117393533A
CN117393533A CN202311099647.XA CN202311099647A CN117393533A CN 117393533 A CN117393533 A CN 117393533A CN 202311099647 A CN202311099647 A CN 202311099647A CN 117393533 A CN117393533 A CN 117393533A
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layer
wiring layer
paving
wiring
chip substrate
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张利丹
冯杰
夏君
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Shenzhen Pango Microsystems Co Ltd
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Shenzhen Pango Microsystems Co Ltd
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Priority to CN202311099647.XA priority Critical patent/CN117393533A/en
Publication of CN117393533A publication Critical patent/CN117393533A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The application belongs to the technical field of chip packaging and discloses a laminated structure of a chip substrate. The laminated structure of the chip substrate comprises first to sixth wiring layers from top to bottom, wherein each wiring layer comprises a core wiring area; in the core wiring area, the first wiring layer is used for paving a first power plane, the second wiring layer is used for paving a ground plane, the third wiring layer is used for paving a second power plane, the fourth wiring layer is used for paving a third power plane, the fifth wiring layer is used for paving the ground plane, and the sixth wiring layer is used for paving the first power plane. The laminated structure of the chip substrate provided by the application can realize the laying of the power plane and the ground plane of the chip substrate by only needing 6 layers of substrates, and reduces the wiring layer of the chip substrate to 6 layers, so that the total thickness of the chip substrate is reduced by nearly half, the production cost of the chip is reduced, and the thickness and the volume of a finished chip are reduced.

Description

Laminated structure of chip substrate
Technical Field
The present disclosure relates to the field of chip packaging technologies, and in particular, to a stacked structure of a chip substrate.
Background
The high-frequency high-speed chip has higher requirements on power performance and high-speed signal performance during packaging design, and in order to ensure the requirements on high-speed signals and power performance, the laminated structure of the traditional high-frequency high-speed chip substrate comprises at least 10 wiring layers, and the thickness and the volume of a finished chip obtained according to the traditional high-frequency high-speed chip substrate are larger.
Disclosure of Invention
The present application is directed to a laminated structure of chip substrates, which reduces the number of laminated chip substrates to reduce the thickness and volume of the finished chip, thereby reducing the production cost of the chip.
The chip substrate comprises first to sixth wiring layers from top to bottom, and each wiring layer comprises a core wiring area;
in the core wiring area, the first wiring layer is used for paving a first power plane, the second wiring layer is used for paving a ground plane, the third wiring layer is used for paving a second power plane, the fourth wiring layer is used for paving a third power plane, the fifth wiring layer is used for paving the ground plane, and the sixth wiring layer is used for paving the first power plane.
In some embodiments, each of the trace layers further includes a high-speed serial signal trace region and a high-speed input-output interface trace region;
in the high-speed serial signal wiring area, the first wiring layer is used for paving a fourth power plane, and a high-speed serial signal of a fan-out transmitting end, the second wiring layer is used for paving the ground plane and a fan-out clock signal, the third wiring layer is used for paving the fourth power plane and a fifth power plane, the fourth wiring layer is used for paving the ground plane, the fifth wiring layer is used for paving the fourth power plane, a high-speed serial signal of a fan-out receiving end and the clock signal of a fan-out jumper, and the sixth wiring layer is used for paving the ground plane;
in the high-speed input/output interface wiring area, the first wiring layer is used for paving a sixth power plane and fanning out a first high-speed differential signal, the second wiring layer is used for paving the ground plane, the third wiring layer is used for paving the sixth power plane, the fourth wiring layer is used for paving the ground plane, the fifth wiring layer is used for paving the sixth power plane and fanning out a second high-speed differential signal, and the sixth wiring layer is used for paving the ground plane, the first high-speed differential signal of a fanning-out jumper and the second high-speed differential signal of the fanning-out jumper.
In some embodiments, the trace materials of the first to sixth trace layers are conductive metals.
In some embodiments, the trace material of the first to sixth trace layers is metallic copper.
In some embodiments, the first, second, fifth, and sixth trace layers have thicknesses of 10 to 20 microns, and the third and fourth trace layers have thicknesses of 15 to 29 microns.
In some embodiments, a first dielectric layer is disposed between the first routing layer and the second routing layer, a second dielectric layer is disposed between the second routing layer and the third routing layer, a third dielectric layer is disposed between the third routing layer and the fourth routing layer, a fourth dielectric layer is disposed between the fourth routing layer and the fifth routing layer, and a fifth dielectric layer is disposed between the fifth routing layer and the sixth routing layer.
In some embodiments, the first, second, fourth, and fifth dielectric layers are resin materials, and the third dielectric layer is a core material.
In some embodiments, the first, second, fourth, and fifth dielectric layers have a thickness of 24 microns to 36 microns and the third dielectric layer has a thickness of 370 microns to 450 microns.
In some embodiments, the chip substrate further comprises a first solder mask layer and a second solder mask layer;
the first solder mask layer is arranged above the first wiring layer, and the second solder mask layer is arranged below the sixth wiring layer.
In some embodiments, the thickness of the first and second solder masks is from 13.5 microns to 28.5 microns.
Compared with the laminated structure of the traditional chip substrate, the laminated structure of the chip substrate has the advantages that the wiring layer of the chip substrate is reduced to 6 layers from 10 layers, so that the total layer number of the chip substrate is reduced by nearly half, the production cost of the chip is reduced, and the thickness and the volume of a finished chip are reduced.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 shows a plan structure diagram of an FPGA chip according to an embodiment of the present application.
Fig. 2 shows a schematic diagram of high-speed signals in an FPGA chip according to an embodiment of the present application.
Detailed Description
In order to better understand the solution of the present application, the following description will make clear and complete descriptions of the technical solution of the embodiment of the present application with reference to the accompanying drawings in the embodiment of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The high-frequency high-speed FPGA chip has higher requirements on power performance and high-speed signal performance during packaging design, and in order to ensure the requirements on high-speed signals and power performance, the laminated structure of the traditional high-frequency high-speed FPGA chip substrate at least comprises 10 wiring layers, and the thickness and the volume of a finished chip obtained according to the traditional high-frequency high-speed chip substrate are also larger, and the laminated structure of the traditional high-frequency high-speed chip substrate is as shown in the following table 1 and the following table 2.
TABLE 1
Layer number Core High speed serial signal High-speed IO interface
L1 Power supply 1 Power supply 5 Power supply 1
L2 GND TX/GND GND/Sigal
L3 GND/Sigal GND GND
L4 GND RX/GND GND/Sigal
L5 Power supply 2/power supply 3 GND Power supply 7
L6 Power supply 1 Power supply 5 Power supply 8
L7 GND GND GND
L8 Power supply 2 GND GND/Sigal
L9 GND Power supply 6 Power supply 1
L10 Power supply 4 GND GND
As shown in table 1, the conventional high-frequency high-speed chip substrate includes a Core routing area (Core) and a high-speed serial signal routing area and a high-speed input/output interface routing area, the chip substrate includes ten layers of L1 to L10 routing layers from top to bottom, in the Core routing area (Core), a layer L1 is used for laying a power supply 1, a layer L2 is used for laying a GND plane, a layer L3 is used for laying a GND plane, fan-out static wires and other stray signals (table 1 is indicated by signal), a layer L4 is used for laying a GND plane, a layer L5 is used for laying a power supply 2 and a power supply 3, a layer L6 is used for still laying a power supply 1, a layer L7 is used for laying a GND plane, a layer L8 is used for still laying a power supply 2, a layer L9 is used for laying a GND plane, and a layer L10 is used for laying a power supply 4.
In the high-speed serial signal wiring area, a power supply 5 is laid on the L1 layer, a GND plane is laid on the L2 layer, and the high-speed serial signal of the fan-out transmitting end, a GND plane is laid on the L3 layer, a GND plane is laid on the L4 layer, and the high-speed serial signal of the fan-out receiving end, a GND plane is laid on the L5 layer, a power supply 5 power supply is still laid on the L6 layer, a GND plane is laid on the L7 layer, a GND plane is laid on the L8 layer, a power supply 6 is laid on the L9 layer, and a GND plane is laid on the L10 layer.
In the high-speed input/output interface wiring area, a power supply 1 is laid on the layer L1, a GND plane is laid on the layer L2, and a group of high-speed differential signals of the fan-out chip, a GND plane is laid on the layer L3, a GND plane is laid on the layer L4, and another group of high-speed differential signals of the fan-out chip, a power supply 7 is laid on the layer L5, a power supply 8 is laid on the layer L6, a GND plane is laid on the layer L7, a jumper wire is needed in the high-speed differential signals of the layer L2 and the layer L4 of the fan-out layer L8, a power supply 1 is still laid on the layer L9, and a GND plane is laid on the layer L10.
It should be clear that, in the field of chip package design, various signals may be required to correspond to different power types, and each power type is an independent power source, so in fact, the power sources 1 to 8 will determine different power types according to the chip types and the chip requirements, and the differences between the power sources 1 to 8 generally include differences between the voltage, the current, and the related communication/power protocols, etc., so the purpose of the embodiments of the present application is to provide a laminated structure of a chip substrate, and therefore, the power source differences used in the chip package design will not be further described.
TABLE 2
As shown in table 2, the conventional high-frequency high-speed chip substrate includes a dielectric layer between each trace layer, the dielectric layer between L5 and L6 is made of Core material, the dielectric layers between the other layers are all made of resin material (ABF, ajinomoto Build-up Film), the thickness of the dielectric layer between the L5 layer and the L6 layer is 820 μm, and because the Core layer is too thick, the main parts of the two groups of high-speed differential signals can only fan out above the Core layer, namely the L1 layer and the L4 layer.
In view of the problems of multiple routing layers and thick chip substrate of the conventional chip substrate, the embodiment of the present application provides a laminated structure of the chip substrate, the chip substrate includes first to sixth routing layers from Top to bottom (i.e. Top end to bottom end of the chip substrate), each routing layer includes a core routing region, table 3 shows routing of each layer of the core routing region of the laminated structure of the chip substrate provided in the embodiment of the present application, as shown in table 3 below:
Layer/Layer number Core/Core routing area
L1 First power supply
L2 GND
L3 Second power supply
L4 Third power supply
L5 GND
L6 First power supply
As shown in table 3, in the Core routing area (Core), the first routing layer L1 is used for laying a first power plane, the second routing layer L2 is used for laying a ground plane GND, the third routing layer L3 is used for laying a second power plane, the fourth routing layer L4 is used for laying a third power plane, the fifth routing layer L5 is used for laying a ground plane GND, and the sixth routing layer L6 is used for laying a first power plane.
Compared with the laminated structure of the traditional chip substrate, the laminated structure of the chip substrate provided by the embodiment of the application is compared with the laminated structure of the traditional 10-layer chip substrate, the power plane and the ground plane of the chip substrate can be paved only by 6 layers of substrates, so that the wiring layer of the chip substrate is reduced to 6 layers by 10 layers, the total layer number of the chip substrate is reduced to be close to half, the production cost of the chip is reduced, and the thickness and the volume of a finished chip are reduced.
It should be clear that, in the field of chip package design, various signals may be required to correspond to different power types, and each power type is an independent power source, so the power type of the chip should be determined according to the chip requirement in practical application, and the power types can be generally distinguished by voltage, current, related communication/power protocol and the like.
In the stacked structure of the chip substrate provided in the embodiment of the present application, the first power supply, the second power supply and the third power supply are all common power supply types of those skilled in the art in the chip packaging design, and correspond to independent power supplies respectively, in some embodiments, in the FPGA chip substrate, the first power supply is a 1V power supply, the second power supply is a 1.8V power supply, the third power supply is a 1V power supply, and one of the differences between the first power supply and the third power supply is that the dynamic current of the first power supply is higher than that of the third power supply; the embodiments of the present application only exemplify the distinction between the above power supply types by voltage and current, but do not represent that the above power supply types only include the distinction between voltage and current, and the specific distinction between the above power supply types relates to the chip power supply technology, which has been deviated from the solutions provided in the embodiments of the present application and all belong to the prior art, so this embodiment of the present application will not be described.
In some embodiments, each trace layer further includes a high-speed serial signal trace area and a high-speed input/output interface trace area; table 4 shows the routing layers of the high-speed serial signal routing area and the high-speed input/output interface routing area of the stacked structure of the chip substrate provided in the embodiment of the present application, and table 4 below:
Layer/Layer number High-speed serial signal wiring area High-speed input/output interface wiring area
L1 TX/fourth power supply Sigal/sixth power supply
L2 Clk/GND GND
L3 Fourth power supply/fourth power supplyFive power sources L Sixth power supply
L4 GND GND
L5 RX/Clk/fourth power supply Sigal/sixth power supply
L6 GND Sigal/GND
As shown in table 4, in the high-speed serial signal routing area, the first routing layer L1 layer is used for laying a fourth power plane, and the high-speed serial signal TX of the fan-out transmitting end, the second routing layer L2 layer is used for laying a ground plane GND, and the fan-out clock signal Clk, the third routing layer L3 layer is used for laying a fourth power plane and a fifth power plane, the fourth routing layer L4 layer is used for laying a ground plane GND, the fifth routing layer L5 layer is used for laying a fourth power plane, the high-speed serial signal RX of the fan-out receiving end, and the clock signal Clk of the fan-out jumper, and the sixth routing layer L6 layer is used for laying a ground plane GND. Optionally, in some embodiments, in the FPGA chip substrate, the routing of the high-speed serial signal is implemented by using a Serdes module, that is, in the high-speed serial signal routing area of the FPGA chip, the sending end refers to a sending end of the Serdes module, and the receiving end is a receiving end of the Serdes module.
The first routing layer is used for paving a fourth power plane and a fifth power plane respectively, the fifth routing layer is used for paving the high-speed serial signal of the receiving end and the clock signal of a fanning jumper, the fourth power plane is paved firstly, then the high-speed differential signal is fanned in the fourth power plane, the second routing layer is used for fanning out the clock signal, the ground plane is paved firstly, then the clock signal is fanned out in the ground plane, the third routing layer is paved with the fourth power plane and the fifth power plane, the routing layer is divided into two areas and is respectively used for paving the fourth power plane and the fifth power plane, the fifth routing layer is used for fanning out the high-speed serial signal of the receiving end and the clock signal of the fanning jumper, the fourth power plane is paved firstly, then the high-speed serial signal of the receiving end and the clock signal of the fanning jumper are fanned out in the fourth power plane, and the clock signal of the jumper is fanned out in the fourth power plane, and the jumper is not fanned out all the second routing layer, and therefore the rest clock signals are fanned out by the fifth routing layer.
As shown in table 4, in the high-speed input-output interface routing area, the first routing layer L1 layer is used for laying a sixth power plane and fanning out a first high-speed differential signal, the second routing layer L2 layer is used for laying a ground plane GND, the third routing layer L3 layer is used for laying a sixth power plane, the fourth routing layer L4 layer is used for laying a ground plane GND, the fifth routing layer L5 layer is used for laying a sixth power plane and fanning out a second high-speed differential signal, the sixth routing layer L6 layer is used for laying a ground plane GND and fanning out a first high-speed differential signal of a jumper and a second high-speed differential signal of a jumper.
The purpose of the first routing layer is to fan out a first high-speed differential signal, a sixth power plane is paved firstly, then the first high-speed differential signal is fan out in the sixth power plane, the purpose of the fifth routing layer is to fan out a second high-speed differential signal, the purpose of the sixth routing layer is to lay out a jumper part in the first high-speed differential signal and the second high-speed signal, a ground plane is paved firstly, then the jumper part in the first high-speed differential signal and the second high-speed signal is fan out in the ground plane, the jumper first high-speed differential signal and the second high-speed differential signal refer to that the first routing layer and the second routing layer cannot fan out all the first high-speed differential signal and the second high-speed differential signal, and therefore the rest first high-speed differential signal and the second high-speed differential signal cannot fan out through the fifth routing layer.
It should be clear that, in the embodiment of the present application, the first high-speed differential signal and the second high-speed differential signal respectively represent a plurality of high-speed differential signals, instead of a certain high-speed differential signal, fig. 1 shows a plane structure diagram of an FPGA chip provided in the embodiment of the present application, as shown in fig. 1, a conventional FPGA chip includes a Core area in the Die center and a peripheral area around the Core area (including serdes and HP/HR), the Core area in the Die center generally includes a power supply buffer and a ground buffer, the Die peripheral area generally includes various high-speed signals, the high-speed signal in one area in fig. 1 is a high-speed signal of one bank, generally one chip includes a plurality of banks, and in an example where the high-speed signal and the power supply buffer in each bank are arranged identically, fig. 2 shows a schematic diagram of the high-speed signal in the FPGA chip provided in the embodiment of the present application, as shown in fig. 2, and one bank includes two rows of high-speed differential signals, which correspond to the first high-speed differential signal and the second high-speed differential signal of the bank respectively and the high-speed differential signal of the bank are adjacent to the high-speed signal of the bank. The examples of fig. 1 and fig. 2 are only used to illustrate the positions of the first high-speed differential signal and the second high-speed differential signal in one bank in the chip.
In some embodiments, the fourth power supply, the fifth power supply and the sixth power supply are common power supply types of those skilled in the art in the chip packaging design, and correspond to independent power supplies respectively, in some embodiments, the fourth power supply is an analog power supply of 1V, the fifth power supply is an analog power supply of 1.8V, the sixth power supply is an input/output port power supply of 3.3V, the fourth power supply and the fifth power supply are independent power supplies in the high-speed serial signal routing area, and the sixth power supply is an independent power supply in the high-speed input/output interface routing area; the embodiments of the present application only exemplify the distinction between the above power supply types by voltage and current, but do not represent that the above power supply types only include the distinction between voltage and current, and the specific distinction between the above power supply types relates to the chip power supply technology, which has been deviated from the solutions provided in the embodiments of the present application and all belong to the prior art, so this embodiment of the present application will not be described.
Table 5 shows the lamination configuration of the lamination structure of the chip substrate provided in the embodiment of the present application, as follows
Table 5.
Layer number Laminated structure Thickness of (L) Tolerance of
soldermask 21 ±7.5
L1 Metal 15 ±5
ABF 30 ±6
L2 Metal 15 ±5
ABF 30 ±6
L3 Metal 22 ±7
Core 410 ±40
L4 Metal 22 ±7
ABF 30 ±6
L5 Metal 15 ±5
ABF 30 ±6
L6 Metal 15 ±5
soldermask 21 ±7.5
As shown in table 5, in some embodiments, in the stacked structure of the chip substrate provided in the embodiments of the present application, the trace materials of the first to sixth trace layers are conductive metals, and specifically, the conductive metals may be any metals with conductive properties, and the better the conductivity, the higher the chip performance.
As shown in table 5, in some embodiments, in the stacked structure of the chip substrate provided in the embodiments of the present application, the routing materials of the first to sixth routing layers are metal copper, and based on the cost and conductivity of the conductive metal, the cost performance of selecting metal copper as the routing material of the first to sixth routing layers is higher.
As shown in table 5, in some embodiments, the thickness of the first routing layer, the second routing layer, the fifth routing layer, and the sixth routing layer is 10 micrometers to 20 micrometers, and the thickness of the third routing layer and the fourth routing layer is 15 micrometers to 29 micrometers.
As shown in table 5, in some embodiments, in the laminated structure of the chip substrate provided in the embodiments of the present application, a first dielectric layer is disposed between a first routing layer and a second routing layer, a second dielectric layer is disposed between the second routing layer and a third routing layer, a third dielectric layer is disposed between the third routing layer and a fourth routing layer, a fourth dielectric layer is disposed between the fourth routing layer and a fifth routing layer, and a fifth dielectric layer is disposed between the fifth routing layer and a sixth routing layer.
As shown in table 5, in some embodiments, in the stacked structure of the chip substrate provided in the embodiments of the present application, the first dielectric layer, the second dielectric layer, the fourth dielectric layer, and the fifth dielectric layer are resin materials (ABF materials), and the third dielectric layer is a Core material.
As shown in table 5, in some embodiments, in the stacked structure of the chip substrate provided in the embodiments of the present application, the thicknesses of the first dielectric layer, the second dielectric layer, the fourth dielectric layer and the fifth dielectric layer are 24 micrometers to 36 micrometers, and the thickness of the third dielectric layer is 370 micrometers to 450 micrometers.
As shown in table 5, in some embodiments, the chip substrate provided in the embodiments of the present application further includes a first solder mask (soldermask) and a second solder mask (soldermask);
the first solder mask layer is arranged on the first wiring layer, and the second solder mask layer is arranged below the sixth wiring layer.
As shown in table 5, in some embodiments, the thickness of each of the first solder resist layer and the second solder resist layer is 13.5 micrometers to 28.5 micrometers in the laminated structure of the chip substrate provided in the embodiments of the present application.
Compared with the prior art, the laminated structure of the chip substrate reduces the lamination of the chip substrate from 10 wiring layers to 6 wiring layers, so that the total layer number of the chip substrate is reduced by nearly half, and the production cost of the chip and the thickness and volume of a finished chip are reduced. The thickness of the Core material is reduced from about 820 micrometers to about 410 micrometers, so that the second high-speed differential signal is fanned out below a dielectric layer prepared by the Core material.
On the other hand, the laminated structure of the chip substrate provided in the embodiment of the present application optimizes the power supply configuration and the high-speed differential signal configuration of each layer of the chip substrate, specifically referring to table 3 and table 4, and the partial simulation results of the laminated structure of the chip substrate provided in the embodiment of the present application are referring to table 6 and table 7.
TABLE 6
TABLE 7
Return loss/1 GHz Insertion loss/1 GHz Far-end crosstalk/1 GHz
6-layer substrate 14.4db 0.59db 30.35db
10-layer substrate 14.1db 0.58db 32.78db
As shown in tables 6 and 7, after the lamination of the chip substrate is reduced to 6 layers, because the thickness of the core material dielectric layer of the substrate is reduced, the voltage drop and loop inductance of the power supply are better than those of the 10 layers of the chip substrate, the insertion loss and return loss of the high-speed differential signal are close to those of the 10 layers of the chip substrate, and the far-end crosstalk is still within the quality range of the high-speed differential signal compared with that of the 10 layers of the chip substrate although the far-end crosstalk is increased by 2.4 db.
The foregoing is a further detailed description of the present application in connection with the specific embodiments, and it is not intended that the practice of the present application be limited to such descriptions. It should be understood by those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the present application, and the present application is not limited to the above-mentioned embodiments.

Claims (10)

1. The laminated structure of the chip substrate is characterized in that the chip substrate comprises a first wiring layer, a second wiring layer and a third wiring layer from top to bottom, wherein each wiring layer comprises a core wiring area;
in the core wiring area, the first wiring layer is used for paving a first power plane, the second wiring layer is used for paving a ground plane, the third wiring layer is used for paving a second power plane, the fourth wiring layer is used for paving a third power plane, the fifth wiring layer is used for paving the ground plane, and the sixth wiring layer is used for paving the first power plane.
2. The chip substrate laminate structure of claim 1, wherein each of the trace layers further comprises a high-speed serial signal trace region and a high-speed input-output interface trace region;
in the high-speed serial signal wiring area, the first wiring layer is used for paving a fourth power plane, and a high-speed serial signal of a fan-out transmitting end, the second wiring layer is used for paving the ground plane and a fan-out clock signal, the third wiring layer is used for paving the fourth power plane and a fifth power plane, the fourth wiring layer is used for paving the ground plane, the fifth wiring layer is used for paving the fourth power plane, a high-speed serial signal of a fan-out receiving end and the clock signal of a fan-out jumper, and the sixth wiring layer is used for paving the ground plane;
in the high-speed input/output interface wiring area, the first wiring layer is used for paving a sixth power plane and fanning out a first high-speed differential signal, the second wiring layer is used for paving the ground plane, the third wiring layer is used for paving the sixth power plane, the fourth wiring layer is used for paving the ground plane, the fifth wiring layer is used for paving the sixth power plane and fanning out a second high-speed differential signal, and the sixth wiring layer is used for paving the ground plane, the first high-speed differential signal of a fanning-out jumper and the second high-speed differential signal of the fanning-out jumper.
3. The chip substrate laminate structure of claim 1, wherein the trace materials of the first to sixth trace layers are conductive metals.
4. The chip substrate laminate structure of claim 3, wherein the trace material of the first to sixth trace layers is metallic copper.
5. The stacked structure of chip substrates of claim 1, wherein the first, second, fifth and sixth trace layers have thicknesses of 10 to 20 microns, and the third and fourth trace layers have thicknesses of 15 to 29 microns.
6. The laminated structure of the chip substrate according to claim 1, wherein a first dielectric layer is arranged between the first wiring layer and the second wiring layer, a second dielectric layer is arranged between the second wiring layer and the third wiring layer, a third dielectric layer is arranged between the third wiring layer and the fourth wiring layer, a fourth dielectric layer is arranged between the fourth wiring layer and the fifth wiring layer, and a fifth dielectric layer is arranged between the fifth wiring layer and the sixth wiring layer.
7. The stacked structure of chip substrates of claim 6, wherein the first dielectric layer, the second dielectric layer, the fourth dielectric layer, and the fifth dielectric layer are resin materials, and the third dielectric layer is a core material.
8. The stacked structure of chip substrates of claim 6, wherein the first, second, fourth and fifth dielectric layers have a thickness of 24 to 36 microns and the third dielectric layer has a thickness of 370 to 450 microns.
9. The laminate structure of the chip substrate of claim 1, wherein the chip substrate further comprises a first solder mask layer and a second solder mask layer;
the first solder mask layer is arranged above the first wiring layer, and the second solder mask layer is arranged below the sixth wiring layer.
10. The laminate structure of claim 9, wherein the first solder mask layer and the second solder mask layer each have a thickness of 13.5 microns to 28.5 microns.
CN202311099647.XA 2023-08-28 2023-08-28 Laminated structure of chip substrate Pending CN117393533A (en)

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CN202311099647.XA CN117393533A (en) 2023-08-28 2023-08-28 Laminated structure of chip substrate

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CN117393533A true CN117393533A (en) 2024-01-12

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