CN117393505A - Package and method for manufacturing a package - Google Patents

Package and method for manufacturing a package Download PDF

Info

Publication number
CN117393505A
CN117393505A CN202310855742.1A CN202310855742A CN117393505A CN 117393505 A CN117393505 A CN 117393505A CN 202310855742 A CN202310855742 A CN 202310855742A CN 117393505 A CN117393505 A CN 117393505A
Authority
CN
China
Prior art keywords
molded body
package
semiconductor die
lead
drain contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310855742.1A
Other languages
Chinese (zh)
Inventor
常洁
袁晓颖
李根赫
保罗·比拉尔多
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Components Industries LLC
Original Assignee
Semiconductor Components Industries LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US18/349,440 external-priority patent/US20240021487A1/en
Application filed by Semiconductor Components Industries LLC filed Critical Semiconductor Components Industries LLC
Publication of CN117393505A publication Critical patent/CN117393505A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials

Abstract

A package and a method for manufacturing the package are provided. The package includes a semiconductor die attached to a substrate and a molded body encapsulating the semiconductor die. The molded body is a six-sided rectangular box-like structure, and at least one corner portion of the molded body formed by two adjacent faces is free of molding material, thereby reducing the size and weight of the molded body.

Description

Package and method for manufacturing a package
RELATED APPLICATIONS
The present application claims priority from U.S. provisional application No. 63/368,202 filed on 7.12 2022, the entire contents of which are incorporated herein by reference. The present application is also directed to commonly assigned U.S. patent application Ser. No. 18/185,514 entitled "discrete semiconductor device Package," filed on 3/17 of 2023, which is incorporated herein by reference in its entirety.
Technical Field
The present specification relates to packages and methods for manufacturing packages.
Background
Semiconductor packages include metal, plastic, glass, or ceramic enclosures containing one or more semiconductor devices or integrated circuits. Individual components are fabricated on a semiconductor wafer (typically a silicon or silicon carbide wafer) prior to dicing into chips, testing, and packaging. The package provides means to connect the semiconductor device or integrated circuit to an external environment such as a printed circuit board via pins such as pads, balls or pins, as well as to provide protection against threats such as mechanical shock, chemical contamination and illumination. With the increasing demand for high performance Integrated Circuits (ICs), new improvements in packaging technology are needed to improve the performance and reliability of ICs.
Disclosure of Invention
In one aspect, a package includes a semiconductor die attached to a substrate and a molded body encapsulating the semiconductor die. The molded body is of a six-sided rectangular box-like structure, and at least one corner portion of the molded body formed by two adjacent faces is free of molding material, thereby reducing the size and weight of the molded body.
In another aspect, the top surface of the molded body includes a heat dissipating surface. The semiconductor die encapsulated in the molded body is thermally coupled to the heat dissipation surface.
In one aspect, a package includes a semiconductor die attached to a substrate and a molded body encapsulating the semiconductor die. The molded body encapsulating the semiconductor die is a six-sided rectangular box-like structure. At least one lead is attached to the semiconductor die, a portion of the lead extending outside of the molded body and forming an external terminal of the package. The lead is a drain contact lead, and a portion of the drain contact lead extending to the outside of the molded body is notched to reduce the strength of the drain contact lead.
In one aspect, a method for manufacturing a package includes disposing a semiconductor die on a substrate (e.g., a leadframe substrate), and encapsulating the semiconductor die in a molded body. The molded body is a six-sided rectangular box-like structure. At least one corner portion of the molded body formed by two adjacent faces is free of molding material, thereby reducing the size and weight of the molded body.
In one aspect, a method for manufacturing a package includes disposing a semiconductor die on a substrate (e.g., a leadframe substrate), and encapsulating the semiconductor die in a molded body. The molded body has a six-sided rectangular box-like structure. The method further includes attaching the drain contact lead to the semiconductor die. A portion of the drain contact lead extends to the outside of the molded body and forms an external terminal of the package. The method further includes notching a portion of the drain contact lead that extends to the exterior of the molded body to reduce the strength of the drain contact lead.
The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims.
Drawings
Fig. 1A illustrates an exemplary semiconductor device package.
Fig. 1B illustrates the footprint of the semiconductor device package of fig. 1A.
Fig. 2A, 2B, 2C, and 2D illustrate external views of an exemplary semiconductor device package having a structure configured to resist stress-induced cracking of a molded body of the package.
Fig. 3A, 3B, 3C, and 3D illustrate external views of another exemplary semiconductor device package having a structure configured to resist stress-induced cracking of a molded body of the package.
Fig. 4, 5 and 6 illustrate examples of semiconductor die that may be mounted in the molded body of the semiconductor device package of fig. 2A or in the molded body of the semiconductor device package of fig. 3A.
Fig. 7 illustrates an example method for fabricating a semiconductor device package.
Fig. 8 illustrates another example method for fabricating a semiconductor device package.
Detailed Description
A semiconductor device package, such as an Integrated Circuit (IC) package, includes a semiconductor die mounted on a leadframe structure that includes leads that provide external electrical connections (to the outside of the package) for individual devices or integrated circuits in the semiconductor die. The semiconductor die may be mounted on pads or marks in the leadframe structure using solder or conductive adhesive. In addition, device contact pads on the semiconductor die are electrically connected to corresponding leads using bond wires (e.g., aluminum bond wires). Leads extending outside the package and forming external terminal pins may be used to mount the package on a printed circuit board or terminal strip. In example embodiments, the terminal pins may be mounted in receptacles or soldered to a Printed Circuit Board (PCB) or terminal strip.
Many package types may be used in various applications. Some are defined by international, national or industry standards, while others are specific to each manufacturer. The number and configuration of external terminal pins of a package type may be defined by international, national or industry standards. Standardized semiconductor device package types may be used for surface mounting on a circuit board, such as a Printed Circuit Board (PCB). In an exemplary semiconductor device package, pins on the package are bent to rest against the PCB surface. In addition to the tags for power input and output, the package may have, for example, three to seven signal terminals. For automotive applications, the semiconductor package may include a silicon carbide transistor, a gallium nitride device, or an Insulated Gate Bipolar Transistor (IGBT), a Fast Recovery Diode (FRD), a silicon carbide diode, or other devices.
Devices and other components of the semiconductor package (e.g., leadframe substrates) may be packaged in a body of molding material (e.g., a body made of plastic or epoxy, etc.). Pins or terminals (e.g., signal pins, power terminals) may extend outside of the package. In example embodiments, the semiconductor device package excluding the leads may be, for example, a rectangular box-like structure of width W, height H, and length L.
Fig. 1A shows a perspective view of a semiconductor device package 100. The semiconductor device package 100 includes a mold body 30 made of plastic, epoxy, or the like. The molded body 30 may be made of a plastic material. The molded body 30 may house semiconductor devices or circuits (not visible). The molded body 30 may have a generally six-sided rectangular box-like shape with opposing sides a and B, opposing sides C and D, and opposing top and bottom sides T and S.
The molded body 30 may house semiconductor devices or circuits (not visible). The lead frame (lead) connected to the mounted semiconductor device or circuit may extend to the outside of the molded body to form an external terminal of the mounted semiconductor device or circuit. The leads may be made of a metal or metal alloy (e.g., copper). In the example shown in FIG. 1A, seven signal leads (e.g., leads 10-1, 10-2, 10-3, 10-4, 10-5, 10-6, and 10-7) extend, for example, from one face (e.g., face A) of the molded body 30, and a power lead 20 (e.g., drain lead) extends from an opposite face (e.g., face B) of the molded body 30. Seven signal leads may be formed from rectangular metal strips. The power cord 20 may be formed as a metal plate or strip that extends from outside the molded body to form a U-shaped connector with wings having tips 20-1 and 20-2. In example embodiments, the tips 20-1 and 20-2 of the signal leads (e.g., leads 10-1, 10-2, 10-3, 10-4, 10-5, 10-6, and 10-7) and the power line (e.g., drain lead) may be formed as or include a flat surface (FT), which may be uniformly placed on the surface of the printed circuit board for connecting (e.g., soldering) the semiconductor device package 100 to the printed circuit board.
In an example embodiment, the molded body may include a cutout (e.g., cutout 40) (e.g., a semi-cylindrical cutout) extending from the opposing bottom surface S along the opposing faces C and D toward the top surface T. The bottom of the cutout 40 may form a clamping surface 42, which clamping surface 42 may be used to hold the semiconductor device package 100 on a printed circuit board, for example, with a clamp (not shown).
In an example embodiment, the box-like structure of the molded body 30 may have the following dimensions: w is equal to about 20mm, L is equal to about 28 mm, and height H is equal to about 4 mm. Fig. 1B illustrates an example footprint of semiconductor device package 100 showing example dimensions of signal leads (e.g., leads 10-1, 10-2, 10-3, 10-4, 10-5, 10-6, and 10-7) and planar surfaces FT of tips 20-1 and 20-2 of power lines. In fig. 1B, exemplary distances and dimensions of exemplary semiconductor device package 100 are labeled or indicated in millimeters.
In semiconductor device packages, the Coefficient of Thermal Expansion (CTE) mismatch between the semiconductor die and the leadframe (e.g., copper leadframe) or the CTE mismatch between the clip (e.g., copper clip) and the semiconductor die can cause high stresses on the solder between the components. Cracks may be observed after temperature cycling. Furthermore, wire fatigue (fatigue of aluminum wires connecting the gates of the semiconductor die and the leadframe) can be a weakness in typical packages during power cycles.
Further, a Coefficient of Thermal Expansion (CTE) mismatch between the components of the semiconductor device package and the molded body of the semiconductor device package may result in physical degradation (e.g., cracking) of the molded body of the package components.
The packaging embodiments described in this disclosure address these issues and provide a cost effective and reliable solution for packaging a semiconductor die (e.g., a power transistor, a silicon carbide (SiC) MOSFET, or another device).
In accordance with the principles of the present disclosure, in exemplary package embodiments, the leads of the molded body and semiconductor device package are shaped and structured to avoid stress-induced cracking of the molded body (e.g., under temperature cycling).
In example embodiments, a molded body shaped and structured to avoid stress-induced cracking may include one or more of the following features:
a. notched drain leads. The cut in the drain lead may reduce the strength of the drain lead and reduce the stress induced by the drain lead on the printed circuit board.
b. Reduced size and weight of the molded body. The molded body may be shaped to not include molding material, for example, at the corners next to the signal leads and/or the corners next to the drain leads.
c. A wide groove is provided on an edge of a surface of the molded body to increase a creepage distance of the signal leads.
d. A shortened drain lead. The shortened drain leads may enable a high unit density leadframe design.
e. Symmetrically positioned clamping surfaces. Symmetrically positioned clamping surfaces allow the device package on the printed circuit board to be clamped in a balanced manner.
Further, in accordance with the principles of the present disclosure, in an exemplary package embodiment, the top surface of the molded body includes a surface of a heat spreader that is coupled to the semiconductor die housed in the molded body.
Fig. 2A-2D illustrate external views of an exemplary semiconductor device package 200, the package 200 having a structure configured to resist stress-induced cracking of a molded body of the package. The semiconductor device package 200 includes a mold body 210. The semiconductor devices or circuits that can be accommodated in the molded body 210 are not visible in fig. 2A to 2D, but are shown, for example, in fig. 4 to 6. Fig. 2A shows a top plan view. Fig. 2B shows a bottom plan view. Fig. 2C shows a side view. Fig. 2D shows a top perspective view of semiconductor device package 200.
As shown in fig. 2A to 2D, the molded body 210 may have a six-sided rectangular box-like shape having four vertical faces (faces A, B, C and D), a top face T, and a bottom face S. The top and bottom surfaces may have a length L and a width W. Further, signal leads (e.g., leads 10-1,..10-7) extend to the exterior of the molded body through face a, and drain lead 250 extends to the exterior of the molded body through face B. As shown in fig. 2D, the drain lead 250 may be formed as a metal plate. The drain lead is so short that most of the drain lead 250 is located inside the molded body and only the tips 250-1 and 250-2 protrude substantially from the molded body.
Further, in an exemplary embodiment, as shown in fig. 2A and 2D, a wide slot (e.g., slot 230) may be provided in the molded body 210 (e.g., along or aligned with face a). The slot 230 (e.g., having a width w1 and a depth d 1) may increase the creepage distance of the signal leads protruding from the face a.
Further, in an exemplary embodiment, the molded body 210 may be formed (i.e., manufactured) such that, for example, no molding material is included at the corners formed by the faces a and C and the corners formed by the faces a and D (e.g., the corners 240) next to the signal leads (e.g., the leads 10-1 to 10-7). Such that the absence of molding material may reduce the amount (e.g., weight) of molding material included in the molded body 210.
In an example embodiment, the top surface of the molded body 210 includes a surface 220 that is thermally coupled to a heat spreader of a semiconductor die mounted in the molded body.
Further, in an example embodiment, the molded body 210 may include a cutout (e.g., cutout 40) extending along opposite faces C and D from opposite bottom faces S to top face T. The bottom of the cutout 40 may form a clamping surface 42, which clamping surface 42 may be used to hold the semiconductor device package 100 on a printed circuit board, for example, using a clamp (not shown). As shown in fig. 2B, the incision 40 and clamping surface 42 may be formed along an x-axis (e.g., axis M) that is intermediate (e.g., approximately equidistant) between surfaces a and B. The clamping surfaces may be positioned such that the semiconductor device package 200 is balanced clamped on the printed circuit board.
Fig. 3A-3D illustrate external views of another exemplary semiconductor device package 300, the package 300 having a structure configured to resist stress-induced cracking of a molded body of the package. The semiconductor device package 300 includes a mold body 310. The semiconductor devices or circuits that can be accommodated in the molded body 310 are not visible in fig. 3A to 3D, but are shown, for example, in fig. 4 to 6. Fig. 3A shows a top plan view.
Fig. 3B shows a bottom plan view. Fig. 3C shows a side view. Fig. 3D shows a top perspective view of semiconductor device package 200.
As shown in fig. 3A to 3D, the molded body 310 (similar to the molded body 210 of fig. 2A to 2D) may have a six-sided rectangular box-like shape having four vertical faces (faces A, B, C and D), a top face T, and a bottom face S. The top and bottom surfaces may have a length L and a width W. Further, the signal leads (e.g., lead 10-1,..lead 10-7) extend to the exterior of the molded body through face a, and the drain lead 350 extends to the exterior of the molded body through face B and diverges into a pair of tips (e.g., tips 350-1 and 350-2). As shown in fig. 3D, a portion of drain lead 350 extending from face B of molded body 310 is notched (e.g., notch N) before drain lead 350 diverges into tips 350-1 and 350-2. The notch N may reduce the strength of the drain lead 350 and reduce stress on the printed circuit board on which the semiconductor device package 300 is mounted. This can avoid cracking of the molded body during temperature cycling of the semiconductor device package 300.
In example embodiments of the packages described in this disclosure, a solder or silver-based frit can be used to attach a semiconductor die to a Die Attach Pad (DAP) on a substrate.
In an example embodiment of the packages described in the present disclosure, a plurality of device contact pads, including gate contact pads and sense contact pads, are disposed on a semiconductor die. The gate contact pads and sense contact pads are wire bonded to corresponding pairs of signal leads extending from one face of the molded body to the exterior of the molded body.
Further, in some example embodiments, the source contact pad aluminum wires are soldered to the respective signal lead sets.
Further, in some example embodiments, the source contact pads are attached to the respective signal lead sets by direct lead connection (DLA) clips.
In some example embodiments of the packages described in this disclosure, the semiconductor die is a silicon carbide (SiC) power transistor.
In some example embodiments of the packages described in the present disclosure, the semiconductor die is a first semiconductor die, and the package includes a second semiconductor die encapsulated in a molded body. The first semiconductor die is an Insulated Gate Bipolar Transistor (IGBT) and the second semiconductor die is a Fast Recovery Diode (FRD) or a silicon carbide diode.
Fig. 4-6 illustrate examples of semiconductor die that may be mounted in a molded body 210 of a semiconductor device package 200 (fig. 2A) or a molded body 310 of a semiconductor device package 300 (fig. 3A).
Fig. 4 shows an example of a semiconductor die 430 (e.g., a 1200V SiC MOSFET with a maximum current of about 600A, a power of about 500 KW) that may be packaged in a mold (e.g., mold 310). Semiconductor die 430 may be disposed on a die attach pad (e.g., DAP 420) on a top surface SD of a leadframe substrate (e.g., substrate 400) in a package. The substrate 400 may be made of metal (e.g., copper). In some example embodiments, semiconductor die 430 may be attached to DAP 420 by solder. In some other example embodiments, semiconductor die 430 may be attached to DAP 420 by a sintered body (e.g., a silver-based sintered body, (e.g., a silver-sintered body)). The substrate 400 can include a head (e.g., head 410) above (e.g., in the y-direction) the DAP 420. On one face, the head (e.g., the head 410 may be electrically connected to the DAP 420 through the substrate). On the other side, the head 410 may be connected to or extend into a drain lead 350 extending from the side B of the molded body 310.
The top surface SS of the semiconductor die 430 may include device contact pads (e.g., gate contact pad GC, sense contact pad SC, and several (e.g., three) source contact pads SR). In some cases, wire bonding may be used to connect device contact pads on the semiconductor die to signal leads (e.g., leads 10-1..leads 10-7) of semiconductor device package 300. For example, as shown in FIG. 4, gate contact pad GC and sense contact pad SC may be connected to lead 10-1 and lead 10-2 by wires (e.g., wire 411 and wire 412). In some other cases, high current carrying capacity wires (e.g., soldered aluminum wires) may be used to attach leads forming external terminals of the package to device contact pads (e.g., source, gate, sense, and drain contact pads) on the semiconductor die. In example embodiments, some of the leads may share a common lead portion or extension. For example, as shown in FIG. 4, several leads (e.g., lead 10-3, lead 10-4, lead 10-5, lead 10-6, and lead 10-7) are connected to and share a common lead extension (i.e., source lead extension 10-C).
For example, as shown in fig. 4, three source contact pads SR may be connected to a combination of signal leads (e.g., lead 10-3 to lead 10-7 connected as source lead extension 10-C) by soldered aluminum wires (e.g., wire 413).
In some other examples, a direct wire connection (DLA) process may be used to connect wires forming external terminals of a semiconductor device package directly (e.g., without wire connections or other intervening elements) to device contact pads (e.g., source, gate, sense, and drain contact pads) on a semiconductor die. Direct wire connection (DLA) clips with preformed leads can be used, for example, to connect device contact pads on a semiconductor die to signal leads.
Fig. 5 shows an example in which a DLA clip (clip 415) connects a source contact pad on a semiconductor die 430 to a source lead extension 10-C (instead of the aluminum wire shown in fig. 4). It should be noted that the three source contact pads SR shown in fig. 4 are not visible in fig. 5 because they are hidden under the DLA clip (clip 415).
In some example embodiments, a plurality of semiconductor die may be mounted in either the molded body 210 or the molded body 310. The plurality of semiconductor die may, for example, include two semiconductor die (e.g., an IGBT die and an FRD die).
Fig. 6 shows, for example, a first semiconductor die (e.g., IGBT die 630) and a second semiconductor die (e.g., FRD die 635), which may be packaged in a mold body (e.g., mold body 310). The first semiconductor die (e.g., IGBT die 630) and the second semiconductor die (e.g., FRD die 635 or silicon carbide diode) may be disposed on die attach pads (e.g., DAP 420) on a top surface SD of a leadframe substrate (e.g., substrate 400) in a semiconductor device package. In some other exemplary embodiments, the IGBT die 630 and the FRD die 635 may be attached to the DAP 420 by a sintered body (e.g., a silver-based sintered body (e.g., a silver-sintered body). In some other exemplary embodiments, the IGBT die 630 and the FRD die 635 may be attached to the DAP 420 by solder.
The top surface SI of the IGBT die 630 may include device contact pads (e.g., gate contact pad GC, sense contact pad SC, and two source contact pads SR). The top surface SF of FRD die 635 may include device contact pads (e.g., single source contact pad SR).
In an example embodiment, the gate contact pads GC and the sense contact pads SC of the IGBT die 630 may be connected to the leads 10-1 and 10-2 by wires (e.g., wires 411 and 412). Further, the two source contact pads SR of the IGBT die 630 and the single source contact pad SR of the FRD die 635 may be connected to a combination of signal leads (e.g., leads 10-3 to 10-7 connected as source lead extensions 10-C) by soldered aluminum wires (e.g., wires 613).
In an example embodiment, the spacer blocks (e.g., metal spacer blocks) may be thermally coupled to a top surface of a semiconductor die (e.g., semiconductor die 430, IGBT die 630, FRD die 635, etc.) housed in the semiconductor device package. The spacer blocks may be coupled to a heat dissipation surface (e.g., a metal surface) in a top surface of a molded body (in other words, the semiconductor die may be thermally coupled to a heat dissipation surface in a top surface of a molded body) in a semiconductor device package described in the present disclosure.
Fig. 7 illustrates an example method 700 for fabricating a semiconductor device package.
Method 700 includes disposing a semiconductor die on a substrate (710) and encapsulating the semiconductor die in a molded body (720). The molded body may be a six-sided rectangular box-like structure, and at least one corner portion of the molded body formed of two adjacent faces is free of molding material, thereby reducing the size and weight of the molded body.
The method 700 further can include providing a heat dissipation surface in the top surface of the molded body, and thermally coupling the semiconductor die packaged in the molded body to the heat dissipation surface.
The method 700 may further include attaching a drain contact lead to the semiconductor die, wherein a portion of the drain contact lead extends outside of the molded body and forms an external terminal of the package, and notching a portion of the drain contact lead extending outside of the molded body to reduce the strength of the drain contact lead.
Fig. 8 illustrates an example method 800 for fabricating a semiconductor device package.
The method 800 includes disposing a semiconductor die on a substrate (810) and encapsulating the semiconductor die in a molded body (820). The molded body may be a six-sided rectangular box-like structure. The method 800 further includes attaching a drain contact lead to the semiconductor die, wherein a portion of the drain contact lead extends outside of the molded body and forms an external terminal of the package (830), and notching the portion of the drain contact lead that extends outside of the molded body to reduce the strength of the drain contact lead (840).
The method 800 further includes providing a heat dissipation surface in the top surface of the molded body, and thermally coupling the semiconductor die packaged in the molded body to the heat dissipation surface.
In method 800, encapsulating the semiconductor die in the molded body 820 includes excluding at least one corner portion of the molded body formed by two adjacent faces from molding material to reduce the size and weight of the molded body.
It will be understood that in the foregoing description, when an element such as a layer, region, substrate or component is referred to as being "on", "connected" to, electrically connected "to, coupled" to or electrically coupled "to another element, it can be directly on, connected" or coupled to the other element or one or more intervening elements may be present. In contrast, when an element is referred to as being directly on, directly connected to, or directly coupled to another element or layer, there are no intervening elements or layers present. Although the terms directly on … …, directly connected to … …, or directly coupled to … … may not be used throughout the detailed description, elements shown directly on … …, directly connected to … …, or directly coupled to … … may be referred to as elements directly on … …, directly connected to … …, or directly coupled to … …. The claims of the present application may be modified, if any, to reference the exemplary relationships described in the specification or shown in the drawings.
As used in the specification and claims, the singular form may include the plural form unless the context indicates otherwise. Spatially relative terms (e.g., upper, above … …, above, below … …, lower, below, etc.) are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. In some embodiments, the relative terms upper and lower may include a vertical upper and a vertical lower, respectively. In some embodiments, the term adjacent may include laterally adjacent or horizontally adjacent.
Some embodiments may be implemented using various semiconductor processing and/or packaging techniques. Some embodiments may be implemented using various types of semiconductor processing techniques associated with semiconductor substrates, including, but not limited to, for example, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), and the like.
While certain features of the described embodiments have been illustrated as described in the present disclosure, many modifications, substitutions, changes, and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the embodiments. It is to be understood that they have been presented by way of example only, and not limitation, and various changes in form and details may be made. Any portion of the apparatus and/or methods described in this disclosure may be combined in any combination, except mutually exclusive combinations. Embodiments described in this disclosure may include various combinations and/or sub-combinations of the functions, components, and/or features of the different embodiments described.

Claims (13)

1. A package, the package comprising:
a semiconductor die attached to the substrate; and
a molded body encapsulating the semiconductor die, wherein the molded body is a six-sided rectangular box-like structure and at least one corner portion of the molded body formed by two adjacent faces is devoid of molding material, thereby reducing the size and weight of the molded body.
2. The package of claim 1, wherein a top surface of the molded body comprises a heat dissipation surface, and wherein the semiconductor die encapsulated in the molded body is thermally coupled to the heat dissipation surface.
3. The package of claim 1, wherein the package further comprises:
at least one lead attached to the semiconductor die, a portion of the lead extending to the exterior of the molded body and forming an external terminal of the package, wherein the lead is a drain contact lead and a portion of the drain contact lead extending to the exterior of the molded body is notched to reduce the strength of the drain contact lead.
4. The package of claim 1, wherein the package further comprises:
at least one lead attached to a device contact pad on the semiconductor die, a portion of the lead extending to the exterior of the molded body and forming an external terminal of the package, wherein the lead is a drain contact lead formed as a metal plate that extends to form a U-shaped connector with a shoulder having a tip, wherein only the tipped shoulder of the drain contact lead extends to the exterior of the molded body.
5. The package of claim 1, wherein the package further comprises:
a plurality of signal leads connected to a plurality of device contact pads on the semiconductor die, the plurality of device contact pads including a gate contact pad, a sense contact pad, and at least one source contact pad, the plurality of signal leads extending from one side of the molded body to an exterior of the molded body; and
a slot is provided in a top surface of the molded body along the face of the molded body, the slot having a width and a depth to increase a creepage distance of the plurality of signal leads extending from the face of the molded body to an exterior of the molded body.
6. The package of claim 1, wherein the package further comprises:
a pair of cutouts in the molded body extending from a bottom surface to a top surface of the molded body, the cutouts along a face of the molded body forming clamping faces to clamp the package to a printed circuit board, the pair of cutouts being formed along an axis equidistant from a first face and an opposite second face of the molded body.
7. The package of claim 1, wherein the package further comprises:
a plurality of signal leads connected to a plurality of device contact pads on the semiconductor die, the plurality of device contact pads including at least one source contact pad, the plurality of signal leads extending from one face of the molded body to an exterior of the molded body, wherein the source contact pads are soldered to respective groups of signal leads by aluminum wires.
8. A package, the package comprising:
a semiconductor die attached to the substrate;
a molded body encapsulating the semiconductor die, wherein the molded body is a six-sided rectangular box-like structure; and
at least one lead of the semiconductor die is attached, a portion of the lead extending to the exterior of the molded body and forming an external terminal of the package, wherein the lead is a drain contact lead and a portion of the drain contact lead extending to the exterior of the molded body is notched to reduce the strength of the drain contact lead.
9. The package of claim 8, wherein a top surface of the molded body comprises a heat dissipation surface, and wherein the semiconductor die encapsulated in the molded body is thermally coupled to the heat dissipation surface.
10. A method for manufacturing a package, the method comprising:
disposing a semiconductor die on a substrate; and
the semiconductor die is encapsulated in a molded body, wherein the molded body is a six-sided rectangular box-like structure and at least one corner portion of the molded body formed by two adjacent faces is devoid of molding material, thereby reducing the size and weight of the molded body.
11. The method of claim 10, wherein the method further comprises: providing a heat dissipation surface in a top surface of the molded body; and thermally coupling the semiconductor die encapsulated in the molded body to the heat dissipation surface.
12. A method for manufacturing a package, the method comprising:
disposing a semiconductor die on a substrate;
encapsulating the semiconductor die in a molded body, wherein the molded body is a six-sided rectangular box-like structure;
attaching a drain contact lead to the semiconductor die, a portion of the drain contact lead extending outside of the molded body and forming an external terminal of the package; and
the portion of the drain contact lead extending to the outside of the molded body is notched to reduce the strength of the drain contact lead.
13. The method of claim 12, wherein encapsulating the semiconductor die in the molded body comprises: at least one corner portion formed from two adjacent faces of the molded body is made to include no molding material to reduce the size and weight of the molded body.
CN202310855742.1A 2022-07-12 2023-07-12 Package and method for manufacturing a package Pending CN117393505A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US63/368,202 2022-07-12
US18/349,440 2023-07-10
US18/349,440 US20240021487A1 (en) 2022-07-12 2023-07-10 Semiconductor device package

Publications (1)

Publication Number Publication Date
CN117393505A true CN117393505A (en) 2024-01-12

Family

ID=89461967

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310855742.1A Pending CN117393505A (en) 2022-07-12 2023-07-12 Package and method for manufacturing a package

Country Status (1)

Country Link
CN (1) CN117393505A (en)

Similar Documents

Publication Publication Date Title
US6075288A (en) Semiconductor package having interlocking heat sinks and method of fabrication
CN111446217B (en) Semiconductor device with a semiconductor device having a plurality of semiconductor chips
US5378924A (en) Apparatus for thermally coupling a heat sink to a lead frame
US5075759A (en) Surface mounting semiconductor device and method
US6261868B1 (en) Semiconductor component and method for manufacturing the semiconductor component
CN110010489B (en) Method for manufacturing semiconductor device with side wall recess and related device
US20130252381A1 (en) Electrically Isolated Power Semiconductor Package With Optimized Layout
US20040124508A1 (en) High performance chip scale leadframe package and method of manufacturing the package
KR20020079477A (en) Multi-chip-module(mcm) type semiconductor device
US20100193922A1 (en) Semiconductor chip package
US9147600B2 (en) Packages for multiple semiconductor chips
CN108155168B (en) Electronic device
EP3449502B1 (en) Mechanically-compliant and electrically and thermally conductive leadframes for component-on-package circuits
KR102172689B1 (en) Semiconductor package and method of fabricating the same
US9666557B2 (en) Small footprint semiconductor package
CN217719586U (en) Electronic device
EP1560266A2 (en) Hermetic surface mounted power package
US7566967B2 (en) Semiconductor package structure for vertical mount and method
US20130256920A1 (en) Semiconductor device
US20230327350A1 (en) Transfer molded power modules and methods of manufacture
JP2021082714A (en) Semiconductor device
CN110634812A (en) Semiconductor device package with clip interconnect and dual side cooling
US20240021487A1 (en) Semiconductor device package
CN117393505A (en) Package and method for manufacturing a package
EP0408904A2 (en) Surface mounting semiconductor device and method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication