CN117391034B - Layout design file correction method and device - Google Patents
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Abstract
The application relates to a layout design file correction method and device. The layout design file correction method comprises the following steps: acquiring a library exchange format file and a synchronous data stream file of an initial layout; analyzing a library exchange format file of the initial layout to obtain layout physical information in the initial layout, and analyzing a synchronous data stream file of the initial layout to obtain layout data information corresponding to the layout physical information; checking whether the layout physical information has errors or not based on the layout design rules; when the layout physical information has errors, the layout data information corresponding to the layout physical information in the synchronous data stream file of the initial layout is corrected, so that the synchronous data stream file of the corrected layout is obtained. The layout design file correction method can timely check the layout design, has higher correction efficiency, and is beneficial to improving the accuracy of the layout design.
Description
Technical Field
The present disclosure relates to the field of integrated circuit design technologies, and in particular, to a layout design file correction method and apparatus.
Background
The layout design is an important content in the integrated circuit design, the quality of the layout design is directly related to the performance of a chip, the circuit design and the chip are connected through the layout, and the layout is the specific expression of the circuit. The foundry can manufacture the mask plate according to the layout provided by a designer, and then the chip manufacture is realized through the shape of the mask plate and the combination of the process flow.
In the layout design flow, the finally generated layout may not meet the process design rule of the foundry and have errors. However, the conventional layout design file correction method is inaccurate and takes long time to check and verify the layout, and the modification of the layout is complex and difficult to realize, so that the efficiency and accuracy of the layout design are seriously affected.
Disclosure of Invention
Based on the above, the embodiment of the application provides a layout design file correction method and device, which can be used for checking and correcting a layout, are simple in steps and easy to realize, and are beneficial to the efficiency and accuracy of layout design.
According to some embodiments, an aspect of the present application provides a layout design file modification method, including:
acquiring a library exchange format file and a synchronous data stream file of an initial layout;
analyzing the library exchange format file of the initial layout to obtain layout physical information in the initial layout, and analyzing the synchronous data stream file of the initial layout to obtain layout data information corresponding to the layout physical information;
checking whether the layout physical information has errors or not based on layout design rules;
when the layout physical information has errors, the layout data information corresponding to the layout physical information in the synchronous data stream file of the initial layout is corrected, so that the synchronous data stream file of the corrected layout is obtained.
In some embodiments, the layout design file modification method further includes:
verifying the synchronous data stream file of the corrected layout;
when error information exists in the synchronous data stream file of the corrected layout, correcting the error information to obtain the synchronous data stream file of the target layout;
and outputting the synchronous data stream file of the corrected layout as the synchronous data stream file of the target layout when no error information exists in the synchronous data stream file of the corrected layout.
In some embodiments, the layout physical information includes at least one of first format pin location information, first format blocking layer location information, and first format layout boundary information;
the layout data information comprises at least one of second format pin position information, second format blocking layer position information and second format layout boundary information.
In some embodiments, the checking whether the layout physical information is erroneous based on layout design rules includes:
and checking whether a pin overlaps with a blocking layer or a layout boundary according to the first format pin position information, the first format blocking layer position information and the first format layout boundary information, and judging that the layout physical information has errors if the pin overlaps with the blocking layer and/or the layout boundary.
In some embodiments, when the layout physical information has an error, correcting the layout data information corresponding to the layout physical information in the synchronous data stream file of the initial layout includes:
if the pins overlap with the blocking layer, correcting the second format blocking layer position information corresponding to the blocking layer and/or the second format pin position information corresponding to the pins;
and if the pin overlaps with the layout boundary, correcting the position information of the pin corresponding to the pin in the second format.
In some embodiments, the first format pin location information includes first format pin coordinate information and metal layer information where the pin is located; the first format blocking layer information comprises first format blocking layer coordinate information and metal layer information of a blocking layer;
the checking whether the pin overlaps with the blocking layer or the layout boundary according to the first format pin position information, the first format blocking layer position information and the first format layout boundary information comprises the following steps:
judging whether the pin and the blocking layer are on the same layer according to the information of the metal layer where the pin is and the information of the metal layer where the blocking layer is;
and if the pin and the blocking layer are in the same layer, judging whether the pin and the blocking layer overlap or not according to the first format pin coordinate information and the first format blocking layer coordinate information.
In some embodiments, the layout physical information further includes first format pin attribute information;
the checking whether the layout physical information has errors based on the layout design rule further comprises:
checking whether the pin placement positions meet an electrical layout rule according to the first format pin position information and the first format pin attribute information;
when the layout physical information has errors, correcting the layout data information corresponding to the layout physical information in the synchronous data stream file of the initial layout, and further comprising:
and correcting the position information of the pins in the second format, corresponding to the pins with the placement positions not meeting the electrical layout rule.
In some embodiments, the checking whether the layout physical information has an error based on the layout design rule further includes:
checking whether the interval between the pin and the blocking layer meets the minimum interval constraint according to the first format pin position information and the first format blocking layer position information, and judging that the layout physical information has errors if the interval exceeds the minimum interval constraint;
when the layout physical information has errors, correcting the layout data information corresponding to the layout physical information in the synchronous data stream file of the initial layout, including:
and if the interval exceeds the minimum interval constraint, correcting the position information of the pins in the second format corresponding to the pins.
In some embodiments, after checking whether the layout physical information has an error based on the layout design rule, the method further includes:
if the layout physical information is judged to have errors, recording and outputting the layout physical information with errors;
the correcting the layout data information corresponding to the layout physical information in the synchronous data stream file of the initial layout comprises the following steps: and correcting according to the recorded and output layout physical information.
According to some embodiments, another aspect of the present application provides a layout design file modification apparatus, including:
the initial layout design file generation module is used for acquiring a library exchange format file and a synchronous data stream file of the initial layout;
the layout design file analysis module is connected with the initial layout file generation module and is used for analyzing the library exchange format file of the initial layout to acquire layout physical information in the initial layout and analyzing the synchronous data stream file of the initial layout to acquire layout data information corresponding to the layout physical information;
the layout design file correction module is connected with the layout design file analysis module and is used for checking whether the layout physical information has errors or not based on layout design rules, and correcting the layout data information corresponding to the layout physical information in the synchronous data stream file of the initial layout when the layout physical information has errors so as to obtain a synchronous data stream file of the corrected layout.
The layout design file correction method and device provided by the embodiment of the application can/at least have the following advantages:
in the embodiment of the application, a library exchange format file and a synchronous data stream file of an initial layout are acquired, the library exchange format file of the initial layout is analyzed to acquire layout physical information in the initial layout, and the synchronous data stream file of the initial layout is analyzed to acquire layout data information corresponding to the layout physical information; therefore, whether the layout physical information has errors or not can be judged by checking whether the layout physical information meets the layout design rules, the layout design is checked in time, the time consumption is short, and the error checking efficiency is high. When the layout physical information has errors, the layout data information corresponding to the layout physical information in the synchronous data stream file of the initial layout can be corrected to obtain a synchronous data stream file of the corrected layout; the correction process is simple in steps and easy to implement, has higher correction efficiency, and is beneficial to improving the accuracy of layout design.
Drawings
In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a flow chart of a layout design file modification method according to some embodiments of the present disclosure;
FIG. 2 (a) is a schematic diagram illustrating a positional relationship in which pins do not overlap with a blocking layer or a layout boundary in a layout design file correction method according to some embodiments of the present disclosure; fig. 2 (b) is a schematic diagram of a positional relationship between pins and a blocking layer and between pins and a layout boundary in a layout design file correction method according to some embodiments of the present disclosure;
FIG. 3 is a flowchart illustrating a step S300 in a layout design file modification method according to some embodiments of the present disclosure;
FIG. 4 is a flowchart illustrating a layout file modification method according to some embodiments of the present disclosure after step S400;
fig. 5 is a flowchart of a layout design file modification method according to another embodiment of the present application.
Reference numerals illustrate:
10. pins; 20. a blocking layer; 30. layout boundaries.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Examples of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention; for example, the layout physical information may be referred to as layout data information, and similarly, the layout data information may be referred to as layout physical information; the layout physical information and the layout data information are different information.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, the term "and/or" as used in this specification includes any and all combinations of the associated listed items.
In the layout design flow, the finally generated layout may not meet the process design rule of the foundry and have errors. However, the conventional layout design file correction method is inaccurate and takes long time to check and verify the layout, and the modification of the layout is complex and difficult to realize, so that the efficiency and accuracy of the layout design are seriously affected.
Based on the above, the embodiment of the application provides a layout design file correction method and device, which can be used for checking and correcting a layout, are simple in steps and easy to realize, and are beneficial to the efficiency and accuracy of layout design.
According to some embodiments, an aspect of the present application provides a layout design file modification method.
Referring to fig. 1, in some embodiments, the layout design file modification method specifically may include the following steps:
s100: and acquiring a library exchange format file and a synchronous data stream file of the initial layout.
S200: analyzing the library exchange format file of the initial layout to obtain layout physical information in the initial layout, and analyzing the synchronous data stream file of the initial layout to obtain layout data information corresponding to the layout physical information.
S300: and checking whether the layout physical information has errors or not based on the layout design rules.
S400: when the layout physical information has errors, the layout data information corresponding to the layout physical information in the synchronous data stream file of the initial layout is corrected, so that the synchronous data stream file of the corrected layout is obtained.
In the layout design file correction method provided by the embodiment, the library exchange format file and the synchronous data stream file of the initial layout are acquired, the library exchange format file of the initial layout is analyzed to acquire the layout physical information in the initial layout, and the synchronous data stream file of the initial layout is analyzed to acquire the layout data information corresponding to the layout physical information; therefore, whether the layout physical information has errors or not can be judged by checking whether the layout physical information meets the layout design rules, the layout design is checked in time, the time consumption is short, and the error checking efficiency is high. When the layout physical information has errors, the layout data information corresponding to the layout physical information in the synchronous data stream file of the initial layout can be corrected to obtain a synchronous data stream file of the corrected layout; the correction process is simple in steps and easy to implement, has higher correction efficiency, and is beneficial to improving the accuracy of layout design.
In the embodiment of the present application, the library exchange format refers to Library Exchange Format, abbreviated as LEF. The LEF file may be used to describe physical information of the original layout, such as element position, size, pitch, and layer information, among others. The synchronous data stream file refers to Graphic Data Stream file, abbreviated as GDS file, which is usually stored in binary form, also called GDSII file. The GDS file format is a storage file format commonly used in the semiconductor industry for data transfer between design tools, computers, and mask manufacturers for physical fabrication of semiconductors.
For convenience of description, the information for describing the initial layout contained in the definition library exchange format file is layout physical information, and the information corresponding to the layout physical information in the synchronous data stream file is defined as layout data information.
As an example, the layout physical information may include at least one of first format pin location information, first format blocking layer location information, and first format layout boundary information. Correspondingly, the layout data information may include at least one of second format pin position information, second format blocking layer position information, and second format layout boundary information.
It will be appreciated that in the embodiments of the present application, the first format refers to the LEF file format, and the second format refers to the GDSII file format.
As an example, the layout physical information may include first format pin location information, first format blocking layer location information, and first format layout boundary information. As understood in conjunction with fig. 2 (a) and fig. 2 (b), in some embodiments, step S300 checks whether there is an error in the layout physical information based on the layout design rule, and may specifically include the following steps:
checking whether the Pin (Pin) 10 overlaps with the blocking layer 20 or the layout boundary 30 according to the first format Pin position information, the first format blocking layer position information and the first format layout boundary information, and judging that the layout physical information is wrong if the Pin 10 overlaps with the blocking layer 20 and/or the layout boundary 30.
Fig. 2 (a) shows a case where there is no overlap of the pin 10 with either the blocking layer 20 or the layout boundary 30, and fig. 2 (b) shows a case where there is overlap of the pin 10 with both the blocking layer 20 and the layout boundary 30. Wherein, the case that the pin 10 overlaps the blocking layer 20 is shown as an area shown by a dotted line box a, and the case that the pin 10 overlaps the layout boundary 30 is shown as an area shown by a dotted line box B.
That is, if there is overlap between the pin 10 and the blocking layer 20, or between the pin 10 and the layout boundary 30, or between the pin 10 and both the blocking layer 20 and the layout boundary 30, it is determined that there is an error in the layout physical information.
Correspondingly, the layout data information may include second format pin location information and second format blocking layer location information. As an example, when the layout physical information has an error in step S400, the process of correcting the layout data information corresponding to the layout physical information in the synchronous data stream file of the initial layout may specifically include the following steps:
if the pin 10 and the blocking layer 20 overlap, correcting the position information of the blocking layer 20 corresponding to the blocking layer 20 in the second format and/or the position information of the pin 10 corresponding to the second format; and if the pin 10 overlaps the layout boundary 30, correcting the pin position information of the second format corresponding to the pin 10.
Illustratively, the second format blocking layer position information corresponding to the blocking layer 20 may be corrected, or the second format pin position information corresponding to the pin 10 may be corrected, or both the second format blocking layer position information corresponding to the blocking layer 20 and the second format pin position information corresponding to the pin 10 may be corrected.
As an example, the layout physical information may include first format pin location information and first format blocking layer location information. The first format pin position information may include first format pin coordinate information and information of a metal layer where the pin 10 is located; the first format stopper layer location information may include first format stopper layer coordinate information and metal layer information where the stopper layer 20 is located.
In some embodiments, as shown in fig. 3, in the process of executing step S300, when checking whether there is an overlap between the pin 10 and the blocking layer 20 according to the first format pin position information and the first format blocking layer position information, the following steps S311 to S312 may be specifically shown:
in step S311, it is determined whether the lead 10 is on the same level as the stopper layer 20 according to the information of the metal layer where the lead 10 is on and the information of the metal layer where the stopper layer 20 is on.
In step S312, if the pin 10 and the blocking layer 20 are in the same layer, it is determined whether the pin 10 overlaps the blocking layer 20 according to the first format pin coordinate information and the first format blocking layer coordinate information.
It will be appreciated that the layout data information may include pin location information in the second format, respectively. Wherein the second format pin location information may include second format pin coordinate information.
In some embodiments, the layout physical information may also include first format pin attribute information. Correspondingly, the layout data information can also comprise second format pin attribute information.
In the embodiment of the present application, the pin attribute information refers to that the pin is an input pin or the pin is an output pin.
In some embodiments, step S300 checks whether the layout physical information is erroneous based on the layout design rule, and may further include the following steps:
and checking whether the placement positions of the pins 10 meet the electrical layout rules according to the first format pin position information and the first format pin attribute information.
It is understood that the layout design rules include electrical layout rules; if the placement position of the pin 10 does not meet the electrical layout rule, judging that the layout physical information has errors.
In some embodiments, when the layout physical information has an error in step S400, the process of correcting the layout data information corresponding to the layout physical information in the synchronous data stream file of the initial layout may further include the following steps:
and correcting the pin position information of the second format corresponding to the pins 10 with the placement positions not meeting the electrical layout rule.
As an example, the layout physical information may include first format pin location information and first format blocking layer location information. In some embodiments, step S300 checks whether the layout physical information is erroneous based on the layout design rule, and may further include the following steps:
and checking whether the distance between the pin 10 and the blocking layer 20 meets the minimum distance constraint according to the first format pin position information and the first format blocking layer position information, and judging that the layout physical information has errors if the distance exceeds the minimum distance constraint.
Correspondingly, the layout data information may include pin location information in the second format. In some embodiments, when the layout physical information has an error in step S400, the method corrects the layout data information corresponding to the layout physical information in the synchronous data stream file of the initial layout, and may further include the following steps:
and if the interval exceeds the minimum interval constraint, correcting the position information of the pins of the second format corresponding to the pins 10.
In some embodiments, after checking whether the layout physical information has an error based on the layout design rule in step S300, the layout design file correction method may further include the following steps:
if the layout physical information is judged to be in error, the layout physical information in error is recorded and output.
The step of recording and outputting the layout physical information with errors and the step S400 are not limited in sequence; i.e., either performed before or simultaneously, is permissible.
As an example, the modification of the layout data information corresponding to the layout physical information in the synchronous data stream file of the initial layout in step S400 may be specifically expressed as:
and correcting the layout data information corresponding to the layout physical information in the synchronous data stream file of the initial layout according to the layout physical information recorded and output in the steps.
In some embodiments, after correcting the layout data information corresponding to the layout physical information in the synchronous data stream file of the initial layout when the layout physical information has an error in step S400, the layout design file correction method may further include the following steps:
and recording and outputting correction information for correcting the layout data information.
Referring to fig. 4, in some embodiments, the layout design file modification method may further include the following steps:
s500: and verifying the synchronous data stream file of the corrected layout.
S600: when error information exists in the synchronous data stream file of the corrected layout, correcting the error information to obtain the synchronous data stream file of the target layout.
S700: and outputting the synchronous data stream file of the corrected layout as the synchronous data stream file of the target layout when no error information exists in the synchronous data stream file of the corrected layout.
It will be appreciated that steps S500 to S700 described above should be performed after the corrected layout synchronization data stream file is obtained in step S400.
As an example, in step S500, the synchronous data stream file of the corrected layout may be verified by the layout engineer; for example, if the verification result is that there is error information in the synchronous data stream file of the corrected layout, in step S600, the layout engineer may manually correct the error information to obtain the synchronous data stream file of the target layout.
One embodiment of the present application is described in detail below in conjunction with fig. 5.
Firstly, acquiring LEF files and GDSII files of the same initial layout, and keeping information consistency.
Respectively analyzing the LEF file and the GDSII file; the LEF file is analyzed to obtain layout physical information in the initial layout, whether errors exist in the initial layout or not is checked in the subsequent steps, the GDSII file is analyzed to obtain layout data information corresponding to the layout physical information, and the layout data information is used for correction in the subsequent steps.
Then, checking the LEF file; specifically, it refers to checking whether the layout physical information has errors based on the layout design rules. Illustratively, it may include checking pin attribute information, pin location information, the positional relationship of pins 10 with blocking layer 20 and layout boundary 30, and so forth.
Finding out pins which do not meet the layout design rule, judging that the layout physical information is wrong according to the pins, and recording and outputting the layout physical information with the errors; specifically, after a pin which does not meet the layout design rule is found, information which does not meet the requirement can be recorded and output.
When the layout physical information has errors, correcting the layout data information corresponding to the layout physical information in the GDSII file; specifically, the GDSII file is automatically optimized according to the detected content in the previous step, and the pin attribute information is modified mainly according to the layout design rule, and/or the pin coordinate information is modified to meet the layout design rule.
Outputting a synchronous data stream file for obtaining a corrected layout, and simultaneously recording and outputting correction information for correcting layout data information; specifically, the method refers to outputting the optimized GDSII file, recording the optimized detail information and outputting the optimized detail information.
After that, verifying the synchronous data stream file of the corrected layout; in particular, the verification can be performed by a layout engineer.
If the verification finds that the error information exists in the synchronous data stream file of the corrected layout, correcting the error information; specifically, if a personal error is checked in the above steps, the layout engineer can make manual modification.
It should be understood that, although the steps in the flowcharts of fig. 1, 3 to 5 are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps of fig. 1, 3-5 may include a plurality of steps or stages that are not necessarily performed at the same time, but may be performed at different times, nor does the order in which the steps or stages are performed necessarily occur sequentially, but may be performed alternately or alternately with at least a portion of the steps or stages in other steps or other steps.
According to some embodiments, another aspect of the present application provides a layout file modification device, which may be used to perform the layout file modification method described in the foregoing embodiments. Therefore, the above-mentioned layout design file correction method can achieve the technical effects that the layout design file correction device can also achieve, and detailed description thereof is omitted herein.
In some embodiments, the layout design file modification device may include an initial layout design file generation module, a layout design file parsing module, and a layout design file modification module.
The initial layout design file generation module is used for acquiring a library exchange format file and a synchronous data stream file of the initial layout.
The layout design file analysis module is connected with the initial layout design file generation module and is used for analyzing the library exchange format file of the initial layout to acquire the layout physical information in the initial layout and analyzing the synchronous data stream file of the initial layout to acquire the layout data information corresponding to the layout physical information.
The layout design file correction module is connected with the layout design file analysis module and is used for checking whether the layout physical information has errors based on the layout design rules and correcting the layout data information corresponding to the layout physical information in the synchronous data stream file of the initial layout when the layout physical information has errors so as to obtain the synchronous data stream file of the corrected layout.
It should be noted that, the specific limitation of the layout design file correction device may be referred to the limitation of the layout design file correction method, and will not be described herein. All or part of each module in the layout design file correction device can be realized by software, hardware and a combination thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules. It should be noted that, in the embodiment of the present application, the division of the modules is schematic, which is merely a logic function division, and other division manners may be implemented in actual implementation.
In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "ideal embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (8)
1. A layout design file correction method is characterized by comprising the following steps:
acquiring a library exchange format file and a synchronous data stream file of an initial layout;
analyzing a library exchange format file of the initial layout to obtain layout physical information in the initial layout, and analyzing a synchronous data stream file of the initial layout to obtain layout data information corresponding to the layout physical information, wherein the layout physical information comprises at least one of first-format pin position information, first-format blocking layer position information and first-format layout boundary information, and the layout data information comprises at least one of second-format pin position information, second-format blocking layer position information and second-format layout boundary information;
checking whether the layout physical information has errors or not based on layout design rules; wherein, based on the layout design rule, checking whether the layout physical information has errors comprises the following steps: checking whether a pin overlaps with a blocking layer or a layout boundary according to the first format pin position information, the first format blocking layer position information and the first format layout boundary information, and judging that the layout physical information has errors if the pin corresponding to the first format pin position information overlaps with the blocking layer corresponding to the first format blocking layer position information and/or the layout boundary corresponding to the first format layout boundary information;
when the layout physical information has errors, correcting the layout data information corresponding to the layout physical information in the synchronous data stream file of the initial layout to obtain a synchronous data stream file of the corrected layout; when the layout physical information has errors, correcting the layout data information corresponding to the layout physical information in the synchronous data stream file of the initial layout to obtain a synchronous data stream file of a corrected layout, wherein the step of obtaining the synchronous data stream file of the corrected layout comprises the following steps: if the pins overlap with the blocking layer, correcting the second format blocking layer position information corresponding to the blocking layer and/or the second format pin position information corresponding to the pins; and if the pin overlaps with the layout boundary, correcting the position information of the pin corresponding to the pin in the second format.
2. The layout design file modification method according to claim 1, further comprising:
verifying the synchronous data stream file of the corrected layout;
when error information exists in the synchronous data stream file of the corrected layout, correcting the error information to obtain the synchronous data stream file of the target layout;
and outputting the synchronous data stream file of the corrected layout as the synchronous data stream file of the target layout when no error information exists in the synchronous data stream file of the corrected layout.
3. The layout design file modification method according to claim 1, wherein the first format pin position information includes first format pin coordinate information and pin-located metal layer information; the first format blocking layer information comprises first format blocking layer coordinate information and metal layer information of a blocking layer;
the checking whether the pin overlaps with the blocking layer or the layout boundary according to the first format pin position information, the first format blocking layer position information and the first format layout boundary information comprises the following steps:
judging whether the pin and the blocking layer are on the same layer according to the information of the metal layer where the pin is and the information of the metal layer where the blocking layer is;
and if the pin and the blocking layer are in the same layer, judging whether the pin and the blocking layer overlap or not according to the first format pin coordinate information and the first format blocking layer coordinate information.
4. The layout design file modification method according to claim 1, wherein the layout physical information further comprises first format pin attribute information;
the checking whether the layout physical information has errors based on the layout design rule further comprises:
checking whether the placement positions of pins corresponding to the first format pin position information meet an electrical layout rule according to the first format pin position information and the first format pin attribute information;
when the layout physical information has errors, correcting the layout data information corresponding to the layout physical information in the synchronous data stream file of the initial layout, and further comprising:
and correcting the position information of the pins in the second format, corresponding to the pins with the placement positions not meeting the electrical layout rule.
5. The method according to claim 4, wherein the first format pin attribute information includes pin information as input pin information or pin information as output pin information.
6. The layout design file modification method according to claim 1, wherein the checking whether the layout physical information has an error based on a layout design rule further comprises:
checking whether the distance between a pin corresponding to the first format pin position information and a blocking layer corresponding to the first format blocking layer position information meets the minimum distance constraint according to the first format pin position information and the first format blocking layer position information, and judging that the layout physical information has errors if the distance exceeds the minimum distance constraint;
when the layout physical information has errors, correcting the layout data information corresponding to the layout physical information in the synchronous data stream file of the initial layout, including:
and if the distance exceeds the minimum distance constraint, correcting the position information of the pins in the second format corresponding to the pins.
7. The layout design file modification method according to claim 1 or 2, wherein after checking whether the layout physical information has an error based on a layout design rule, further comprising:
if the layout physical information is judged to have errors, recording and outputting the layout physical information with errors;
the correcting the layout data information corresponding to the layout physical information in the synchronous data stream file of the initial layout comprises the following steps: and correcting according to the recorded and output layout physical information.
8. A layout design file correction apparatus, comprising:
the initial layout design file generation module is used for acquiring a library exchange format file and a synchronous data stream file of the initial layout;
the layout design file analysis module is connected with the initial layout file generation module and is used for analyzing the library exchange format file of the initial layout to acquire layout physical information in the initial layout and analyzing the synchronous data stream file of the initial layout to acquire layout data information corresponding to the layout physical information, wherein the layout physical information comprises at least one of first format pin position information, first format blocking layer position information and first format layout boundary information, and the layout data information comprises at least one of second format pin position information, second format blocking layer position information and second format layout boundary information;
the layout design file correction module is connected with the layout design file analysis module and is used for checking whether the layout physical information has errors or not based on layout design rules, and correcting the layout data information corresponding to the layout physical information in the synchronous data stream file of the initial layout when the layout physical information has errors so as to obtain a synchronous data stream file of the corrected layout;
wherein, based on the layout design rule, checking whether the layout physical information has errors comprises the following steps: checking whether a pin overlaps with a blocking layer or a layout boundary according to the first format pin position information, the first format blocking layer position information and the first format layout boundary information, and judging that the layout physical information has errors if the pin corresponding to the first format pin position information overlaps with the blocking layer corresponding to the first format blocking layer position information and/or the layout boundary corresponding to the first format layout boundary information;
when the layout physical information has errors, correcting the layout data information corresponding to the layout physical information in the synchronous data stream file of the initial layout to obtain a synchronous data stream file of the corrected layout, wherein the step of obtaining the synchronous data stream file of the corrected layout comprises the following steps: if the pins overlap with the blocking layer, correcting the second format blocking layer position information corresponding to the blocking layer and/or the second format pin position information corresponding to the pins; and if the pin overlaps with the layout boundary, correcting the position information of the pin corresponding to the pin in the second format.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104655062A (en) * | 2013-11-19 | 2015-05-27 | 鸿富锦精密工业(武汉)有限公司 | Circuit board chip pin information detection method and device |
| CN107590303A (en) * | 2017-07-17 | 2018-01-16 | 上海华虹宏力半导体制造有限公司 | The quick method searched and correct abnormal graph in layout data |
| CN115249004A (en) * | 2022-04-12 | 2022-10-28 | 杰华特微电子股份有限公司 | Physical verification method for integrated circuit layout design, electronic device and storage medium |
| CN116402003A (en) * | 2023-04-07 | 2023-07-07 | 山东云海国创云计算装备产业创新中心有限公司 | Chip design method, system, device and storage medium |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104655062A (en) * | 2013-11-19 | 2015-05-27 | 鸿富锦精密工业(武汉)有限公司 | Circuit board chip pin information detection method and device |
| CN107590303A (en) * | 2017-07-17 | 2018-01-16 | 上海华虹宏力半导体制造有限公司 | The quick method searched and correct abnormal graph in layout data |
| CN115249004A (en) * | 2022-04-12 | 2022-10-28 | 杰华特微电子股份有限公司 | Physical verification method for integrated circuit layout design, electronic device and storage medium |
| CN116402003A (en) * | 2023-04-07 | 2023-07-07 | 山东云海国创云计算装备产业创新中心有限公司 | Chip design method, system, device and storage medium |
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