CN117391021A - Simulation model accuracy verification method and system - Google Patents

Abstract

A method and a system for checking the accuracy of a simulation model, wherein the method comprises the following steps: constructing a simulation signal path and a test signal path, wherein the simulation signal path comprises a simulation model to be tested, the test signal path comprises a serial deserializer interface circuit corresponding to the simulation signal path, and the test signal path further comprises signal measurement equipment connected with the serial deserializer interface circuit, and setting parameters of the simulation signal path and the test signal path are the same; assigning values for the adjustable parameters of the simulation signal path and the test signal path, and operating simulation on the simulation signal path to obtain a simulation signal waveform; running a test on the test signal path to obtain a test signal waveform; and comparing the simulation signal waveform with the test signal waveform, and judging the accuracy of the simulation model to be tested according to the comparison result.

Description

Simulation model accuracy verification method and system

Technical Field

The present disclosure relates to the field of chip design technologies, and in particular, to a method and a system for verifying accuracy of a simulation model.

Background

The current high-speed digital signals have higher and higher speed, and problems, such as jitter, crosstalk and the like, are also more and more increased. The active time domain simulation is established, and the high-speed link design can be comprehensively and efficiently evaluated. One of the important elements in time domain simulation is the IBIS-AMI model, which is used to model the behavior characteristics of active devices. The accuracy of the AMI model is directly related to influence the reliability of the simulation result. However, there is currently no unified standard within the industry to verify model accuracy.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

The embodiment of the disclosure provides an accuracy checking method of a simulation model, comprising the following steps:

constructing a simulation signal path and a test signal path, wherein the simulation signal path comprises a simulation model to be tested, the test signal path comprises a serial deserializer interface circuit corresponding to the simulation signal path, and the test signal path further comprises signal measurement equipment connected with the serial deserializer interface circuit, and setting parameters of the simulation signal path and the test signal path are the same;

assigning values for the adjustable parameters of the simulation signal path and the test signal path, and operating simulation on the simulation signal path to obtain a simulation signal waveform; running a test on the test signal path to obtain a test signal waveform;

and comparing the simulation signal waveform with the test signal waveform, and judging the accuracy of the simulation model to be tested according to the comparison result.

The embodiment of the disclosure also provides an accuracy checking system of the simulation model, comprising: the device comprises a simulation signal path, a test signal path and an accuracy checking device, wherein the simulation signal path comprises a simulation model to be tested, the test signal path comprises a serial deserializer interface circuit corresponding to the simulation signal path, and the device further comprises signal measuring equipment connected with the serial deserializer interface circuit, and setting parameters of the simulation signal path and the test signal path are the same;

the accuracy checking device is configured to assign values to the adjustable parameters of the simulation signal path and the test signal path, and operate simulation on the simulation signal path to obtain a simulation signal waveform; running a test on the test signal path to obtain a test signal waveform; and comparing the simulation signal waveform with the test signal waveform, and judging the accuracy of the simulation model to be tested according to the comparison result.

According to the accuracy verification method and the accuracy verification system for the simulation model, through constructing a simulation signal path and a test signal path, setting parameters of the simulation signal path and the test signal path are the same, and simulation is performed on the simulation signal path to obtain a simulation signal waveform; and running test on the test signal path to obtain a test signal waveform, comparing the simulation signal waveform with the test signal waveform, judging the accuracy of the simulation model to be tested according to a comparison result, creatively providing a comparison method of simulation and test, accurately verifying the accuracy of the simulation model, compressing margin to the maximum extent when designing a PCB high-speed channel, and saving cost.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. Other advantages of the present application may be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

The accompanying drawings are included to provide an understanding of the technical aspects of the present disclosure, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present disclosure and together with the embodiments of the disclosure, not to limit the technical aspects of the present disclosure.

FIG. 1 is a flow chart of a method for verifying the accuracy of a simulation model according to an exemplary embodiment of the present disclosure;

FIG. 2A is a schematic diagram of an emulated signal path, according to an example embodiment of the present disclosure;

FIG. 2B is a schematic diagram of a test signal path according to an exemplary embodiment of the present disclosure;

FIG. 2C is a schematic diagram of a serial deserializer interface circuit according to an exemplary embodiment of the present disclosure;

fig. 3A to 3G are schematic diagrams of simulation signal waveforms and test signal waveforms corresponding to seven sets of adjustable parameter combinations in the PRBS mode;

FIG. 4 is a schematic diagram of a quality factor calculation method according to an exemplary embodiment of the disclosure;

fig. 5A to 5G are schematic diagrams of simulation signal waveforms and test signal waveforms corresponding to seven sets of adjustable parameter combinations in a slow clock mode;

fig. 6A to fig. 6C are schematic diagrams of simulated signal waveforms and test signal waveforms corresponding to combinations of three sets of adjustable parameter extremum values in the slow clock mode;

fig. 7A to 7B are schematic diagrams of eye height and eye width of a receiving end corresponding to the values of the main mark and the post mark before scanning;

fig. 7C to 7D are schematic diagrams of the receiving end eye height and eye width corresponding to the scanned values of the main marks and the front marks.

Detailed Description

The present application describes a number of embodiments, but the description is illustrative and not limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or in place of any other feature or element of any other embodiment unless specifically limited.

The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements of the present disclosure may also be combined with any conventional features or elements to form a unique inventive arrangement as defined in the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive arrangements to form another unique inventive arrangement as defined in the claims. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not to be restricted except in light of the attached claims and their equivalents. Further, various modifications and changes may be made within the scope of the appended claims.

Furthermore, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other sequences of steps are possible as will be appreciated by those of ordinary skill in the art. Accordingly, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Furthermore, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.

Unless otherwise defined, technical or scientific terms used in the disclosure of the embodiments of the present disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present disclosure pertains. The terms "first," "second," and the like, as used in embodiments of the present disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, is intended to mean that elements or items preceding the word encompass the elements or items listed thereafter and equivalents thereof without precluding other elements or items.

As shown in fig. 1, an embodiment of the present disclosure provides a method for checking accuracy of a simulation model, which is characterized by comprising:

step 101, constructing a simulation signal path and a test signal path, wherein the simulation signal path comprises a simulation model to be tested, the test signal path comprises a serial deserializer interface circuit corresponding to the simulation signal path, and the test signal path further comprises signal measurement equipment connected with the serial deserializer interface circuit, and setting parameters of the simulation signal path and the test signal path are the same;

102, assigning values for adjustable parameters of a simulation signal path and a test signal path, and operating simulation on the simulation signal path to obtain a simulation signal waveform; running a test on the test signal path to obtain a test signal waveform;

and step 103, comparing the simulation signal waveform with the test signal waveform, and judging the accuracy of the simulation model to be tested according to the comparison result.

According to the accuracy verification method for the simulation model, provided by the embodiment of the disclosure, the simulation signal path and the test signal path are constructed, the setting parameters of the simulation signal path and the test signal path are the same, and the simulation is performed on the simulation signal path to obtain a simulation signal waveform; and running test on the test signal path to obtain a test signal waveform, comparing the simulation signal waveform with the test signal waveform, judging the accuracy of the simulation model to be tested according to the comparison result, and creatively providing a comparison method of simulation and test for verifying the accuracy of the simulation model.

In some exemplary embodiments, the emulation signal path is a signal path from an emulation model to be tested to a connector model, and the SERializer-deserializer interface circuit is a signal path from a serial deserializer (SERializer/DESerializer, serDes) buffer to a connector.

In some exemplary embodiments, the simulation model to be tested may be an Input/output buffer information Specification (IBIS) model, or may be other models. In some example embodiments, the IBIS model may be an algorithmic modeling interface (Algorithmic Modeling Interface, AMI) model. However, the embodiments of the present disclosure are not limited thereto.

In some exemplary implementations, the connector may be a SFP (Small Form Factor Pluggable) optical module, however, embodiments of the present disclosure are not limited in this regard. The SFP optical module is a hot pluggable optical transceiver independent of a communication protocol, and is convenient to use and small in test error. In other exemplary embodiments, the connector may also be a coaxial connector or the like.

In some exemplary implementations, the signal measurement device may be an oscilloscope, however, embodiments of the present disclosure are not limited in this regard.

2A-2C, the emulation signal path is a signal path from a programmable logic device (Field-Programmable Gate Array, FPGA) AMI model of Siberian (Xilinx) to an SFP optical module, and the test signal path includes a serializer-deserializer interface circuit disposed on a PCB board, and an oscilloscope connected to the serializer-deserializer interface circuit by a cable. The serial deserializer interface circuit is a path from the FPGA to the SFP optical module.

In the embodiment of the disclosure, the FPGA and the SFP optical module can both use an IBIS-AMI model, the model is obtained from a device supplier, the simulation path is shown in fig. 2A, the sending end is the AMI model of the FPGA, the receiving end is the SFP optical module, and the simulation model to be tested is the FPGA.

In the embodiment of the disclosure, the FPGA is taken as a simulation model to be tested, the SFP optical module is taken as a connector model for illustration, and in other examples, the simulation signal path may be a signal path with other structures, for example, the simulation signal path may include other models in addition to the simulation model to be tested and the connector model; the simulation model to be tested can be positioned at the signal transmitting end or the signal receiving end; the connector model may be an optical module, a coaxial connector, or the like. The embodiments of the present disclosure are not limited in this regard.

In some exemplary embodiments, the serial deserializer interface circuit includes a serial deserializer buffer, with the set parameters of the emulation signal path and the test signal path being the same, including:

the signal rate and the output code pattern of the simulation model to be tested are the same as those of the SerDes buffer;

the scattering parameters of the emulated signal path are the same as the scattering parameters of the serializer-deserializer interface circuit.

In the embodiment of the disclosure, a test platform is firstly built, the test platform comprises a PCB board, a cable and a high-speed oscilloscope, after the test platform is built, the passive path characteristics of the test signal path, namely the scattering parameter (S parameter) characteristics, are extracted, and the extracted S parameter characteristics are imported into simulation software (which may be advanced design system (Advanced Design system, ADS) software, however, the embodiment of the disclosure is not limited thereto) so that the scattering parameters of the simulation signal path are the same as those of the test signal path.

The scattering parameter (Scattering parameter, S parameter) is an important parameter in microwave transmission. Because the S parameter reflects the characteristics of the component reflected signal and the transmitted signal, the S parameter includes the reflected parameters, such as S11, S22, etc.; transmission parameters such as S12, S21, etc. S12 is a reverse transmission coefficient, that is, an isolation coefficient. S21 is a forward transmission coefficient, that is, an insertion loss (gain) coefficient. S11 is the input reflection coefficient, i.e. the input return loss, and S22 is the output reflection coefficient, i.e. the output return loss.

Next, the test platform set-up and the dummy signal path set-up are aligned. The test settings need to be the same as the simulation settings, including: signal rate, output pattern, etc.

In some exemplary implementations, the signal rate of the simulation model under test may be 10Gbps, however, embodiments of the present disclosure are not limited thereto.

In some exemplary embodiments, the output pattern of the simulation model under test includes: pseudo-random binary sequence (PRBS) code, consecutive binary sequence code comprising a binary sequence occurring periodically, each period of consecutive binary sequence code comprising N consecutive 0 s and M consecutive 1 s, N and M each being a natural number greater than or equal to 4.

The pseudo-random binary sequence refers to a pseudo-random sequence only comprising 0 and 1, and the pseudo-random binary sequence is a binary code sequence which can be predetermined, can be repeatedly generated and copied and has random statistical characteristics. In modern engineering practice, pseudo-random signals have been widely used in the fields of mobile communications, navigation, radar and secret communications, measurement of communication system performance, etc. The cycle length of the PRBS code is related to its order, and the common orders are 7, 9, 11, 15, 20, 23, 31, etc., that is, PRBS7, PRBS9, PRBS11, PRBS15, PRBS20, PRBS23, PRBS31, etc. which we will call. For an n-order PRBS code, the sequence length of each period is 2n-1, in each period, "0" and "1" are randomly distributed, the number of "0" and "1" are equal, the maximum number of consecutive "1" is n, and the maximum number of consecutive "0" is n-1 (n-1 consecutive "1" and n consecutive "0" after inversion).

In some exemplary embodiments, the adjustable parameters include: a main label (maincurror), a pre-label (prefursor) and a post-label (Postcursor).

The transmission model of the FPGA of the siren has three adjustable parameters: maincursor, precuror, postcuror. The effect of these three parameters on the signal is as follows: maincursor affects signal swing, and prefursor and Postcursor are used to de-emphasize the signal. In the chip design process, the three parameter values need to be adjusted to make the signal at the receiving end meet the preset eye pattern requirement. Often, the parameters cannot be adjusted in place in one step, but the parameters are grouped for simulation according to the characteristics of the passive channel, and finally, a group of most suitable values are found.

In some exemplary embodiments, assigning values to adjustable parameters of the simulated signal path and the test signal path includes:

acquiring the value range of each adjustable parameter;

according to the value range and channel loss of each adjustable parameter, setting n groups of adjustable parameter combinations to be tested, wherein n is a natural number greater than or equal to 1.

Illustratively, assuming a signal rate set to 10Gbps, the FPGA output pattern is set to PRBS7. The loss of the channel is-15 dB@5GHz, the Maincursor value range is 0-20, the Precursor value range is 0-30, and the PostCursor value range is 0-30. As shown in table 1, seven sets of adjustable parameter combinations were set according to the loss and experience of the channel, and simulation and test were performed for the seven sets of adjustable parameters, respectively.

Combination of two or more kinds of materials	Main cursor	Precursor	Postcursor
				1	15	0	0
2	8	5	0
				3	8	10	0
4	8	0	5
				5	8	0	10
6	8	5	5
				7	8	10	10

TABLE 1

The simulated signal waveform and the test signal waveform at the receiving end under the seven sets of parameter combinations are acquired as shown in fig. 3A to 3F. And comparing the simulation signal waveform with the test signal waveform, and judging the accuracy of the simulation model to be tested according to the comparison result.

In some exemplary embodiments, the simulated signal waveforms include a fast mode signal waveform, a typical mode signal waveform, and a slow mode signal waveform.

In signal waveform simulation, the following combinations of working conditions are set for analysis:

the process is slowest (slow), the temperature is highest, the voltage is lowest, and the waveform output by the working condition is a slow mode signal waveform;

a typical (typicai) process, where temperature is nominal and voltage is nominal, the operating condition corresponds to the output waveform being a typical mode signal waveform.

The process is fastest, the temperature is lowest, the voltage is highest, and the waveform output by the working condition is the waveform of the fast mode signal.

In some exemplary embodiments, determining accuracy of the simulation model to be tested based on the comparison result includes:

when the test signal waveform is between the fast mode signal waveform and the slow mode signal waveform, determining that the accuracy of the simulation model to be tested is high;

when the test signal waveform is above the fast mode signal waveform or below the slow mode signal waveform, the accuracy of the simulation model to be tested is determined to be low.

As can be seen from fig. 3A to 3F, the test signal waveform is between the fast mode signal waveform and the slow mode signal waveform and is close to the fast mode signal waveform, so that the accuracy of determining the simulation model to be tested is higher.

In other exemplary embodiments, determining accuracy of the simulation model to be tested based on the comparison results includes:

the quality factor FOM between the test signal waveform and the dummy signal waveform (exemplary, where the dummy signal waveform may be a typical mode signal waveform) is calculated as follows:

wherein N is the number of sampling points, deltaX is the interval between adjacent sampling points, and X _i (sim) is the amplitude value of the simulated signal waveform; x is X _i (meas) is the amplitude value of the test signal waveform;

when the quality factor FOM is larger than or equal to a preset quality factor threshold value, determining that the accuracy of the simulation model to be detected is high; and when the quality factor FOM is smaller than a preset quality factor threshold, determining that the accuracy of the simulation model to be detected is low.

The disclosed embodiments quantify the comparison of simulations and tests by employing the quality factor FOM method. As shown in fig. 4, the quality factor FOM can be understood as the ratio of the area of the shadow portion to the entire waveform area, and the smaller the area of the shadow portion, the larger the FOM value, which indicates the better the simulation and test match. The values and matching results of the quality factor FOM are shown in table 2.

TABLE 2

The quality factor calculation results obtained for the 7 sets of adjustable parameter combinations applied to this case are shown in table 3.

Case	Main cursor	Precursor	Postcursor	FOM
					1	15	0	0	95.4％
2	8	5	0	95.1％
					3	8	10	0	94.8％
4	8	0	5	95％
					5	8	0	10	94.9％
6	8	5	5	95.2％
					7	8	10	10	95％

TABLE 3 Table 3

As can be seen from table 3, the simulation and test results of the seven sets of adjustable parameters of the present embodiment are excellent or good. If the FOM value corresponding to one group of adjustable parameters is below 90%, the model corresponding to the combination of the group of adjustable parameters is inaccurate, and the model should avoid taking the values of the group of adjustable parameters.

The PRBS7 is adopted as the output code pattern, and the influence of three adjustable parameters on the waveform cannot be obviously reflected from the comparison result because the PRBS7 code pattern changes fast.

In other exemplary embodiments, the output pattern of the simulation model under test includes: consecutive binary sequence codes, the consecutive binary sequence codes comprising a binary sequence of periodic occurrences, the period of each consecutive binary sequence code comprising N consecutive "0" s and M consecutive "1 s, N and M each being a natural number greater than or equal to 4.

The present embodiment uses another mode (which may be called a slow clock mode) to perform the simulated comparison, and the mode no longer uses a continuously variable code pattern excitation, but uses a code pattern of continuous "0" and continuous "1", that is, each period includes several continuous "0" s and several continuous "1" s, for example, each period includes eight continuous "0" s and eight continuous "1" s, so as to obviously observe the influence of three adjustable parameters on the waveform of the receiving end.

The slow clock mode simulation and test of this example was also performed with the combination of 7 adjustable parameters of table 1, and the comparison results are shown in fig. 5A to 5G. By means of the slow clock mode, it is possible to clearly observe that the edges of the waveform are affected by different adjustable parameter combinations. As can be seen from fig. 5A to 5G, the prefursor and Postcursor affect the edges of the signal, the prefursor affects the rising edges of the signal, and the Postcursor affects the falling edges of the signal. In this embodiment, the test signal waveform is also between the fast mode signal waveform and the slow mode signal waveform and is close to the fast mode signal waveform, so that the accuracy of determining the simulation model to be tested is higher.

In some exemplary embodiments, the n sets of adjustable parameter combinations to be tested include at least one set of limit combinations, the values of the front and/or rear markers in the limit combinations being usable limit values. In the disclosed embodiments, the limit value may be a maximum value or a minimum value.

To adequately verify the parameters of the AMI model, in this embodiment, one or more sets of available limit values may be taken for the adjustable parameters. Illustratively, as shown in Table 4, three sets of adjustable parameter limit value combinations are set for which simulations and tests were performed, respectively (Precursor and Postcursor do not take 30 because 20 is typically the maximum available) based on experience 30. It is generally only necessary to set the limit values available for the prescursor and Postcursor, since these two parameters have a relatively large influence on the waveform. By setting the adjustable parameter limit value combination, the compared test waveform and simulation waveform more obviously reflect the effects of three adjustable parameters, and as can be seen from fig. 6A to 6C, the test signal waveform is also between the fast mode signal waveform and the slow mode signal waveform and is close to the fast mode signal waveform, so that the accuracy of the simulation model to be detected can be determined to be higher, and the influence of the preforr and the Postcursor on the rising edge and the falling edge of the signal waveform respectively can be seen.

Limit combination	Main cursor	Precursor	Postcursor
				1	8	0	0
2	8	20	0
				3	8	0	20

TABLE 4 Table 4

When the PRBS mode simulates continuous and rapid change of signals, the waveform change condition of the receiving end is simulated; when the signal is simulated through the slow clock mode and the code pattern of 0 and 1 is used, namely the waveform of the receiving end changes slowly. In the PRBS mode, trend simulation analysis can be performed in addition to comparing the simulation waveforms and the test waveforms corresponding to the 7 groups of adjustable parameter combinations. The trend analysis refers to fixing the values of two adjustable parameters, scanning the value of the third adjustable parameter, and then printing the height and width values in the eye diagram of the receiving end into a comparison graph respectively, so that the influence of the preforr and the Postcursor on the eye diagram of the receiving end can be observed.

In some exemplary embodiments, the method further comprises:

acquiring the value range of each adjustable parameter;

fixing the values of the main mark and the rear mark, gradually taking the values of the front mark from the minimum value to the maximum value according to a preset interval, and running simulation and test for each front mark value to obtain the eye height and the eye width of the eye pattern of the receiving end corresponding to each front mark value;

and determining the influence of the front marks on the eye pattern according to the eye height and the eye width of the eye pattern of the receiving end corresponding to each front mark value.

As shown in fig. 7A to 7B, the eye height and eye width data of the receiving-end eye pattern are printed out by fixing maincursor=8, postcursor=0, scanning prefursor from 0 to 20. In fig. 7A, the abscissa represents the value of preforr, and the ordinate represents the eye height in millivolts. In fig. 7B, the abscissa represents the value of prefursor, and the ordinate represents the eye width in picoseconds, and it can be seen from fig. 7A and 7B that the trend of the test point is the same as the trend corresponding to the simulation.

In some exemplary embodiments, the method further comprises:

acquiring the value range of each adjustable parameter;

fixing the values of the main mark and the front mark, gradually taking the values of the rear mark from the minimum value to the maximum value according to a preset interval, and running simulation and test for each value of the rear mark to obtain the eye height and the eye width of the eye pattern of the receiving end corresponding to each value of the rear mark;

and determining the influence of the rear marks on the eye pattern according to the eye height and the eye width of the eye pattern of the receiving end corresponding to each rear mark value.

As shown in fig. 7C to 7D, the eye height and eye width data of the receiving-end eye pattern are printed out by fixing maincursor=8, prefursor=0, scanning Postcursor from 0 to 30. In fig. 7C, the abscissa represents the value of Postcursor, and the ordinate represents the eye height in millivolts. In fig. 7D, the abscissa represents the value of Postcursor, and the ordinate represents the eye width in picoseconds, and it can be seen from fig. 7C and 7D that the trend of the test point is the same as the trend corresponding to the simulation. As can be seen from fig. 3A to 3G, fig. 5A to 5G, fig. 6A to 6C, and fig. 7A to 7D, the simulation and test results in the above three modes (PRBS mode, slow clock mode, and trend-simulated test analysis mode) are all identical, and thus, the test and simulation comparison results fully demonstrate the accuracy of the IBIS-AMI model.

The accuracy verification method of the simulation model provided by the embodiment of the disclosure provides a method for verifying the accuracy (degree) of the AMI model, and makes up for the fact that the accuracy of the AMI model cannot be verified in the prior art.

The embodiment of the disclosure also provides an accuracy checking system of the simulation model, comprising: the device comprises a simulation signal path, a test signal path and an accuracy checking device, wherein the simulation signal path comprises a simulation model to be tested, the test signal path comprises a serial deserializer interface circuit corresponding to the simulation signal path, and the device further comprises signal measuring equipment connected with the serial deserializer interface circuit, and setting parameters of the simulation signal path and the test signal path are the same;

the accuracy checking device is configured to assign values to the adjustable parameters of the simulation signal path and the test signal path, and operate simulation on the simulation signal path to obtain a simulation signal waveform; running a test on the test signal path to obtain a test signal waveform; and comparing the simulation signal waveform with the test signal waveform, and judging the accuracy of the simulation model to be tested according to the comparison result.

In this embodiment, how the accuracy checking device performs accuracy checking on the simulation model to be tested specifically may be described in the foregoing, and will not be described herein again.

The accuracy checking method and the accuracy checking system for the simulation model can compress the margin to the maximum extent and save the cost when designing the PCB high-speed channel. When designing a high-speed channel, in the case that the accuracy of the model is unknown, more margin is reserved while the eye requirement is met, for example, the eye height required by the standard is minimum 100mV, and the simulation is usually based on more than 150mV to cover the error caused by the accuracy of the model. After the accuracy of the model is clarified through the method disclosed by the invention, the design can be made with smaller margin, so that the cost is reduced and the design confidence is increased.

Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.

Claims (12)

1. The method for checking the accuracy of the simulation model is characterized by comprising the following steps of:

constructing a simulation signal path and a test signal path, wherein the simulation signal path comprises a simulation model to be tested, the test signal path comprises a serial deserializer interface circuit corresponding to the simulation signal path, and the test signal path further comprises signal measurement equipment connected with the serial deserializer interface circuit, and setting parameters of the simulation signal path and the test signal path are the same;

assigning values for the adjustable parameters of the simulation signal path and the test signal path, and operating simulation on the simulation signal path to obtain a simulation signal waveform; running a test on the test signal path to obtain a test signal waveform;

and comparing the simulation signal waveform with the test signal waveform, and judging the accuracy of the simulation model to be tested according to the comparison result.

2. The method of claim 1, wherein the adjustable parameter comprises: main marks, front marks, and rear marks.

3. The method of claim 2, wherein the simulation signal waveforms include a fast mode signal waveform, a typical mode signal waveform, and a slow mode signal waveform, and wherein determining the accuracy of the simulation model to be tested based on the comparison result comprises:

when the test signal waveform is between the fast mode signal waveform and the slow mode signal waveform, determining that the accuracy of the simulation model to be tested is high;

and when the test signal waveform is above the fast mode signal waveform or below the slow mode signal waveform, determining that the accuracy of the simulation model to be tested is low.

4. A method according to claim 3, wherein the fast mode signal waveform corresponds to an operating condition of: fastest process, lowest temperature, highest voltage; the working conditions corresponding to the typical mode signal waveform are as follows: typical process, typical temperature, typical voltage; the working conditions corresponding to the waveform of the slow mode signal are as follows: slowest process, highest temperature, lowest voltage.

5. The method according to claim 2, wherein determining the accuracy of the simulation model to be tested according to the comparison result comprises:

calculating a quality factor FOM between the test signal waveform and the simulated signal waveform: the method comprises the steps of carrying out a first treatment on the surface of the

When the quality factor FOM is larger than or equal to a preset quality factor threshold, judging that the accuracy of the simulation model to be detected is high; and when the quality factor FOM is smaller than a preset quality factor threshold, determining that the accuracy of the simulation model to be detected is low.

6. The method of claim 5, wherein the quality factor is calculated by the formula:

wherein N is the number of sampling points, deltaX is the interval between adjacent sampling points, and X _i (sim) being the amplitude value of the simulated signal waveform; x is X _i (meas) is the amplitude value of the test signal waveform.

7. The method of claim 2, wherein the serializer-deserializer interface circuit includes a serial deserializer buffer, the setting parameters of the dummy signal path and the test signal path are the same, comprising:

the signal rate and the output code pattern of the simulation model to be tested are the same as those of the SerDes buffer;

the scattering parameters of the emulated signal path are the same as the scattering parameters of the serializer-deserializer interface circuit.

8. The method of claim 2, wherein assigning values to the adjustable parameters of the simulated signal path and the test signal path comprises:

acquiring the value range of each adjustable parameter;

according to the value range and channel loss of each adjustable parameter, setting n groups of adjustable parameter combinations to be tested, wherein n is a natural number greater than or equal to 1.

9. The method according to claim 8, characterized in that the n sets of adjustable parameter combinations to be measured comprise at least one set of limit combinations, the values of the front and/or rear marks in the limit combinations being usable limit values.

10. The method according to claim 2, wherein the method further comprises:

acquiring the value range of each adjustable parameter;

fixing the values of the main mark and the front mark, gradually taking the value of the rear mark from the minimum value to the maximum value according to a preset interval, and running simulation and test for the value of each rear mark to obtain the eye height and the eye width of the eye diagram of the receiving end corresponding to the value of each rear mark; determining the influence of the rear marks on the eye pattern according to the eye height and the eye width of the eye pattern of the receiving end corresponding to each rear mark value;

fixing the values of the main mark and the rear mark, gradually taking the values of the front mark from the minimum value to the maximum value according to preset intervals, and running simulation and test for each front mark value to obtain the eye height and the eye width of the eye pattern of the receiving end corresponding to each front mark value; and determining the influence of the front marks on the eye pattern according to the eye height and the eye width of the eye pattern of the receiving end corresponding to each front mark value.

11. The method of claim 1, wherein the emulation signal path is a signal path from the emulation model to be tested to a connector model, and the serializer-deserializer interface circuit is a signal path from a serializer-deserializer buffer to a connector.

12. An accuracy verification system for a simulation model, comprising: the device comprises a simulation signal path, a test signal path and an accuracy checking device, wherein the simulation signal path comprises a simulation model to be tested, the test signal path comprises a serial deserializer interface circuit corresponding to the simulation signal path, and the device further comprises signal measuring equipment connected with the serial deserializer interface circuit, and setting parameters of the simulation signal path and the test signal path are the same;

the accuracy checking device is configured to assign values to the adjustable parameters of the simulation signal path and the test signal path, and operate simulation on the simulation signal path to obtain a simulation signal waveform; running a test on the test signal path to obtain a test signal waveform; and comparing the simulation signal waveform with the test signal waveform, and judging the accuracy of the simulation model to be tested according to the comparison result.