CN117389942A - Fault tolerance upper bound solving method and device for interconnection network structure - Google Patents

Fault tolerance upper bound solving method and device for interconnection network structure Download PDF

Info

Publication number
CN117389942A
CN117389942A CN202311397061.1A CN202311397061A CN117389942A CN 117389942 A CN117389942 A CN 117389942A CN 202311397061 A CN202311397061 A CN 202311397061A CN 117389942 A CN117389942 A CN 117389942A
Authority
CN
China
Prior art keywords
neighbor
vertex
fdsc
upper bound
fault tolerance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202311397061.1A
Other languages
Chinese (zh)
Other versions
CN117389942B (en
Inventor
张运嵩
尤澜涛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suzhou Industrial Park Service Outsourcing Vocational College Suzhou Service Outsourcing Talent Training Center
Original Assignee
Suzhou Industrial Park Service Outsourcing Vocational College Suzhou Service Outsourcing Talent Training Center
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suzhou Industrial Park Service Outsourcing Vocational College Suzhou Service Outsourcing Talent Training Center filed Critical Suzhou Industrial Park Service Outsourcing Vocational College Suzhou Service Outsourcing Talent Training Center
Priority to CN202311397061.1A priority Critical patent/CN117389942B/en
Publication of CN117389942A publication Critical patent/CN117389942A/en
Application granted granted Critical
Publication of CN117389942B publication Critical patent/CN117389942B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/173Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356Indirect interconnection networks
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/173Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17306Intercommunication techniques
    • G06F15/17318Parallel communications techniques, e.g. gather, scatter, reduce, roadcast, multicast, all to all

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

The embodiment of the invention discloses a fault tolerance upper bound solving method and device of an interconnection network structure, and belongs to the technical field of computers. In the method, K of the exchange diagram is divided for folding 1,2 The structure constructs the upper bound of the structure connectivity on the folding partition exchange diagram, constructs a plurality of K by giving any one vertex u and surrounding the neighbor vertexes of u 1,2 Structure such that FDSC n Non-connected to obtain FDSC n K of (2) 1,2 Structural connectivity and sub-structural connectivity.

Description

Fault tolerance upper bound solving method and device for interconnection network structure
Technical Field
The embodiment of the invention relates to the technical field of computers, in particular to a fault tolerance upper bound solving method and device of an interconnection network structure.
Background
High-performance parallel computers play an increasingly important role in related fields such as scientific research, education, petroleum, weather and the like. With the increasing performance of high performance parallel computers, the number of processors (processors) it has become increasingly large. The network resulting from connecting several processors together in a particular way is called an interconnection network (Interconnection Network), one interconnection network can be represented by a simple graph g= (V (G), E (G)), where V (G) represents the vertex set of graph G and E (G) represents the edge set of graph G. The vertices in graph G represent processor nodes in the interconnection network, while the edges represent connection links between processor nodes. Folding partition exchange diagram FDSC n Is a typical interconnection network topology.
For an interconnection network, structural fault tolerance is represented by structural connectivity and sub-structural connectivity. Fabric fault tolerance may be used to measure the reliability of a network when certain fabrics in a network fail. The greater the structural fault tolerance of the network, the greater the reliability of the network when the network fails structurally.
For folding partition exchange diagram FDSC n This interconnection network topology has no upper bound solution for structural fault tolerance in the related art.
Disclosure of Invention
The embodiment of the invention provides a fault tolerance upper bound solving method and device for an interconnection network structure, which are used for solving the problem that the fault tolerance upper bound solving method for the interconnection network structure is difficult in the related art. The technical scheme is as follows:
on one hand, the embodiment of the invention provides an interconnection network structure fault tolerance upper bound solving method, which is suitable for folding partition exchange diagram FDSC n K of (2) 1,2 Fault tolerance upper bound solution of structure, folding partition exchange diagram FDSC n For representing an interconnection network, said folding partition switch diagram FDSC n Is a binary zero digit string of n bits, where n=2 d And n is greater than or equal to 4 and d is greater than or equal to 2, the method comprising:
in folding and dividing the exchange diagram FDSC n In determining all neighbor vertices u of said vertex u i And secondary neighbor u i,j The secondary neighbor u i,j For the neighbor vertex u i 1.ltoreq.i=j-1.ltoreq.d, where i is an odd number;
neighbor set { u } of vertex u i ,u j ,u i,j Composition of at least 1K 1,2 A structure, denoted as a first set, of the K 1,2 U in structure i,j =u j,i
In response to d being an even number, the neighbor set { u } of the vertex u d+1 ,u d+1,1 ,u d+1,2 Composition of 1K 1,2 A structure, denoted as a second set;
determining a union of the first set and the second set, and confirming the union as a target set;
determining that the first set is a target set in response to d being an odd number;
determining the folding partition exchange diagram FDSC according to the size of the target set n K of (2) 1,2 The upper bound of the structural connectivity and sub-structural connectivity of the structure;
using the K 1,2 The upper bound of the structural connectivity and the sub-structural connectivity of the fabric determines the structural fault tolerance of the interconnect network.
On the other hand, the embodiment of the invention provides an interconnection network structure fault tolerance upper bound solving device which is suitable for folding partition exchange diagram FDSC n K of (2) 1,2 Fault tolerance upper bound solution of structure, folding partition exchange diagram FDSC n For representing an interconnection network, said folding partition switch diagram FDSC n Is a binary zero digit string of n bits, where n=2 d And n is greater than or equal to 4 and d is greater than or equal to 2, the device comprising:
a first processing module for dividing the switch diagram FDSC in a folding manner n In determining all neighbor vertices u of said vertex u i And secondary neighbor u i,j The secondary neighbor u i,j For the neighbor vertex u i 1.ltoreq.i=j-1.ltoreq.d, where i is an odd number;
a second processing module for processing the neighbor set { u } of the vertex u i ,u j ,u i,j Composition of at least 1K 1,2 A structure, denoted as a first set, of the K 1,2 U in structure i,j =u j,i
A third processing module for responding d as even number and setting the neighbor set { u } of the vertex u d+1 ,u d+1,1 ,u d+1,2 Composition of 1K 1,2 A structure, denoted as a second set;
a fourth processing module configured to determine a union of the first set and the second set, and confirm the union as a target set;
a fifth processing module configured to determine, in response to d being an odd number, that the first set is a target set;
a sixth processing module, configured to determine, according to the size of the target set, the folding partition switch diagram FDSC n K of (2) 1,2 The upper bound of the structural connectivity and sub-structural connectivity of the structure;
a seventh processing module for using the K 1,2 The upper bound of the structural connectivity and the sub-structural connectivity of the fabric determines the structural fault tolerance of the interconnect network.
In another aspect, an embodiment of the present invention provides a terminal, where the terminal includes a processor and a memory; the memory stores at least one instruction for execution by the processor to implement the interconnection network structure fault tolerance upper bound solution method of the above aspect.
In another aspect, a computer-readable storage medium is provided that stores at least one instruction for execution by a processor to implement the interconnection network structure fault tolerance upper bound solution method of the above aspect.
In another aspect, a computer program product is provided that stores at least one instruction that is loaded and executed by a processor to implement the interconnection network structure fault tolerance upper bound solution method of the above aspect.
By adopting the method for solving the upper bound of the fault tolerance of the interconnection network structure provided by the embodiment of the invention, aiming at K of the folding partition exchange diagram 1,2 Structure, K for folding partition exchange diagram 1,2 The structure constructs the upper bound of the structure connectivity on the folding partition exchange diagram, constructs a plurality of K by giving any one vertex u and surrounding the neighbor vertexes of u 1,2 Structure such that FDSC n Non-connected to obtain FDSC n K of (2) 1,2 Structural connectivity and sub-structural connectivity.
Drawings
FIG. 1 shows a folding partition switch diagram FDSC provided by an exemplary embodiment of the invention 2 And FDSC 4 Schematic of (2);
FIG. 2 illustrates a schematic diagram of an H-structure cut shown in accordance with an exemplary embodiment of the present invention;
FIG. 3 illustrates a schematic diagram of an H-sub-structure cut shown in accordance with an exemplary embodiment of the present invention;
FIG. 4 shows K 1,m And C 4 Is a structural schematic diagram of (a);
FIG. 5 illustrates a flow chart of a fault tolerance upper bound solution method for an interconnect network structure, as shown in an exemplary embodiment of the invention;
FIG. 6 shows a schematic diagram of the structure of the neighbor vertices of the corresponding vertex u of FIG. 5;
FIG. 7 shows a construction FDSC corresponding to FIG. 5 n K of (2) 1,2 A schematic diagram of a structure cutting process;
FIG. 8 is a block diagram illustrating an interconnection network architecture fault tolerance upper bound solver according to one embodiment of the present invention;
fig. 9 is a block diagram showing the structure of a terminal according to an exemplary embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the embodiments of the present invention will be described in further detail with reference to the accompanying drawings.
References herein to "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.
The method for solving the fault tolerance upper bound of the interconnection network structure is suitable for folding partition exchange diagram FDSC n K of (2) 1,2 Fault tolerance upper bound solution of structure, folding partition exchange diagram FDSC n For representing an interconnection network.
First, background knowledge related to the folding partition exchange diagram is described as follows.
Folding partition exchange diagram FDSC n There is 2 n (n=2 d D.gtoreq.1) vertices, each of which may be represented as a binary digit string of n bits, i.e., u=s 1 s 2 …s n . Wherein s is i =0,1(1≤i≤n)。
Folding partition exchange diagram FDSC as shown in FIG. 1 2 And FDSC 4 . When n=4, 0101 and 1001 are the labels of two vertices thereof. Dividing the representation of vertex u into 3 parts, i.e. u=s 1 s 2 …s n =t 1 t 2 t 3 . Wherein t is 1 Expressed as (formula 1), t 2 Expressed as (formula 2), t 3 Expressed as (formula 3).
Note that if k=1, then t 3 Is an empty string. For FDSC n Is said to be connected to v when v satisfies one of the following conditions.
(1)Wherein (1)>At this time, (u, v) is referred to as the e (1) side.
(2)At this time, (u, v) is called the e (f) side.
(3) If t 1 =t 2 ThenIf t 1 ≠t 2 Then v=t 2 t 1 t 3 . At this time, (u, v) is called +.>Edges.
FDSC as shown in FIG. 1 4 Vertex 0000 is connected to vertex 1000, and vertex 0010 is connected to vertex 0110. We will use labels directly to denote vertices later. For any vertex u, there are d+2 vertices connected to it.
Two vertices are connected, and then the two vertices are neighbors of each other. For any vertex u, if (u, v) is an e (1) edge, then v is referred to as the 1 neighbor of u, noted v=u 1 . If (u, v) is the e (f) edge, then v is referred to as the f neighbor of u, noted v=u f . If (u, v) isEdge, then v is called the d+2-k neighbor of u, denoted v=u i (i=d+2-k). For example, in fig. 1, 1 neighbor of vertex 0010 is 1010, f neighbor is 0110,2 neighbor is 1110. Thus, 1010=0010 1 ,0110=0010 f ,1110=0010 2 . In addition, u i,j J neighbors of i neighbors representing vertex u, and so on.
Let f= { F 1 ,F 2 ,…,F t The sub-graph set of figure G is a sub-graph of G for each element in F. If V (F) is deleted such that G is not connected, then F is referred to as a subgraph cut of graph G. Let diagram H be a connected subgraph in diagram G, if each element in F is isomorphic to H, then F is called an H-structure cut. Typically, a graph has a plurality of H-cuts, the size of which is the smallest element of which is called the degree of structural connectivity, designated kappa (FDSC) n ;H)。
If each element in F is isomorphic to one connected subgraph of H, then F is called an H-substructure cut (F: an H-substructure-cut). Typically one pattern has many H-substructure cuts, these junctionsThe size of the structure segment with the least number of the constructed sub-graphs is the sub-structure connectivity and is marked as kappa s (FDSC n The method comprises the steps of carrying out a first treatment on the surface of the H) A. The invention relates to a method for producing a fibre-reinforced plastic composite By definition we have kappa (FDSC) n ;H)≥κ s (FDSC n ;H)。
The H-structure cut schematic shown in FIG. 2, with three triangle structures deleted, can make the graph non-connected. The set of these triangular structures is a structure cut.
The H-substructure shown in FIG. 3 is cut into schematic views, and the three structures are deleted to render the views non-contiguous. Since these three structures are all sub-graphs of a square structure, the set of these structures is a sub-structure.
The structural connectivity and the sub-structural connectivity are collectively referred to as structural fault tolerance. Fabric fault tolerance may be used to measure the reliability of a network when certain fabrics in a network fail. The greater the structural fault tolerance of the network, the greater the reliability of the network when the network fails structurally.
In the related art, the switch diagram FDSC is divided in a folding manner n There is no upper bound solution for structural fault tolerance. The related paper (Structure and substructure connectivity of divide-and-swap cube) discusses a partition switch diagram DSC n Upper K 1,m (2.ltoreq.m.ltoreq.d+1) and C 4 Is not shown in the drawings.
As shown in FIG. 4, K 1,m Is a claw-type structure with a central apex, C 4 Is a graph containing 4 vertices due to FDSC n Compared with DSC n Each vertex has one more edge, so that the structure of the graph is changed, and the structural fault tolerance upper bound solving method of the two is different.
Therefore, the invention provides an interconnection network structure fault tolerance upper bound solving method which is suitable for folding partition exchange diagram FDSC n K of (2) 1,2 The fault tolerance upper bound of the structure is solved, please refer to the description of the embodiments below.
Referring to FIG. 5, a flow chart of a fault tolerance upper bound solution method for an interconnection network architecture according to an exemplary embodiment of the invention is shown. The embodiment is toThe method is applied to folding and dividing the exchange diagram FDSC n K of (2) 1,2 The fault tolerance upper bound solution of the structure is illustrated, and the method comprises:
step 501, dividing the switch diagram FDSC in a folding manner n In determining all neighbor vertices u of vertex u i And secondary neighbor u i,j
Wherein, folding and dividing the exchange diagram FDSC n For representing interconnected networks, folding partition switch diagram FDSC n Is a binary zero digit string of n bits, i.e. vertex u is represented as 000..0, where the number of 0 is n, n=2 d And n is greater than or equal to 4, d is greater than or equal to 2.
Step 502, neighbor set { u } of vertex u i ,u j ,u i,j Composition of at least 1K 1,2 The structure is denoted as the first set.
For ease of representation, the first set is denoted by F1. Fig. 6 shows a schematic diagram of the structure of the neighboring vertex of the vertex u corresponding to fig. 5. Consider FDSC n Vertex u=000··0, k of (n≡4) 1,2 In the structure, 1 is less than or equal to i=j-1 is less than or equal to d, u i,j =u j,i . Thus { u ] i ,u j ,u i,j Form a K 1,2 Structure is as follows. For example, u 2 =1100,u 3 =1111,u 2,3 =u 3,2 =0011,{u 2 ,u 3 ,u 2,3 "is a K 1,2 Structure is as follows.
In one possible embodiment, for FDSC n D+2 neighbor vertices of vertex u= … 0 in (n≡4), step 502 is discussed in terms of parity cases of d.
Content one, responding d as odd number, and collecting neighbor set { u } of vertex u i ,u j ,u i,j Composition (d+1)/2K 1,2 The structure is denoted as the first set. For example d is 3, then 2K are composed 1,2 Structure is as follows.
Analytically, by { u } i ,u j ,u i,j (1. Ltoreq.i=j-1. Ltoreq.d, where i is an odd number), consisting of (d+1)/2K 1,2 The structure is put into the first set F, since d is oddI.e. the union F. Since d is an odd number, thereforeAfter F is deleted, FDSC n Will not communicate, where u is an isolated point.
Specifically, all neighbor vertices u of vertex u are obtained i The method comprises the steps of carrying out a first treatment on the surface of the Determining the j-th neighbor vertex u of the vertex u according to the connection relation j And neighbor vertex u i Is the j-th neighbor vertex u of (2) i,j The method comprises the steps of carrying out a first treatment on the surface of the According to u i 、u j And u i,j Constitute (d+1)/2K 1,2 The structure is denoted as the first set.
Content two, responding d as even number, and collecting the neighbor set { u } of the vertex u i ,u j ,u i,j Composition d/2K 1,2 The structure is denoted as the first set. For example d is 4, then 2K are composed 1,2 Structure is as follows.
Analytically, by { u } i ,u j ,u i,j The composition d/2K is } (1.ltoreq.i=j-1.ltoreq.d, where i is an odd number) 1,2 The structure is put into the first set F1, then { u } d+1 ,u d+1,1 ,u d+1,2 Composition of 1K 1,2 The structure is put into the second set F2. F1 and F2 are combined into a union F. Since d is an even number, thenAfter deleting union F, FDSC n Will not communicate, where u is an isolated point.
Specifically, all neighbor vertices u of vertex u are obtained i The method comprises the steps of carrying out a first treatment on the surface of the Determining the j-th neighbor vertex u of the vertex u according to the connection relation j And neighbor vertex u i Is the j-th neighbor vertex u of (2) i,j The method comprises the steps of carrying out a first treatment on the surface of the According to u i 、u j And u i,j Constitute d/2K 1,2 The structure is denoted as the first set.
Step 503, responding d as even number, and collecting the neighbor set { u } of the vertex u d+1 ,u d+1,1 ,u d+1,2 Composition of 1K 1,2 The structure is denoted as the second set.
In one possible implementation, all neighbor vertices u of vertex u are obtained i . From the neighbor vertex u i The (d+1) th neighbor vertex u of the obtained vertex u d+1 . Acquiring the (d+1) th neighbor vertex u d+1 Will be the (d+1) th neighbor vertex u d+1 Is marked as u d+1,1 . Acquiring the (d+1) th neighbor vertex u d+1 Will be the (d+1) th neighbor vertex u d+1 Is noted as u d+1,2 . Finally, according to u d+1 、u d+1,1 And u d+1,2 Constitute 1K 1,2 The structure is denoted as second set F2.
Step 504, determining a union of the first set and the second set, and confirming the union as a target set.
In one possible implementation, the results of the first set and the results of the second set are obtained, and the union of the first set and the second set is determined according to a union operation of the union.
In response to d being an odd number, the first set is determined to be the target set, step 505.
Combining the two cases, FDSC n K of (2) 1,2 The upper boundary of the structure connectivity and the substructure connectivity is
Is recorded asAnd->
Step 506, determining the folding partition exchange diagram FDSC according to the size of the target set n K of (2) 1,2 The upper bound of the structural connectivity and the sub-structural connectivity of the structure.
Since the value of the structural connectivity is not smaller than that of the sub-structural connectivity, the value of the structural connectivity is smaller than that of the union. According to the definition of structural connectivity, the structural connectivity is a structure that makes the graphics non-connectedMinimum of cuts. The presently constructed structure set F is one of many structure sets, which may not be the smallest, so the value of the structure connectivity must be equal to or less than |f|. The size of F is the folding partition exchange diagram FDSC n K of (2) 1,2 Is the upper bound of the structural connectivity of (c).
Step 507, using K 1,2 The upper bound of the fabric connectivity and sub-fabric connectivity of the fabric determines the fabric fault tolerance of the interconnect network.
The structural connectivity and the sub-structural connectivity are collectively referred to as structural fault tolerance. Fabric fault tolerance may be used to measure the reliability of a network when certain fabrics in a network fail. The greater the structural fault tolerance of the network, the greater the reliability of the network when the network fails structurally.
FIG. 7 shows a construction FDSC corresponding to FIG. 5 n K of (2) 1,1 The process schematic of the structure cut, in one example, the algorithm process schematic corresponding to fig. 7 is described in terms of the following program algorithm.
For K 1,2 Structural connectivity and substructural connectivity, in FDSC 4 For example, let u=0000, by calling k12_fdsc_connectivity, K can be constructed as follows 1,2 Collection of structures:
f= { {1000, 0100, 1100}, {1111, 0111,0011 }. After deleting V (F), FDSC 4 Not connected, the vertex u is an independent branch, so F is the required K 1,1 The structure is cut to a size of 2, so that FDSC can be obtained 4 K of (2) 1,2 The upper bound of the structural connectivity is 2.
The method is characterized by comprising the following steps: kappa (kappa) s (FDSC 4 ;K 1,2 )≤κ(FDSC 4 ;K 1,2 )≤2。
In summary, by adopting the method for solving the upper bound of fault tolerance of the interconnection network structure provided by the embodiment of the invention, K of the folding partition exchange diagram is aimed at 1,2 The structure constructs the upper bound of the structure connectivity on the folding partition exchange diagram, constructs a plurality of K by giving any one vertex u and surrounding the neighbor vertexes of u 1,2 Structure such that FDSC n Non-connected to obtain FDSC n K of (2) 1,2 Structural connectivity and sub-structural connectivity.
Referring now to FIG. 8, shown is a block diagram illustrating an apparatus for solving an upper bound fault tolerance of an interconnect network fabric adapted for folding partition switch fabric FDSC in accordance with one embodiment of the present invention n K of (2) 1,2 Fault tolerance upper bound solution of structure, folding partition exchange diagram FDSC n For representing an interconnection network, said folding partition switch diagram FDSC n Is a binary zero digit string of n bits, where n=2 d And n is greater than or equal to 4 and d is greater than or equal to 2, the device comprising:
a first processing module 801 for dividing the switch fabric FDSC in a folding manner n In determining all neighbor vertices u of said vertex u i And secondary neighbor u i,j The secondary neighbor u i,j For the neighbor vertex u i 1.ltoreq.i=j-1.ltoreq.d, where i is an odd number;
a second processing module 802, configured to combine the neighbor set { u } of the vertex u i ,u j ,u i,j Composition of at least 1K 1,2 A structure, denoted as a first set, of the K 1,2 U in structure i,j =u j,i
A third processing module 803, configured to respond to d being an even number, by setting the neighbor set { u } of the vertex u d+1 ,u d+1,1 ,u d+1,2 Composition of 1K 1,2 A structure, denoted as a second set;
a fourth processing module 804 configured to determine a union of the first set and the second set, and confirm the union as a target set;
a fifth processing module 805 configured to determine, in response to d being an odd number, that the first set is a target set;
a sixth processing module 806, configured to determine, according to the size of the target set, K of the folded partition switch diagram FDSCn 1,2 The upper bound of the structural connectivity and sub-structural connectivity of the structure;
a seventh processing module 807 for using the K 1,2 The upper bound of the structural connectivity and the sub-structural connectivity of the fabric determines the structural fault tolerance of the interconnect network.
Optionally, the second processing module 802 includes:
a first processing unit for responding d as odd number and setting the neighbor set { u } of the vertex u i ,u j ,u i,j Composition (d+1)/2K 1,2 A structure, denoted as the first set;
a second processing unit for responding d as even number and setting the neighbor set { u } of the vertex u i ,u j ,u i,j Composition d/2K 1,2 And (3) a structure, namely the first set.
Optionally, the first processing unit is further configured to:
acquiring all neighbor vertexes u of the vertexes u i
Determining a j-th neighbor vertex u of the vertex u according to the connection relation j And the neighbor vertex u i Is the j-th neighbor vertex u of (2) i,j
According to said u i Said u j And said u i,j Constitute (d+1)/2K 1,2 And (3) a structure, namely the first set.
Optionally, the second processing unit is further configured to:
acquiring all neighbor vertexes u of the vertexes u i
Determining a j-th neighbor vertex u of the vertex u according to the connection relation j And the neighbor vertex u i Is the j-th neighbor vertex u of (2) i,j
According to said u i Said u j And said u i,j Constitute d/2K 1,2 And (3) a structure, namely the first set.
Optionally, the third processing module 803 includes:
a third processing unit, configured to obtain all neighboring vertices u of the vertex u i
A fourth processing unit for processing the neighboring vertex u i The (d+1) th neighbor vertex u of the vertex u is obtained d+1
A fifth processing unit for acquiring the (d+1) th neighbor vertex u d+1 Is to the first neighbor vertex of the (d+1) th neighbor vertex u d+1 Is marked as u d+1,1
A sixth processing unit, configured to obtain the (d+1) -th neighbor vertex u d+1 Is to the second neighbor vertex of the (d+1) th neighbor vertex u d+1 Is noted as u d+1,2
A seventh processing unit for processing according to the u d+1 Said u d+1,1 And said u d+1,2 Constitute 1K 1,2 And (3) a structure, namely the second set.
Optionally, the fourth processing module 804 includes:
an eighth processing unit, configured to obtain a result of the first set and a result of the second set;
and the ninth processing unit is used for determining the union set of the first set and the second set according to the combination operation of the union sets.
Optionally, the value of the structural connectivity is not smaller than the value of the sub-structural connectivity, and the value of the structural connectivity is smaller than the value of the union.
Referring to fig. 9, a block diagram illustrating a structure of a terminal 900 according to an exemplary embodiment of the present invention is shown. The terminal 900 may be an electronic device in which an application program is installed and run, such as a smart phone, a tablet computer, an electronic book, a portable personal computer, etc. The terminal 900 of the present invention may include one or more of the following components: processor 910, memory 920, and screen 930.
Processor 910 may include one or more processing cores. The processor 910 connects various parts within the overall terminal 900 using various interfaces and lines, performs various functions of the terminal 900 and processes data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 920, and invoking data stored in the memory 920. Alternatively, the processor 910 may be implemented in hardware in at least one of digital signal processing (Digital Signal Processing, DSP), field programmable gate array (Field-Programmable Gate Array, FPGA), programmable logic array (Programmable Logic Array, PLA). The processor 910 may integrate one or a combination of several of a central processing unit (Central Processing Unit, CPU), an image processor (Graphics Processing Unit, GPU), and a modem, etc. The CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is responsible for rendering and drawing of the content required to be displayed by the screen 930; the modem is used to handle wireless communications. It will be appreciated that the modem may not be integrated into the processor 910 and may be implemented solely by a single communication chip.
The Memory 920 may include a random access Memory (Random Access Memory, RAM) or a Read-Only Memory (Read-Only Memory). Optionally, the memory 920 includes a non-transitory computer readable medium (non-transitory computer-readable storage medium). Memory 920 may be used to store instructions, programs, code, sets of codes, or instruction sets. The memory 920 may include a stored program area and a stored data area, where the stored program area may store instructions for implementing an operating system, which may be an Android (Android) system (including a system developed based on an Android system), an IOS system developed by apple corporation (including a system developed based on an IOS system depth), or other systems, instructions for implementing at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the above-described various method embodiments, and so on. The storage data area may also store data created by terminal 1000 in use (e.g., phonebook, audiovisual data, chat log data), and the like.
The screen 930 may be a touch display screen for receiving a touch operation of a user thereon or thereabout using a finger, a touch pen, or any other suitable object, and displaying a user interface of the respective application programs. The touch display screen is typically provided at the front panel of the terminal 900. The touch display screen may be designed as a full screen, a curved screen, or a contoured screen. The touch display screen may also be designed as a combination of a full screen and a curved screen, and the combination of a special-shaped screen and a curved screen, which is not limited in the embodiment of the present invention.
Embodiments of the present invention also provide a computer readable medium storing at least one instruction that is loaded and executed by the processor to implement the fault tolerance upper bound solution method of the interconnection network structure as described in the above embodiments.
Embodiments of the present invention also provide a computer program product storing at least one instruction that is loaded and executed by the processor to implement the fault tolerance upper bound solution method of the interconnection network structure as described in the above embodiments.
Those skilled in the art will appreciate that in one or more of the examples described above, the functions described in the embodiments of the present invention may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, these functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.
The foregoing description of the preferred embodiments of the present invention is not intended to limit the invention, but rather, the invention is to be construed as limited to the appended claims.

Claims (10)

1. An upper bound solving method for fault tolerance of an interconnection network structure, which is characterized in thatThe method is suitable for folding and dividing the exchange diagram FDSC n K of (2) 1,2 Fault tolerance upper bound solution of structure, folding partition exchange diagram FDSC n For representing an interconnection network, said folding partition switch diagram FDSC n Is a binary zero digit string of n bits, where n=2 d And n is greater than or equal to 4 and d is greater than or equal to 2, the method comprising:
in folding and dividing the exchange diagram FDSC n In determining all neighbor vertices u of said vertex u i And secondary neighbor u i,j The secondary neighbor u i,j For the neighbor vertex u i 1.ltoreq.i=j-1.ltoreq.d, where i is an odd number;
neighbor set { u } of vertex u i ,u j ,u i,j Composition of at least 1K 1,2 A structure, denoted as a first set, of the K 1,2 U in structure i,j =u j,i
In response to d being an even number, the neighbor set { u } of the vertex u d+1 ,u d+1,1 ,u d+1,2 Composition of 1K 1,2 A structure, denoted as a second set;
determining a union of the first set and the second set, and confirming the union as a target set;
determining that the first set is a target set in response to d being an odd number;
determining the folding partition exchange diagram FDSC according to the size of the target set n K of (2) 1,2 The upper bound of the structural connectivity and sub-structural connectivity of the structure;
using the K 1,2 The upper bound of the structural connectivity and the sub-structural connectivity of the fabric determines the structural fault tolerance of the interconnect network.
2. The method of claim 1, wherein the grouping of neighbors { u } of the vertex u i ,u j ,u i,j Composition of at least 1K 1,2 A structure, denoted as a first set, comprising:
in response to d being an odd number, the neighbor set { u } of the vertex u i ,u j ,u i,j Composition (d+1)/2K 1,2 A structure, denoted as the first set;
in response to d being an even number, the neighbor set { u } of the vertex u i ,u j ,u i,j Composition d/2K 1,2 And (3) a structure, namely the first set.
3. The method of claim 2, wherein the neighbor set { u } of the vertex u is determined in response to d being an odd number i ,u j ,u i,j Composition (d+1)/2K 1,2 A structure, denoted as the first set, comprising:
acquiring all neighbor vertexes u of the vertexes u i
Determining a j-th neighbor vertex u of the vertex u according to the connection relation j And the neighbor vertex u i Is the j-th neighbor vertex u of (2) i ,j
According to said u i Said u j And said u i,j Constitute (d+1)/2K 1,2 And (3) a structure, namely the first set.
4. The method of claim 2, wherein the neighbor set { u } of the vertex u is determined in response to d being an even number i ,u j ,u i,j Composition d/2K 1,2 A structure, denoted as the first set, comprising:
acquiring all neighbor vertexes u of the vertexes u i
Determining a j-th neighbor vertex u of the vertex u according to the connection relation j And the neighbor vertex u i Is the j-th neighbor vertex u of (2) i ,j
According to said u i Said u j And said u i,j Constitute d/2K 1,2 And (3) a structure, namely the first set.
5. The method of claim 1, wherein the neighbor set { u } of the vertex u is determined in response to d being an even number d+1 ,u d+1,1 ,u d+1,2 Composition of 1K 1,2 A structure, denoted as a second set, comprising:
acquiring all neighbor vertexes u of the vertexes u i
From the neighbor vertex u i The (d+1) th neighbor vertex u of the vertex u is obtained d+1
Acquiring the (d+1) th neighbor vertex u d+1 Is to the first neighbor vertex of the (d+1) th neighbor vertex u d+1 Is marked as u d+1,1
Acquiring the (d+1) th neighbor vertex u d+1 Is to the second neighbor vertex of the (d+1) th neighbor vertex u d+1 Is noted as u d+1,2
According to said u d+1 Said u d+1,1 And said u d+1,2 Constitute 1K 1,2 And (3) a structure, namely the second set.
6. The method of claim 1, wherein the determining a union of the first set and the second set, validating the union as a target set, comprises:
acquiring the results of the first set and the results of the second set;
and determining the union of the first set and the second set according to the combination operation of the union.
7. The method of any one of claims 1 to 6, wherein the value of the structural connectivity is not less than the value of the sub-structural connectivity, which is less than the value of the union.
8. An interconnection network structure fault tolerance upper bound solving device, which is characterized in that the device is suitable for folding partition exchange diagram FDSC n K of (2) 1,2 Fault tolerance upper bound solution of structure, folding partition exchange diagram FDSC n For representing an interconnection network, said folding partition switch diagram FDSC n Is a binary zero digit string of n bits, where n=2 d And n is greater than or equal to 4, d is greater than or equal to 2, the deviceComprising the following steps:
a first processing module for dividing the switch diagram FDSC in a folding manner n In determining all neighbor vertices u of said vertex u i And secondary neighbor u i,j The secondary neighbor u i,j For the neighbor vertex u i 1.ltoreq.i=j-1.ltoreq.d, where i is an odd number;
a second processing module for processing the neighbor set { u } of the vertex u i ,u j ,u i,j Composition of at least 1K 1,2 A structure, denoted as a first set, of the K 1,2 U in structure i,j =u j,i
A third processing module for responding d as even number and setting the neighbor set { u } of the vertex u d+1 ,u d+1,1 ,u d+1,2 Composition of 1K 1,2 A structure, denoted as a second set;
a fourth processing module configured to determine a union of the first set and the second set, and confirm the union as a target set;
a fifth processing module configured to determine, in response to d being an odd number, that the first set is a target set;
a sixth processing module, configured to determine, according to the size of the target set, the folding partition switch diagram FDSC n K of (2) 1,2 The upper bound of the structural connectivity and sub-structural connectivity of the structure;
a seventh processing module for using the K 1,2 The upper bound of the structural connectivity and the sub-structural connectivity of the fabric determines the structural fault tolerance of the interconnect network.
9. A terminal, the terminal comprising a processor and a memory; the memory stores at least one instruction for execution by the processor to implement the interconnection network structure fault tolerance upper bound solution method of any one of claims 1 to 7.
10. A computer readable storage medium having stored thereon at least one instruction for execution by a processor to implement the fault tolerance upper bound solution method of the interconnection network structure of any of claims 1 to 7.
CN202311397061.1A 2023-10-26 2023-10-26 Fault tolerance upper bound solving method and device for interconnection network structure Active CN117389942B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311397061.1A CN117389942B (en) 2023-10-26 2023-10-26 Fault tolerance upper bound solving method and device for interconnection network structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311397061.1A CN117389942B (en) 2023-10-26 2023-10-26 Fault tolerance upper bound solving method and device for interconnection network structure

Publications (2)

Publication Number Publication Date
CN117389942A true CN117389942A (en) 2024-01-12
CN117389942B CN117389942B (en) 2024-06-11

Family

ID=89438759

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311397061.1A Active CN117389942B (en) 2023-10-26 2023-10-26 Fault tolerance upper bound solving method and device for interconnection network structure

Country Status (1)

Country Link
CN (1) CN117389942B (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103164291A (en) * 2011-12-12 2013-06-19 天津工业大学 Method for solving fault-tolerant upper bound of reconfigurable multiprocessor array
US20130326038A1 (en) * 2012-06-05 2013-12-05 Microsoft Corporation Management of datacenters for fault tolerance and bandwidth
CN111245655A (en) * 2020-01-10 2020-06-05 长春理工大学 Intra-network topology structure, construction method and system
CN114826931A (en) * 2022-04-24 2022-07-29 苏州工业园区服务外包职业学院 Method, device, equipment and storage medium for determining fault tolerance of alternate group network structure
US11611485B1 (en) * 2022-03-03 2023-03-21 Eci Telecom Ltd. Shared risk link group-disjoint routing in data communication networks
CN116257485A (en) * 2023-03-06 2023-06-13 苏州工业园区服务外包职业学院(苏州市服务外包人才培养实训中心) Hamiltonian path construction method of multiprocessor interconnection network

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103164291A (en) * 2011-12-12 2013-06-19 天津工业大学 Method for solving fault-tolerant upper bound of reconfigurable multiprocessor array
US20130326038A1 (en) * 2012-06-05 2013-12-05 Microsoft Corporation Management of datacenters for fault tolerance and bandwidth
CN111245655A (en) * 2020-01-10 2020-06-05 长春理工大学 Intra-network topology structure, construction method and system
US11611485B1 (en) * 2022-03-03 2023-03-21 Eci Telecom Ltd. Shared risk link group-disjoint routing in data communication networks
CN114826931A (en) * 2022-04-24 2022-07-29 苏州工业园区服务外包职业学院 Method, device, equipment and storage medium for determining fault tolerance of alternate group network structure
CN116257485A (en) * 2023-03-06 2023-06-13 苏州工业园区服务外包职业学院(苏州市服务外包人才培养实训中心) Hamiltonian path construction method of multiprocessor interconnection network

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
YOU LANTAO等: "Structure Connectivity and Substructure Connectivity of Alternating Group Graphs", 《 PROCEEDINGS OF THE 2018 IEEE INTERNATIONAL CONFERENCE ON PROGRESS IN INFORMATICS AND COMPUTING》, 31 December 2018 (2018-12-31), pages 317 - 321, XP033545145, DOI: 10.1109/PIC.2018.8706296 *
尤澜涛: "几种互连网络上图嵌入的研究", 《中国博士学位论文全文数据库信息科技辑(月刊)》, no. 06, 15 June 2016 (2016-06-15), pages 137 - 2 *

Also Published As

Publication number Publication date
CN117389942B (en) 2024-06-11

Similar Documents

Publication Publication Date Title
CN105549936B (en) Data table display method and device
CN114741217B (en) Method, device, equipment and storage medium for determining fault tolerance of network structure
CN111353591A (en) Computing device and related product
CN111753094A (en) Method and device for constructing event knowledge graph and method and device for determining event
CN108885683B (en) Method and system for pose estimation
CN114826931B (en) Method, device, equipment and storage medium for determining fault tolerance of alternate group network structure
US11037356B2 (en) System and method for executing non-graphical algorithms on a GPU (graphics processing unit)
CN103699652A (en) Webpage access method and webpage access system
CN113987152B (en) Knowledge graph extraction method, system, electronic equipment and medium
CN110297764A (en) Loophole test model training method and device
CN117389941B (en) Fault tolerance upper bound solving method and device for interconnection network structure
CN117389942B (en) Fault tolerance upper bound solving method and device for interconnection network structure
CN113761293A (en) Graph data strong-connectivity component mining method, device, equipment and storage medium
CN115795203B (en) Method and device for constructing menu page, electronic equipment and storage medium
CN105700704A (en) Method and device for inputting characters to mini-size screen
CN111885614B (en) CORS base station networking method, device and storage medium
CN107329654A (en) Draw method, device and the computer-readable recording medium of element floating layer
CN105279157B (en) A kind of method and apparatus of canonical inquiry
CN113642054A (en) CAD drawing data processing method, device and storage medium
CN113657408A (en) Method and device for determining image characteristics, electronic equipment and storage medium
CN110704561A (en) Map edge pasting method, terminal device and storage medium
CN114692808A (en) Method and system for determining graph neural network propagation model
CN111125715A (en) TCG data processing acceleration method and device based on solid state disk, computer equipment and storage medium
CN113392673A (en) Image correction method, device, equipment and computer readable storage medium
CN110215705A (en) The display methods of information, device, terminal and storage medium in game

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant