CN117389183A - Chained power source control method and system based on determined time slot - Google Patents

Abstract

The invention discloses a chain power source control system based on determined time slots, which includes a main FPGA. The main FPGA includes Ethernet A and Ethernet B. Each power source includes Ethernet A and Ethernet B. The power source Ethernet B is connected to Ethernet A of the next-level power source through optical fiber, thereby realizing the serial connection of each power source. Ethernet A of the head-end power source is connected to Ethernet A of the main FPGA through optical fiber, and the Ethernet A of the tail-end power source is connected through optical fiber. Ethernet B and the Ethernet B of the main FPGA are connected through optical fibers. The invention also discloses a chain power source control system based on determined time slots. The sampling number data sequence of the present invention adopts bidirectional loop propagation, which improves the reliability of sampling number data sequence propagation and power source control. It also has loop disconnection alarm reminder, power source out-of-loop reminder, and power source failure reminder.

Description

A chain power source control method and system based on determined time slots

Technical field

The invention relates to the technical field of electric power analog power sources, specifically to a chain power source control system based on a determined time slot, and also relates to a chain power source control method based on a determined time slot.

Background technique

In power system relay protection testing, analog power equipment is often used. A single analog power source cannot meet the entire interval or entire station test, and multiple power source equipment is required. Generally, conventional analog power sources use analog small signal input or use a single Ethernet interface to connect. When multiple analog power sources need to be connected to the system, the conventional analog small signal or single Ethernet method cannot meet the test needs.

Contents of the invention

The purpose of the present invention is to provide a chain power source control system based on determined time slots and a chain power source control method based on determined time slots in order to solve the above-mentioned problems existing in the prior art.

A chain power source control system based on determined time slots, including a main FPGA. The main FPGA includes Ethernet A and Ethernet B. Each power source includes Ethernet A and Ethernet B. The Ethernet B and Ethernet B of the power source are The Ethernet A of the next-level power source is connected through optical fiber, and each power source is connected in series. The Ethernet A of the head-end power source is connected to the Ethernet A of the main FPGA through optical fiber. The Ethernet B of the tail-end power source is connected to the Ethernet B of the main FPGA. Ethernet B is connected via optical fiber,

The power source includes a sub-FPGA, a digital-to-analog conversion module, and a power amplification module. The sub-FPGA includes Ethernet A and Ethernet B. The sub-FPGA is connected to the digital-to-analog conversion module, and the digital-to-analog conversion module is connected to the power amplification module.

The main FPGA generates a sampling number data sequence. The sampling number data sequence includes a time synchronization frame and multiple power source data frames. The power source data frame corresponds to the power source one-to-one;

The main FPGA sends the sampling sequence number data sequence from Ethernet A and Ethernet B respectively. The sampling sequence number data sequence sent from the Ethernet A of the main FPGA passes through each sub-connector in sequence according to the forward loop propagation direction from the first terminal FPGA to the last terminal FPGA. FPGA, and receives it from the Ethernet B of the main FPGA; the sampling sequence number data sequence sent from the Ethernet B of the main FPGA passes through each sub-FPGA in sequence according to the reverse loop propagation direction from the tail terminal FPGA to the first terminal FPGA, and is transmitted from the main FPGA Ethernet A receive;

For the same sampling number data sequence in different loop propagation directions, the sub-FPGA selects the first arriving sampling number data sequence, analyzes the time synchronization frame and power source data frame in the sampling number data sequence, and updates the sub-FPGA system based on the time synchronization frame. time, and output the corresponding voltage and current according to the power source data frame;

Based on the received sampling sequence number data sequence, the main PFGA determines whether the loop propagation direction is disconnected, whether the power source is in the loop, and whether the power source is faulty.

As mentioned above, the time synchronization frame includes frame separator, destination address, source address, frame type, time synchronization field, and frame check;

The time synchronization field includes the main clock time, single-stage path delay, accumulated delay of this stage, sampling rate, and sampling sequence number;

The single-stage path delay is the path delay from the main FPGA to the next sub-FPGA or the multi-path delay between two adjacent sub-FPGAs;

The cumulative delay of this level. The sub-FPGA adds the cumulative delay of this level in the received time synchronization frame plus the single-level path delay plus the forwarding delay of this level to obtain the corrected cumulative delay of this level and then writes it to the time The cumulative delay of this level in the synchronization frame. The forwarding delay of this level is the time from when the Ethernet A of the sub-FPGA of this level receives the data to the time when it is forwarded to Ethernet B of the sub-FPGA of this level.

The power source data frame includes frame separator, destination address, source address, frame type, power source data field, and frame check;

The power source data field includes frame number, control word, voltage data, and current data;

The control word contains the in-loop information and alarm information of the corresponding power source. The initial values of the in-loop information and alarm information in the control word are both 0.

As mentioned above, after the sub-FPGA receives the first arriving sampling sequence number data sequence from one of its own Ethernets, it parses the time synchronization frame and power source data frame in the sampling sequence number data sequence.

If the sub-FPGA finds the corresponding power source data frame in the sampling sequence number data sequence, it controls the output of the digital-to-analog conversion module according to the voltage data and current data of each channel of the power source data frame corresponding to the sub-FPGA, and performs power amplification through the power amplifier. Set the in-loop information in the control word corresponding to the power source data frame to 1; when there is an alarm in the power source, set the alarm information corresponding to the power source data frame to 1;

After the sub-FPGA parses the time synchronization frame, it obtains the main clock time, single-stage path delay, and accumulated delay of this level, and updates the sub-FPGA based on the sum of the main clock time, single-stage path delay, and accumulated delay of this level. system time;

The sub-FPGA forwards the updated sampling sequence number data sequence to the next sub-FPGA or main PFGA along the ring propagation direction through its own other Ethernet.

As mentioned above, after the sub-FPGA receives the sample sequence number data sequence from one of its own Ethernet networks:

After the sub-FPGA receives the incoming sampling sequence number data sequence from one of its own Ethernet networks, it updates the in-loop information and alarm information in the control word in the power source data frame, and updates the cumulative delay of the current level in the time synchronization frame. The FPGA forwards the updated sampling sequence number data sequence to the next sub-FPGA or main PFGA along the ring propagation direction through its own other Ethernet.

If the main FPGA does not receive two time synchronization frames in the sampling sequence number data sequence of the same sampling sequence number, otherwise it will consider that one of the loop propagation directions is disconnected, and a loop disconnection alarm will be issued;

The main FPGA analyzes the in-loop information and alarm information in the control word in the power source data frame. If the in-loop information in the power source data frame is 0, it is determined that the corresponding power source is not in the loop. If the alarm in the power source data frame If the information is 1, it is determined that the corresponding power source is faulty. If it is determined that the power source is not in the loop or the power source is faulty, the voltage data and current data in the corresponding power source data frame are 0.

A chain power source control method based on determined time slots, including the following steps:

Step 1. The main FPGA generates a sampling number data sequence. The sampling number data sequence includes a time synchronization frame and multiple power source data frames. The power source data frame corresponds to the power source one-to-one;

Step 2. The main FPGA sends the sampling sequence number data sequence from Ethernet A and Ethernet B respectively. The sampling sequence number data sequence sent from Ethernet A of the main FPGA follows the forward loop propagation direction from the first terminal FPGA to the last terminal FPGA. After passing through each sub-FPGA, it is received from the Ethernet B of the main FPGA; the sampling sequence number data sequence sent from the Ethernet B of the main FPGA passes through each sub-FPGA in sequence according to the reverse loop propagation direction from the tail terminal FPGA to the first terminal FPGA, and is received from the Ethernet B of the main FPGA. Ethernet A reception of the main FPGA;

Step 3. For the same sampling number data sequence in different loop propagation directions, the sub-FPGA selects the first arriving sampling number data sequence, analyzes the time synchronization frame and power source data frame in the sampling number data sequence, and updates the sub-FPGA according to the time synchronization frame. The system time of FPGA outputs the corresponding voltage and current according to the power source data frame;

Step 4. Based on the received sampling number data sequence, the main PFGA determines whether the loop propagation direction is disconnected, whether the power source is in the loop, and whether the power source is faulty.

As mentioned above in step 1,

The time synchronization frame includes frame separator, destination address, source address, frame type, time synchronization field, and frame check;

The time synchronization field includes the main clock time, single-stage path delay, accumulated delay of this stage, sampling rate, and sampling sequence number;

The single-stage path delay is the path delay from the main FPGA to the next sub-FPGA or the multi-path delay between two adjacent sub-FPGAs;

The cumulative delay of this level. The sub-FPGA adds the cumulative delay of this level in the received time synchronization frame plus the single-level path delay plus the forwarding delay of this level to obtain the corrected cumulative delay of this level and then writes it to the time The cumulative delay of this level in the synchronization frame. The forwarding delay of this level is the time from when the Ethernet A of the sub-FPGA of this level receives the data to the time when it is forwarded to Ethernet B of the sub-FPGA of this level.

The power source data frame includes frame separator, destination address, source address, frame type, power source data field, and frame check;

The power source data field includes frame number, control word, voltage data, and current data;

The control word contains the in-loop information and alarm information of the corresponding power source. The initial values of the in-loop information and alarm information in the control word are both 0.

As mentioned above in step 3, for the first arriving sampling number data sequence:

After the sub-FPGA receives the first arriving sampling number data sequence from one of its own Ethernets, it parses the time synchronization frame and power source data frame in the sampling number data sequence.

If the sub-FPGA finds the corresponding power source data frame in the sampling sequence number data sequence, it controls the output of the digital-to-analog conversion module according to the voltage data and current data of each channel of the power source data frame corresponding to the sub-FPGA, and performs power amplification through the power amplifier. Set the in-loop information in the control word corresponding to the power source data frame to 1; when there is an alarm in the power source, set the alarm information corresponding to the power source data frame to 1;

After the sub-FPGA parses the time synchronization frame, it obtains the main clock time, single-stage path delay, and accumulated delay of this level, and updates the sub-FPGA based on the sum of the main clock time, single-stage path delay, and accumulated delay of this level. system time;

The sub-FPGA forwards the updated sampling sequence number data sequence to the next sub-FPGA or main PFGA along the ring propagation direction through its own other Ethernet.

As mentioned above in step 3, for the later sampling number data sequence:

After the sub-FPGA receives the incoming sampling sequence number data sequence from one of its own Ethernet networks, it updates the in-loop information and alarm information in the control word in the power source data frame, and updates the cumulative delay of the current level in the time synchronization frame. The FPGA forwards the updated sampling sequence number data sequence to the next sub-FPGA or main PFGA along the ring propagation direction through its own other Ethernet.

As above in step 4:

If the main FPGA does not receive two time synchronization frames in the sampling sequence number data sequence of the same sampling sequence number, otherwise it will consider that one of the loop propagation directions is disconnected, and a loop disconnection alarm will be issued;

The main FPGA analyzes the in-loop information and alarm information in the control word in the power source data frame. If the in-loop information in the power source data frame is 0, it is determined that the corresponding power source is not in the loop. If the alarm in the power source data frame If the information is 1, it is determined that the corresponding power source is faulty. If it is determined that the power source is not in the loop or the power source is faulty, the voltage data and current data in the corresponding power source data frame are 0.

Compared with the existing technology, the present invention has the following beneficial effects:

1. The optical Ethernet digital input method is more stable, anti-interference and easier to wire than the analog small signal method;

2. The chain connection method can save the need for multiple optical Ethernet ports on the main control device and reduce the number of hardware interfaces;

3. The chain connection method is adopted and based on two-way redundant communication, which can significantly enhance the stability of the network.

Description of the drawings

Figure 1 is a schematic structural diagram of a chain power source control system based on determined time slots;

Figure 2 is a schematic diagram of the sampling sequence number data sequence;

Figure 3 is a schematic diagram of the frame structure of the time synchronization frame and the power source data frame.

Detailed ways

In order to facilitate those of ordinary skill in the art to understand and implement the present invention, the present invention will be further described in detail below in conjunction with examples. It should be understood that the implementation examples described here are only used to illustrate and explain the present invention and are not intended to limit the present invention.

A chain power source control system based on determined time slots, including a main FPGA and multiple power sources. The main FPGA includes Ethernet A and Ethernet B. Each power source includes Ethernet A and Ethernet B. The power source The Ethernet B of the next-level power source is connected to the Ethernet A of the next-level power source through optical fiber, thereby realizing the serial connection of each power source. The Ethernet A of the head-end power source is connected to the Ethernet A of the main FPGA through optical fiber. The power source of the tail-end The Ethernet B and the main FPGA's Ethernet B are connected via optical fiber.

The power source includes a sub-FPGA, a digital-to-analog conversion module, and a power amplification module. The sub-FPGA includes Ethernet A and Ethernet B. The sub-FPGA is connected to the digital-to-analog conversion module, and the digital-to-analog conversion module is connected to the power amplification module.

A chain power source control method based on determined time slots, using the above-mentioned chain power source control system based on determined time slots, including the following steps:

Step 1. The main FPGA generates a sampling number data sequence. The sampling number data sequence includes a time synchronization frame TimeSync and multiple power source data frames. The power source data frame corresponds to the power source one-to-one;

Time synchronization frame TimeSync includes frame separator SDF (8 bytes), destination address DA (1 byte), source address SA (1 byte), frame type FrameType (1 byte), and time synchronization field (41 bytes) , and frame check FCS (4 bytes), a total of 56 bytes;

The time synchronization field includes the master clock time MasterTime, single-stage path delay TDelay, current-level cumulative delay FDelay, sampling rate SampleRate, and sampling sequence number SampleNum;

The master clock time MasterTime is the time information of the main FPGA, incremented by 1 every 10ns, and is the time base of the entire system. The time interval between two adjacent sampling points is 250us;

Single-stage path delay TDelay, single-stage path delay TDelay is the path delay from the main FPGA to the next sub-FPGA or the multi-path delay between two adjacent sub-FPGAs, including possible physical layer PHY, optical modules, optical fibers, etc. The delay of the equipment, usually the delay of each stage of the circuit module can be considered the same;

The accumulated delay FDelay of this level is filled in with 0 on the main FPGA side, and is calculated and written by each subsequent sub-FPGA. The correction method of the accumulated delay FDelay of this level is to add the accumulated delay FDelay of this level in the received time synchronization frame. The upper single-level path delay TDelay is added to the current-level forwarding delay. The corrected current-level cumulative delay FDelay is then written to the current-level cumulative delay FDelay in the time synchronization frame TimeSync. The forwarding delay at this level is the time from when Ethernet A of the sub-FPGA at this level receives data to when it is forwarded to Ethernet B of sub-FPGA at this level.

The sampling rate SampleRate is 4000hz. The Ethernet A of the main FPGA divides the Gigabit Ethernet line speed 1000Mbs into 4000 intervals according to the sampling rate 4000hz, that is, the length of each interval is 250us, and the number of data bytes that can be sent is 125000000/4000, that is 31250 bytes; further, in order to better control the sending time and bandwidth utilization, each 250us is divided into 255 precise time slots, that is, the number of bytes that can be sent in each precise time slot is 122 bytes. In each 250us interval, the sampling sequence number data sequence is sent as shown in Figure 2.

The sampling serial number SampleNum is the serial number of the sampling serial number data sequence. The sampling rate SampleRate is generally set to 4000hz, and the sampling number SampleNum increases sequentially from 0 to 3999.

The power source data frame includes frame separator SDF (8 bytes), destination address DA (1 byte), source address SA (1 byte), frame type FrameType (1 byte), and power source data field (41 bytes). ), and frame check FCS (4 bytes), a total of 56 bytes;

The power source data field includes frame number FrameNum, control word ctrlword, voltage data, and current data.

The control word ctrlword contains the in-loop information and alarm information of the corresponding power source. The initial values of the in-loop information and alarm information in the control word ctrlword are both 0.

The voltage data is the output voltage value of each voltage channel of the corresponding power source,

The current data is the output current value of each current channel of the corresponding power source.

Each power source has its own independent address. The address of the main FPGA is 0x00, the address of power source 1 is 0x01, and so on. 0xff is the broadcast address. The destination address DA in the time synchronization frame TimeSync is the broadcast address. The destination address of the power source data frame is the address of the corresponding power source (that is, the address of the sub-FPGA).

Step 2. The main FPGA sends the sampling sequence number data sequence from Ethernet A and Ethernet B respectively. The sampling sequence number data sequence sent from Ethernet A of the main FPGA follows the forward loop propagation direction from the first terminal FPGA to the last terminal FPGA. After passing through each sub-FPGA, it is received from the Ethernet B of the main FPGA; the sampling sequence number data sequence sent from the Ethernet B of the main FPGA passes through each sub-FPGA in sequence according to the reverse loop propagation direction from the tail terminal FPGA to the first terminal FPGA, and is received from the Ethernet B of the main FPGA. Ethernet A reception of the main FPGA;

Step 3. Under normal circumstances, the sub-FPGA receives two copies of the sampling sequence number data sequence with the same sampling sequence number, and performs loop transmission in clockwise and counterclockwise directions. The sub-FPGA receives the same sampling sequence number data sequence in different loop propagation directions. Adopting the first come first served principle,

For the first arriving sample sequence number data sequence:

After the sub-FPGA receives the first arriving sampling number data sequence from one of its own Ethernets, it parses the time synchronization frame TimeSync and power source data frame PA Data in the sampling number data sequence.

If the sub-FPGA finds the corresponding power source data frame PA Data in the sampling sequence number data sequence, that is, the destination address DA in the power source data frame PA Data corresponding to the sub-FPGA is the same as the address of the sub-FPGA, according to the power source data frame corresponding to the sub-FPGA The voltage data and current data of each channel of PA Data control the DA output of the digital-to-analog conversion module, and after PA power amplification, the in-loop information in the control word ctrlword corresponding to the power source data frame is set to 1; when there is For any alarm, including over-temperature, short circuit, open circuit and other alarm information, set the alarm information corresponding to the power source data frame to 1.

After the sub-FPGA parses the time synchronization frame TimeSync, it obtains the main clock time MasterTime, single-stage path delay TDelay, and current-level cumulative delay FDelay. It updates the system time of the sub-FPGA based on MasterTimer+TDelay+FDelay, which is the internal system of the sub-FPGA. Time is synchronized to the time of the entire system;

The sub-FPGA further analyzes the sampling rate SampleRate in the time synchronization frame TimeSync, and determines the accurate power source data frame PA Data based on the system time and sampling rate SampleRate inside the sub-FPGA and outputs it to the digital-to-analog conversion module DA;

The sub-FPGA forwards the updated sampling sequence number data sequence to the next sub-FPGA or main PFGA along the loop propagation direction (forward loop propagation direction or reverse loop propagation direction) through another Ethernet of itself;

For the later arriving sample sequence number data sequence:

After the sub-FPGA receives the subsequent sampling number data sequence from one of its own Ethernet networks, it only updates the in-loop information and alarm information in the control word ctrlword in the power source data frame PA Data, and updates the current level in the time synchronization frame TimeSync. Accumulated delay FDelay, the sub-FPGA forwards the updated sampling sequence number data sequence to the next sub-FPGA or main PFGA through its other Ethernet along the loop propagation direction (forward loop propagation direction or reverse loop propagation direction);

Step 4. The main PFGA receives the sampling number data sequence and parses the time synchronization frame TimeSync and the power source data frame PA Data.

The main FPGA should receive the time synchronization frame TimeSync in the data sequence of two sampling numbers with the same sampling number SampleNum. Otherwise, it will be considered that a certain loop propagation direction of the link is disconnected, and a loop disconnection alarm will be issued;

The main FPGA analyzes the in-loop information and alarm information in the control word ctrlword in the power source data frame. If the in-loop information in the power source data frame is 0, it is determined that the corresponding power source is not in the loop. If the in-loop information in the power source data frame is If the alarm information is 1, it is determined that the corresponding power source is faulty, and the corresponding power source register table is updated to determine whether the corresponding power source is online and whether there are abnormal alarms such as over-temperature, short circuit, and open circuit;

The main FPGA decides whether to continue to output the data of the corresponding power source based on the in-loop information and alarm information in the corresponding control subctrlword. If it is determined that the power source is not in the loop or the power source is faulty, the voltage data in the corresponding power source data frame and The current data is 0, that is, the corresponding power source does not output voltage and current.

It should be noted that the specific embodiments described in the present invention are only illustrative of the spirit of the present invention. Those skilled in the technical field to which the present invention belongs can make various modifications or additions to the described specific embodiments or substitute them in similar ways, but this will not deviate from the spirit of the present invention or exceed the definition of the appended claims. range.

Claims (10)

1. The chain type power source control system based on the determined time slot comprises a main FPGA, and is characterized in that the main FPGA comprises an Ethernet A and an Ethernet B, each power source comprises the Ethernet A and the Ethernet B, the Ethernet B of the power source is connected with the Ethernet A of the next-stage power source through an optical fiber, each power source is connected in series, the Ethernet A of the power source at the head end is connected with the Ethernet A of the main FPGA through an optical fiber, the Ethernet B of the power source at the tail end is connected with the Ethernet B of the main FPGA through an optical fiber,

the power source comprises a sub-FPGA, a digital-to-analog conversion module and a power amplification module, wherein the sub-FPGA comprises an Ethernet A and an Ethernet B, the sub-FPGA is connected with the digital-to-analog conversion module, the digital-to-analog conversion module is connected with the power amplification module,

the method comprises the steps that a main FPGA generates a sampling sequence number data sequence, wherein the sampling sequence number data sequence sequentially comprises a time synchronization frame and a plurality of power source data frames, and the power source data frames correspond to power sources one by one;

the main FPGA sends out a sampling sequence number data sequence from the Ethernet A and the Ethernet B respectively, and the sampling sequence number data sequence sent out from the Ethernet A of the main FPGA sequentially passes through each sub-FPGA according to the forward loop propagation direction from the head terminal FPGA to the tail sub-FPGA and is received from the Ethernet B of the main FPGA; the sampling sequence number data sequence sent from the Ethernet B of the main FPGA sequentially passes through each sub-FPGA according to the reverse loop propagation direction from the tail sub-FPGA to the head sub-FPGA and is received from the Ethernet A of the main FPGA;

for the same sampling sequence number data sequence in different loop propagation directions, the sub-FPGA selects the first sampling sequence number data sequence, analyzes a time synchronization frame and a power source data frame in the sampling sequence number data sequence, updates the system time of the sub-FPGA according to the time synchronization frame, and outputs corresponding voltage and current according to the power source data frame;

the main PFGA judges whether the loop propagation direction is disconnected, whether the power source is in the loop or not and whether the power source fails or not according to the received sampling sequence number data sequence.

2. The system of claim 1, wherein the time synchronization frame comprises a frame spacer, a destination address, a source address, a frame type, a time synchronization field, and a frame check;

the time synchronization field comprises a master clock time, single-stage path delay, current-stage accumulated delay, sampling rate and sampling sequence number;

the single-stage path delay is the path delay from the main FPGA to the next sub-FPGA or the multipath delay between two adjacent sub-FPGAs;

the sub-FPGA adds the current-level accumulated time delay in the received time synchronous frame with the single-stage path time delay and the current-level forwarding time delay to obtain the corrected current-level accumulated time delay which is written into the current-level accumulated time delay in the time synchronous frame, the current-level forwarding time delay is the time from the start of receiving data by the Ethernet A of the current-level sub-FPGA to the start of forwarding the data to the Ethernet B of the current-level sub-FPGA,

the power source data frame comprises a frame spacer, a destination address, a source address, a frame type, a power source data field, and a frame check;

the power source data field comprises a frame number, a control word, voltage data and current data;

the control word contains the corresponding power source in-loop information and alarm information, and the initial values of the in-loop information and the alarm information in the control word are all 0.

3. The system of claim 2, wherein the sub-FPGA parses the time sync frame and the power source data frame in the sequence of sample sequence numbers after receiving the first sequence of sample sequence numbers from one of its own ethernets,

if the sub-FPGA finds a corresponding power source data frame in the sampling sequence number data sequence, controlling the output of the digital-to-analog conversion module according to the voltage data and the current data of each channel of the power source data frame corresponding to the sub-FPGA, performing power amplification through the power amplifier, and setting the ring information in the control word corresponding to the power source data frame to be 1; when an alarm exists in the power source, setting the alarm information corresponding to the power source data frame to be 1;

after the sub-FPGA analyzes the time synchronization frame, acquiring main clock time, single-stage path delay and current-stage accumulated delay, and updating the system time of the sub-FPGA according to the total of the main clock time, the single-stage path delay and the current-stage accumulated delay;

the sub-FPGA forwards the updated sampling sequence number data sequence to the next sub-FPGA or the main PFGA along the loop propagation direction through another Ethernet.

4. A chained power source control system based on a determined time slot as claimed in claim 3, wherein said sub-FPGA receives a sequence of sample sequence numbers from one of its own ethernet networks:

after receiving the sampling serial number data sequence from one of the Ethernet networks, the sub-FPGA updates the ring information and the alarm information in the control word in the power source data frame, updates the current-stage accumulated time delay in the time synchronization frame, and forwards the updated sampling serial number data sequence to the next sub-FPGA or the main PFGA along the loop propagation direction through the other Ethernet network.

5. The system of claim 4, wherein if the main FPGA does not receive the time synchronization frame in the sequence of two sampling sequence numbers with the same sampling sequence number, it considers that one of the loop propagation directions is disconnected, and performs a loop disconnection alarm reminding;

the main FPGA analyzes the ring information and the alarm information in the control word in the power source data frame, if the ring information in the power source data frame is 0, the corresponding power source is judged not to be in the ring, if the alarm information in the power source data frame is 1, the corresponding power source is judged to be in fault, and if the power source is judged not to be in the ring or the power source is in fault, the voltage data and the current data in the corresponding power source data frame are 0.

6. The chain type power source control method based on the determined time slot is characterized by comprising the following steps:

step 1, a main FPGA generates a sampling sequence number data sequence, wherein the sampling sequence number data sequence sequentially comprises a time synchronization frame and a plurality of power source data frames, and the power source data frames correspond to power sources one by one;

step 2, the main FPGA sends out a sampling sequence number data sequence from the Ethernet A and the Ethernet B respectively, and the sampling sequence number data sequence sent out from the Ethernet A of the main FPGA sequentially passes through all the sub-FPGAs according to the forward loop propagation direction from the head terminal FPGA to the tail sub-FPGA and is received from the Ethernet B of the main FPGA; the sampling sequence number data sequence sent from the Ethernet B of the main FPGA sequentially passes through each sub-FPGA according to the reverse loop propagation direction from the tail sub-FPGA to the head sub-FPGA and is received from the Ethernet A of the main FPGA;

step 3, for the same sampling sequence number data sequence in different loop propagation directions, the sub-FPGA selects the first sampling sequence number data sequence, analyzes a time synchronization frame and a power source data frame in the sampling sequence number data sequence, updates the system time of the sub-FPGA according to the time synchronization frame, and outputs corresponding voltage and current according to the power source data frame;

and 4, the main PFGA judges whether the loop propagation direction is disconnected, whether the power source is in the loop or not and whether the power source fails or not according to the received sampling sequence number data sequence.

7. The method of claim 6, wherein in the step 1,

the time synchronization frame comprises a frame spacer, a destination address, a source address, a frame type, a time synchronization field, and a frame check;

the time synchronization field comprises a master clock time, single-stage path delay, current-stage accumulated delay, sampling rate and sampling sequence number;

the single-stage path delay is the path delay from the main FPGA to the next sub-FPGA or the multipath delay between two adjacent sub-FPGAs;

the sub-FPGA adds the current-level accumulated time delay in the received time synchronous frame with the single-stage path time delay and the current-level forwarding time delay to obtain the corrected current-level accumulated time delay which is written into the current-level accumulated time delay in the time synchronous frame, the current-level forwarding time delay is the time from the start of receiving data by the Ethernet A of the current-level sub-FPGA to the start of forwarding the data to the Ethernet B of the current-level sub-FPGA,

the power source data frame comprises a frame spacer, a destination address, a source address, a frame type, a power source data field, and a frame check;

the power source data field comprises a frame number, a control word, voltage data and current data;

the control word contains the corresponding power source in-loop information and alarm information, and the initial values of the in-loop information and the alarm information in the control word are all 0.

8. The method for chain power source control based on determined time slots as claimed in claim 7, wherein in the step 3, for the first-come sampling sequence number data sequence:

after receiving the first sampling sequence number data sequence from one of the Ethernet networks, the sub-FPGA analyzes a time synchronization frame and a power source data frame in the sampling sequence number data sequence,

if the sub-FPGA finds a corresponding power source data frame in the sampling sequence number data sequence, controlling the output of the digital-to-analog conversion module according to the voltage data and the current data of each channel of the power source data frame corresponding to the sub-FPGA, performing power amplification through the power amplifier, and setting the ring information in the control word corresponding to the power source data frame to be 1; when an alarm exists in the power source, setting the alarm information corresponding to the power source data frame to be 1;

after the sub-FPGA analyzes the time synchronization frame, acquiring main clock time, single-stage path delay and current-stage accumulated delay, and updating the system time of the sub-FPGA according to the total of the main clock time, the single-stage path delay and the current-stage accumulated delay;

the sub-FPGA forwards the updated sampling sequence number data sequence to the next sub-FPGA or the main PFGA along the loop propagation direction through another Ethernet.

9. The method for controlling a chained power source based on a determined time slot as claimed in claim 8, wherein in step 3, for the subsequent sample sequence number data sequence:

after receiving the sampling serial number data sequence from one of the Ethernet networks, the sub-FPGA updates the ring information and the alarm information in the control word in the power source data frame, updates the current-stage accumulated time delay in the time synchronization frame, and forwards the updated sampling serial number data sequence to the next sub-FPGA or the main PFGA along the loop propagation direction through the other Ethernet network.

10. The method for controlling a chained power source based on a determined time slot as claimed in claim 9, wherein in the step 4:

if the main FPGA does not receive the time synchronization frames in the sampling sequence number data sequences of the two same sampling sequence numbers, otherwise, one loop propagation direction is considered to be disconnected, and loop disconnection alarm reminding is carried out;

the main FPGA analyzes the ring information and the alarm information in the control word in the power source data frame, if the ring information in the power source data frame is 0, the corresponding power source is judged not to be in the ring, if the alarm information in the power source data frame is 1, the corresponding power source is judged to be in fault, and if the power source is judged not to be in the ring or the power source is in fault, the voltage data and the current data in the corresponding power source data frame are 0.