CN117389183A - Chained power source control method and system based on determined time slot - Google Patents

Abstract

The invention discloses a chain type power source control system based on a determined time slot, which comprises a main FPGA, wherein the main FPGA comprises an Ethernet A and an Ethernet B, each power source comprises the Ethernet A and the Ethernet B, the Ethernet B of the power source is connected with the Ethernet A of the next stage of power source through optical fibers, the serial connection of the power sources is further realized, the Ethernet A of the power source at the head end is connected with the Ethernet A of the main FPGA through optical fibers, and the Ethernet B of the power source at the tail end is connected with the Ethernet B of the main FPGA through optical fibers. The sampling sequence number data sequence adopts bidirectional loop propagation, improves the reliability of the sampling sequence number data sequence propagation and power source control, and simultaneously has loop disconnection alarm reminding, power source non-loop reminding and power source fault reminding.

Description

Chained power source control method and system based on determined time slot

Technical Field

The invention relates to the technical field of power simulation power sources, in particular to a chained power source control system based on a determined time slot and a chained power source control method based on the determined time slot.

Background

In relay protection test of a power system, analog power equipment is often used, a single analog power source cannot meet the requirement of whole interval or whole station test, and multiple power source equipment is needed. In general, a conventional analog power source adopts analog small signal input or single Ethernet interface for access, and when a plurality of analog power sources need to be accessed into a system, the conventional analog small signal or single Ethernet mode can not meet the test requirement.

Disclosure of Invention

The invention aims to solve the problems in the prior art, and provides a chained power source control system based on a determined time slot and a chained power source control method based on the determined time slot.

The chain type power source control system based on the determined time slot comprises a main FPGA, wherein the main FPGA comprises an Ethernet A and an Ethernet B, each power source comprises the Ethernet A and the Ethernet B, the Ethernet B of the power source is connected with the Ethernet A of the next-stage power source through optical fibers, each power source is connected in series, the Ethernet A of the power source at the head end is connected with the Ethernet A of the main FPGA through optical fibers, the Ethernet B of the power source at the tail end is connected with the Ethernet B of the main FPGA through optical fibers,

the power source comprises a sub-FPGA, a digital-to-analog conversion module and a power amplification module, wherein the sub-FPGA comprises an Ethernet A and an Ethernet B, the sub-FPGA is connected with the digital-to-analog conversion module, the digital-to-analog conversion module is connected with the power amplification module,

the method comprises the steps that a main FPGA generates a sampling sequence number data sequence, wherein the sampling sequence number data sequence sequentially comprises a time synchronization frame and a plurality of power source data frames, and the power source data frames correspond to power sources one by one;

the main FPGA sends out a sampling sequence number data sequence from the Ethernet A and the Ethernet B respectively, and the sampling sequence number data sequence sent out from the Ethernet A of the main FPGA sequentially passes through each sub-FPGA according to the forward loop propagation direction from the head terminal FPGA to the tail sub-FPGA and is received from the Ethernet B of the main FPGA; the sampling sequence number data sequence sent from the Ethernet B of the main FPGA sequentially passes through each sub-FPGA according to the reverse loop propagation direction from the tail sub-FPGA to the head sub-FPGA and is received from the Ethernet A of the main FPGA;

for the same sampling sequence number data sequence in different loop propagation directions, the sub-FPGA selects the first sampling sequence number data sequence, analyzes a time synchronization frame and a power source data frame in the sampling sequence number data sequence, updates the system time of the sub-FPGA according to the time synchronization frame, and outputs corresponding voltage and current according to the power source data frame;

the main PFGA judges whether the loop propagation direction is disconnected, whether the power source is in the loop or not and whether the power source fails or not according to the received sampling sequence number data sequence.

The time synchronization frame includes a frame spacer, a destination address, a source address, a frame type, a time synchronization field, and a frame check as described above;

the time synchronization field comprises a master clock time, single-stage path delay, current-stage accumulated delay, sampling rate and sampling sequence number;

the single-stage path delay is the path delay from the main FPGA to the next sub-FPGA or the multipath delay between two adjacent sub-FPGAs;

the sub-FPGA adds the current-level accumulated time delay in the received time synchronous frame with the single-stage path time delay and the current-level forwarding time delay to obtain the corrected current-level accumulated time delay which is written into the current-level accumulated time delay in the time synchronous frame, the current-level forwarding time delay is the time from the start of receiving data by the Ethernet A of the current-level sub-FPGA to the start of forwarding the data to the Ethernet B of the current-level sub-FPGA,

the power source data frame comprises a frame spacer, a destination address, a source address, a frame type, a power source data field, and a frame check;

the power source data field comprises a frame number, a control word, voltage data and current data;

the control word contains the corresponding power source in-loop information and alarm information, and the initial values of the in-loop information and the alarm information in the control word are all 0.

After receiving the first sampling sequence number data sequence from one of the Ethernet networks, the sub-FPGA analyzes the time synchronization frame and the power source data frame in the sampling sequence number data sequence,

if the sub-FPGA finds a corresponding power source data frame in the sampling sequence number data sequence, controlling the output of the digital-to-analog conversion module according to the voltage data and the current data of each channel of the power source data frame corresponding to the sub-FPGA, performing power amplification through the power amplifier, and setting the ring information in the control word corresponding to the power source data frame to be 1; when an alarm exists in the power source, setting the alarm information corresponding to the power source data frame to be 1;

after the sub-FPGA analyzes the time synchronization frame, acquiring main clock time, single-stage path delay and current-stage accumulated delay, and updating the system time of the sub-FPGA according to the total of the main clock time, the single-stage path delay and the current-stage accumulated delay;

the sub-FPGA forwards the updated sampling sequence number data sequence to the next sub-FPGA or the main PFGA along the loop propagation direction through another Ethernet.

After the sub-FPGA receives the sampling sequence number data sequence from one of its own ethernet networks, as described above:

after receiving the sampling serial number data sequence from one of the Ethernet networks, the sub-FPGA updates the ring information and the alarm information in the control word in the power source data frame, updates the current-stage accumulated time delay in the time synchronization frame, and forwards the updated sampling serial number data sequence to the next sub-FPGA or the main PFGA along the loop propagation direction through the other Ethernet network.

If the main FPGA does not receive the time synchronization frames in the sampling sequence number data sequences of the two same sampling sequence numbers, otherwise, one loop propagation direction is considered to be disconnected, and loop disconnection alarm reminding is carried out;

the main FPGA analyzes the ring information and the alarm information in the control word in the power source data frame, if the ring information in the power source data frame is 0, the corresponding power source is judged not to be in the ring, if the alarm information in the power source data frame is 1, the corresponding power source is judged to be in fault, and if the power source is judged not to be in the ring or the power source is in fault, the voltage data and the current data in the corresponding power source data frame are 0.

A chained power source control method based on a determined time slot comprises the following steps:

step 1, a main FPGA generates a sampling sequence number data sequence, wherein the sampling sequence number data sequence sequentially comprises a time synchronization frame and a plurality of power source data frames, and the power source data frames correspond to power sources one by one;

step 2, the main FPGA sends out a sampling sequence number data sequence from the Ethernet A and the Ethernet B respectively, and the sampling sequence number data sequence sent out from the Ethernet A of the main FPGA sequentially passes through all the sub-FPGAs according to the forward loop propagation direction from the head terminal FPGA to the tail sub-FPGA and is received from the Ethernet B of the main FPGA; the sampling sequence number data sequence sent from the Ethernet B of the main FPGA sequentially passes through each sub-FPGA according to the reverse loop propagation direction from the tail sub-FPGA to the head sub-FPGA and is received from the Ethernet A of the main FPGA;

step 3, for the same sampling sequence number data sequence in different loop propagation directions, the sub-FPGA selects the first sampling sequence number data sequence, analyzes a time synchronization frame and a power source data frame in the sampling sequence number data sequence, updates the system time of the sub-FPGA according to the time synchronization frame, and outputs corresponding voltage and current according to the power source data frame;

and 4, the main PFGA judges whether the loop propagation direction is disconnected, whether the power source is in the loop or not and whether the power source fails or not according to the received sampling sequence number data sequence.

In the step 1 as described above,

the time synchronization frame comprises a frame spacer, a destination address, a source address, a frame type, a time synchronization field, and a frame check;

the time synchronization field comprises a master clock time, single-stage path delay, current-stage accumulated delay, sampling rate and sampling sequence number;

the single-stage path delay is the path delay from the main FPGA to the next sub-FPGA or the multipath delay between two adjacent sub-FPGAs;

the sub-FPGA adds the current-level accumulated time delay in the received time synchronous frame with the single-stage path time delay and the current-level forwarding time delay to obtain the corrected current-level accumulated time delay which is written into the current-level accumulated time delay in the time synchronous frame, the current-level forwarding time delay is the time from the start of receiving data by the Ethernet A of the current-level sub-FPGA to the start of forwarding the data to the Ethernet B of the current-level sub-FPGA,

the power source data frame comprises a frame spacer, a destination address, a source address, a frame type, a power source data field, and a frame check;

the power source data field comprises a frame number, a control word, voltage data and current data;

the control word contains the corresponding power source in-loop information and alarm information, and the initial values of the in-loop information and the alarm information in the control word are all 0.

For the first sample sequence number data sequence in step 3 as described above:

after receiving the first sampling sequence number data sequence from one of the Ethernet networks, the sub-FPGA analyzes a time synchronization frame and a power source data frame in the sampling sequence number data sequence,

if the sub-FPGA finds a corresponding power source data frame in the sampling sequence number data sequence, controlling the output of the digital-to-analog conversion module according to the voltage data and the current data of each channel of the power source data frame corresponding to the sub-FPGA, performing power amplification through the power amplifier, and setting the ring information in the control word corresponding to the power source data frame to be 1; when an alarm exists in the power source, setting the alarm information corresponding to the power source data frame to be 1;

after the sub-FPGA analyzes the time synchronization frame, acquiring main clock time, single-stage path delay and current-stage accumulated delay, and updating the system time of the sub-FPGA according to the total of the main clock time, the single-stage path delay and the current-stage accumulated delay;

the sub-FPGA forwards the updated sampling sequence number data sequence to the next sub-FPGA or the main PFGA along the loop propagation direction through another Ethernet.

For the subsequent sample sequence number data sequence in step 3 as described above:

after receiving the sampling serial number data sequence from one of the Ethernet networks, the sub-FPGA updates the ring information and the alarm information in the control word in the power source data frame, updates the current-stage accumulated time delay in the time synchronization frame, and forwards the updated sampling serial number data sequence to the next sub-FPGA or the main PFGA along the loop propagation direction through the other Ethernet network.

In step 4 as described above:

if the main FPGA does not receive the time synchronization frames in the sampling sequence number data sequences of the two same sampling sequence numbers, otherwise, one loop propagation direction is considered to be disconnected, and loop disconnection alarm reminding is carried out;

the main FPGA analyzes the ring information and the alarm information in the control word in the power source data frame, if the ring information in the power source data frame is 0, the corresponding power source is judged not to be in the ring, if the alarm information in the power source data frame is 1, the corresponding power source is judged to be in fault, and if the power source is judged not to be in the ring or the power source is in fault, the voltage data and the current data in the corresponding power source data frame are 0.

Compared with the prior art, the invention has the following beneficial effects:

1, the digital input mode of the optical Ethernet mode is adopted, so that the optical network has stability, anti-interference performance and easy wiring compared with the analog small signal mode;

2, by adopting a chain connection mode, a plurality of optical Ethernet ports required by the main control equipment can be saved, and the number of hardware interfaces is reduced;

and 3, the stability of the network can be obviously enhanced based on bidirectional redundant communication by adopting a chain connection mode.

Drawings

FIG. 1 is a schematic diagram of a chain power source control system based on a determined time slot;

FIG. 2 is a schematic diagram of a sample sequence number data sequence;

fig. 3 is a schematic frame structure diagram of a time synchronization frame and a power source data frame.

Detailed Description

The present invention will be further described in detail below in conjunction with the following examples, for the purpose of facilitating understanding and practicing the present invention by those of ordinary skill in the art, it being understood that the examples described herein are for the purpose of illustration and explanation only and are not intended to limit the invention.

The chain type power source control system based on the determined time slots comprises a main FPGA and a plurality of power sources, wherein the main FPGA comprises an Ethernet A and an Ethernet B, each power source comprises the Ethernet A and the Ethernet B, the Ethernet B of the power source is connected with the Ethernet A of the next stage of power source through optical fibers, the serial connection of the power sources is further realized, the Ethernet A of the power source at the head end is connected with the Ethernet A of the main FPGA through optical fibers, and the Ethernet B of the power source at the tail end is connected with the Ethernet B of the main FPGA through optical fibers.

The power source comprises a sub-FPGA, a digital-to-analog conversion module and a power amplification module, wherein the sub-FPGA comprises an Ethernet A and an Ethernet B, the sub-FPGA is connected with the digital-to-analog conversion module, and the digital-to-analog conversion module is connected with the power amplification module.

The chain type power source control method based on the determined time slot utilizes the chain type power source control system based on the determined time slot, and comprises the following steps:

step 1, a main FPGA generates a sampling sequence number data sequence, wherein the sampling sequence number data sequence sequentially comprises a time synchronization frame TimeSync and a plurality of power source data frames, and the power source data frames correspond to power sources one by one;

the time synchronization frame TimeSync includes a frame spacer SDF (8 bytes), a destination address DA (1 byte), a source address SA (1 byte), a frame type FrameType (1 byte), a time synchronization field (41 bytes), and a frame check FCS (4 bytes), totaling 56 bytes;

the time synchronization field comprises a master clock time MasterTime, a single-stage path delay TDelay, a current-stage accumulated delay FDelay, a sampling rate sampleRate and a sampling sequence number sampleNum;

the master clock time MasterTime is the time information of the master FPGA, 1 is added every 10ns and is the time reference of the whole system, and the time interval of the sampling points of two adjacent times is 250us;

single-stage path delay TDelay, which is the path delay from a main FPGA to the next sub-FPGA or the multipath delay between two adjacent sub-FPGAs, including the delay of possible physical layer PHY, optical module, optical fiber and other devices, usually each stage of delay of a circuit module can be considered as the same;

the method for correcting the self-level accumulated time delay FDelay comprises the steps of starting to fill 0 on a main FPGA side, calculating and writing the 0 by each subsequent sub-FPGA, wherein the self-level accumulated time delay FDelay correction method is to add the self-level accumulated time delay FDelay in a received time synchronization frame with single-stage path delay TDelay and the self-level forwarding time delay, and the corrected self-level accumulated time delay FDelay is rewritten to the self-level accumulated time delay FDelay in the time synchronization frame. The local stage forwarding delay is the time from the start of receiving data by the Ethernet A of the local stage sub-FPGA to the start of forwarding the data to the Ethernet B of the local stage sub-FPGA.

The sampling rate SampleRate is 4000hz, the Ethernet A of the main FPGA divides the gigabit Ethernet line speed 1000Mbs into 4000 intervals according to the sampling rate 4000hz, namely, the length of each interval is 250us, and the number of bytes of transmittable data is 125000000/4000, namely 31250 bytes; further, to better control the transmission time and utilization bandwidth, each 250us is divided into 255 precise slots, i.e., 122 bytes of bytes can be transmitted per precise slot. At each 250us interval, a sequence of sample sequence number data is transmitted as shown in fig. 2.

The sampling sequence number sampplenum is the sequence number of the sampling sequence number data sequence. The sampling rate SampleRate is set to 4000hz, and the sampling sequence number SampleNum increases from 0 to 3999 in sequence.

The power source data frame includes a frame spacer SDF (8 bytes), a destination address DA (1 byte), a source address SA (1 byte), a frame type FrameType (1 byte), a power source data field (41 bytes), and a frame check FCS (4 bytes), totaling 56 bytes;

the power source data field includes a frame sequence number FrameNum, a control word ctrlword, voltage data, and current data.

The control word ctrlword contains the corresponding ring information and alarm information of the power source, and the initial values of the ring information and the alarm information in the control word ctrlword are both 0.

The voltage data is the output voltage value of each voltage channel of the corresponding power source,

the current data is the output current value of each current channel of the corresponding power source,

each power source has an independent address, the address of the main FPGA is 0x00, the address of the power source 1 is 0x01, and the like, and 0xff is a broadcast address. The destination address DA in the time sync frame TimeSync is a broadcast address. The destination address of the power source data frame is the address of the corresponding power source (i.e., the address of the sub FPGA).

Step 2, the main FPGA sends out a sampling sequence number data sequence from the Ethernet A and the Ethernet B respectively, and the sampling sequence number data sequence sent out from the Ethernet A of the main FPGA sequentially passes through all the sub-FPGAs according to the forward loop propagation direction from the head terminal FPGA to the tail sub-FPGA and is received from the Ethernet B of the main FPGA; the sampling sequence number data sequence sent from the Ethernet B of the main FPGA sequentially passes through each sub-FPGA according to the reverse loop propagation direction from the tail sub-FPGA to the head sub-FPGA and is received from the Ethernet A of the main FPGA;

step 3, the sub-FPGA receives two sampling sequence number data sequences of the same sampling sequence number under normal conditions, and carries out loop transmission clockwise and anticlockwise, the sub-FPGA adopts a first-come first-use principle for the same sampling sequence number data sequences of different loop propagation directions,

for the first-come sample sequence number data sequence:

after receiving the first sampling sequence number Data sequence from one of the Ethernet networks, the sub-FPGA analyzes a time synchronization frame TimeSync and a power source Data frame PA Data in the sampling sequence number Data sequence,

if the sub-FPGA finds out the corresponding power source Data frame PA Data in the sampling sequence number Data sequence, namely the destination address DA in the power source Data frame PA Data corresponding to the sub-FPGA is the same as the address of the sub-FPGA, controlling the digital-to-analog conversion module DA to output according to the voltage Data and the current Data of each channel of the power source Data frame PA Data corresponding to the sub-FPGA, and setting the ring information in the control word ctrlword corresponding to the power source Data frame to be 1 through PA power amplification; when any alarm exists in the power source, including over-temperature, short circuit, open circuit and other alarm information, the alarm information corresponding to the power source data frame is set to be 1.

After the sub-FPGA analyzes the time synchronization frame TimeSync, acquiring a master clock time MasterTime, a single-stage path delay TDelay and a current-stage accumulated delay FDelay, and updating the system time of the sub-FPGA according to the MasterTimer+TDelay+FDelay, namely synchronizing the internal system time of the sub-FPGA to the time of the whole system;

the sub-FPGA further analyzes the sampling rate SampleRate in the time synchronization frame, and determines an accurate power source Data frame PA Data to be output to the digital-to-analog conversion module DA according to the system time and the sampling rate SampleRate in the sub-FPGA;

the sub-FPGA forwards the updated sampling sequence number data sequence to the next sub-FPGA or the main PFGA along the loop propagation direction (forward loop propagation direction or reverse loop propagation direction) through the other Ethernet;

for the subsequent sample sequence number data sequence:

after receiving the sampling sequence number Data sequence from one Ethernet, the sub-FPGA only updates ring information and alarm information in a control word ctrlword in a power source Data frame PA Data, updates the local accumulated time delay FDelay in a time synchronization frame TimeSync, and forwards the updated sampling sequence number Data sequence to the next sub-FPGA or the main PFGA along the loop propagation direction (forward loop propagation direction or reverse loop propagation direction) through the other Ethernet;

step 4, the main PFGA receives the sampling sequence number Data sequence, analyzes the time synchronization frame TimeSync and the power source Data frame PA Data,

the main FPGA receives the time synchronization frames TimeSync in the sampling sequence number data sequences of the two sampleNum with the same sampling sequence number, otherwise, the main FPGA considers that a certain loop propagation direction of a link is disconnected, and loop disconnection alarm reminding is carried out;

the main FPGA analyzes the ring information and the alarm information in the control word ctrlword in the power source data frame, if the ring information in the power source data frame is 0, the corresponding power source is judged not to be in a ring, if the alarm information in the power source data frame is 1, the corresponding power source fault is judged, and the corresponding power source register table is updated to be used as whether the corresponding power source is on line or not, and whether abnormal alarms such as over-temperature, short circuit, open circuit and the like exist or not;

the main FPGA determines whether to continue outputting data of the corresponding power source according to the ring information and the alarm information in the corresponding control sub ctrlword, and if the power source is judged not to be in the ring or to be in fault, the voltage data and the current data in the corresponding power source data frame are 0, namely the corresponding power source does not output voltage and current.

It should be noted that the specific embodiments described in this application are merely illustrative of the spirit of the invention. Those skilled in the art may make various modifications or additions to the described embodiments or substitutions thereof without departing from the spirit of the invention or its scope as defined in the accompanying claims.

Claims (10)

1. The chain type power source control system based on the determined time slot comprises a main FPGA, and is characterized in that the main FPGA comprises an Ethernet A and an Ethernet B, each power source comprises the Ethernet A and the Ethernet B, the Ethernet B of the power source is connected with the Ethernet A of the next-stage power source through an optical fiber, each power source is connected in series, the Ethernet A of the power source at the head end is connected with the Ethernet A of the main FPGA through an optical fiber, the Ethernet B of the power source at the tail end is connected with the Ethernet B of the main FPGA through an optical fiber,

the power source comprises a sub-FPGA, a digital-to-analog conversion module and a power amplification module, wherein the sub-FPGA comprises an Ethernet A and an Ethernet B, the sub-FPGA is connected with the digital-to-analog conversion module, the digital-to-analog conversion module is connected with the power amplification module,

the method comprises the steps that a main FPGA generates a sampling sequence number data sequence, wherein the sampling sequence number data sequence sequentially comprises a time synchronization frame and a plurality of power source data frames, and the power source data frames correspond to power sources one by one;

the main FPGA sends out a sampling sequence number data sequence from the Ethernet A and the Ethernet B respectively, and the sampling sequence number data sequence sent out from the Ethernet A of the main FPGA sequentially passes through each sub-FPGA according to the forward loop propagation direction from the head terminal FPGA to the tail sub-FPGA and is received from the Ethernet B of the main FPGA; the sampling sequence number data sequence sent from the Ethernet B of the main FPGA sequentially passes through each sub-FPGA according to the reverse loop propagation direction from the tail sub-FPGA to the head sub-FPGA and is received from the Ethernet A of the main FPGA;

for the same sampling sequence number data sequence in different loop propagation directions, the sub-FPGA selects the first sampling sequence number data sequence, analyzes a time synchronization frame and a power source data frame in the sampling sequence number data sequence, updates the system time of the sub-FPGA according to the time synchronization frame, and outputs corresponding voltage and current according to the power source data frame;

the main PFGA judges whether the loop propagation direction is disconnected, whether the power source is in the loop or not and whether the power source fails or not according to the received sampling sequence number data sequence.

2. The system of claim 1, wherein the time synchronization frame comprises a frame spacer, a destination address, a source address, a frame type, a time synchronization field, and a frame check;

the time synchronization field comprises a master clock time, single-stage path delay, current-stage accumulated delay, sampling rate and sampling sequence number;

the single-stage path delay is the path delay from the main FPGA to the next sub-FPGA or the multipath delay between two adjacent sub-FPGAs;

the sub-FPGA adds the current-level accumulated time delay in the received time synchronous frame with the single-stage path time delay and the current-level forwarding time delay to obtain the corrected current-level accumulated time delay which is written into the current-level accumulated time delay in the time synchronous frame, the current-level forwarding time delay is the time from the start of receiving data by the Ethernet A of the current-level sub-FPGA to the start of forwarding the data to the Ethernet B of the current-level sub-FPGA,

the power source data frame comprises a frame spacer, a destination address, a source address, a frame type, a power source data field, and a frame check;

the power source data field comprises a frame number, a control word, voltage data and current data;

the control word contains the corresponding power source in-loop information and alarm information, and the initial values of the in-loop information and the alarm information in the control word are all 0.

3. The system of claim 2, wherein the sub-FPGA parses the time sync frame and the power source data frame in the sequence of sample sequence numbers after receiving the first sequence of sample sequence numbers from one of its own ethernets,

if the sub-FPGA finds a corresponding power source data frame in the sampling sequence number data sequence, controlling the output of the digital-to-analog conversion module according to the voltage data and the current data of each channel of the power source data frame corresponding to the sub-FPGA, performing power amplification through the power amplifier, and setting the ring information in the control word corresponding to the power source data frame to be 1; when an alarm exists in the power source, setting the alarm information corresponding to the power source data frame to be 1;

after the sub-FPGA analyzes the time synchronization frame, acquiring main clock time, single-stage path delay and current-stage accumulated delay, and updating the system time of the sub-FPGA according to the total of the main clock time, the single-stage path delay and the current-stage accumulated delay;

the sub-FPGA forwards the updated sampling sequence number data sequence to the next sub-FPGA or the main PFGA along the loop propagation direction through another Ethernet.

4. A chained power source control system based on a determined time slot as claimed in claim 3, wherein said sub-FPGA receives a sequence of sample sequence numbers from one of its own ethernet networks:

after receiving the sampling serial number data sequence from one of the Ethernet networks, the sub-FPGA updates the ring information and the alarm information in the control word in the power source data frame, updates the current-stage accumulated time delay in the time synchronization frame, and forwards the updated sampling serial number data sequence to the next sub-FPGA or the main PFGA along the loop propagation direction through the other Ethernet network.

5. The system of claim 4, wherein if the main FPGA does not receive the time synchronization frame in the sequence of two sampling sequence numbers with the same sampling sequence number, it considers that one of the loop propagation directions is disconnected, and performs a loop disconnection alarm reminding;

the main FPGA analyzes the ring information and the alarm information in the control word in the power source data frame, if the ring information in the power source data frame is 0, the corresponding power source is judged not to be in the ring, if the alarm information in the power source data frame is 1, the corresponding power source is judged to be in fault, and if the power source is judged not to be in the ring or the power source is in fault, the voltage data and the current data in the corresponding power source data frame are 0.

6. The chain type power source control method based on the determined time slot is characterized by comprising the following steps:

step 1, a main FPGA generates a sampling sequence number data sequence, wherein the sampling sequence number data sequence sequentially comprises a time synchronization frame and a plurality of power source data frames, and the power source data frames correspond to power sources one by one;

step 2, the main FPGA sends out a sampling sequence number data sequence from the Ethernet A and the Ethernet B respectively, and the sampling sequence number data sequence sent out from the Ethernet A of the main FPGA sequentially passes through all the sub-FPGAs according to the forward loop propagation direction from the head terminal FPGA to the tail sub-FPGA and is received from the Ethernet B of the main FPGA; the sampling sequence number data sequence sent from the Ethernet B of the main FPGA sequentially passes through each sub-FPGA according to the reverse loop propagation direction from the tail sub-FPGA to the head sub-FPGA and is received from the Ethernet A of the main FPGA;

step 3, for the same sampling sequence number data sequence in different loop propagation directions, the sub-FPGA selects the first sampling sequence number data sequence, analyzes a time synchronization frame and a power source data frame in the sampling sequence number data sequence, updates the system time of the sub-FPGA according to the time synchronization frame, and outputs corresponding voltage and current according to the power source data frame;

and 4, the main PFGA judges whether the loop propagation direction is disconnected, whether the power source is in the loop or not and whether the power source fails or not according to the received sampling sequence number data sequence.

7. The method of claim 6, wherein in the step 1,

the time synchronization frame comprises a frame spacer, a destination address, a source address, a frame type, a time synchronization field, and a frame check;

the time synchronization field comprises a master clock time, single-stage path delay, current-stage accumulated delay, sampling rate and sampling sequence number;

the single-stage path delay is the path delay from the main FPGA to the next sub-FPGA or the multipath delay between two adjacent sub-FPGAs;

the sub-FPGA adds the current-level accumulated time delay in the received time synchronous frame with the single-stage path time delay and the current-level forwarding time delay to obtain the corrected current-level accumulated time delay which is written into the current-level accumulated time delay in the time synchronous frame, the current-level forwarding time delay is the time from the start of receiving data by the Ethernet A of the current-level sub-FPGA to the start of forwarding the data to the Ethernet B of the current-level sub-FPGA,

the power source data frame comprises a frame spacer, a destination address, a source address, a frame type, a power source data field, and a frame check;

the power source data field comprises a frame number, a control word, voltage data and current data;

the control word contains the corresponding power source in-loop information and alarm information, and the initial values of the in-loop information and the alarm information in the control word are all 0.

8. The method for chain power source control based on determined time slots as claimed in claim 7, wherein in the step 3, for the first-come sampling sequence number data sequence:

after receiving the first sampling sequence number data sequence from one of the Ethernet networks, the sub-FPGA analyzes a time synchronization frame and a power source data frame in the sampling sequence number data sequence,

if the sub-FPGA finds a corresponding power source data frame in the sampling sequence number data sequence, controlling the output of the digital-to-analog conversion module according to the voltage data and the current data of each channel of the power source data frame corresponding to the sub-FPGA, performing power amplification through the power amplifier, and setting the ring information in the control word corresponding to the power source data frame to be 1; when an alarm exists in the power source, setting the alarm information corresponding to the power source data frame to be 1;

after the sub-FPGA analyzes the time synchronization frame, acquiring main clock time, single-stage path delay and current-stage accumulated delay, and updating the system time of the sub-FPGA according to the total of the main clock time, the single-stage path delay and the current-stage accumulated delay;

the sub-FPGA forwards the updated sampling sequence number data sequence to the next sub-FPGA or the main PFGA along the loop propagation direction through another Ethernet.

9. The method for controlling a chained power source based on a determined time slot as claimed in claim 8, wherein in step 3, for the subsequent sample sequence number data sequence:

after receiving the sampling serial number data sequence from one of the Ethernet networks, the sub-FPGA updates the ring information and the alarm information in the control word in the power source data frame, updates the current-stage accumulated time delay in the time synchronization frame, and forwards the updated sampling serial number data sequence to the next sub-FPGA or the main PFGA along the loop propagation direction through the other Ethernet network.

10. The method for controlling a chained power source based on a determined time slot as claimed in claim 9, wherein in the step 4:

if the main FPGA does not receive the time synchronization frames in the sampling sequence number data sequences of the two same sampling sequence numbers, otherwise, one loop propagation direction is considered to be disconnected, and loop disconnection alarm reminding is carried out;

the main FPGA analyzes the ring information and the alarm information in the control word in the power source data frame, if the ring information in the power source data frame is 0, the corresponding power source is judged not to be in the ring, if the alarm information in the power source data frame is 1, the corresponding power source is judged to be in fault, and if the power source is judged not to be in the ring or the power source is in fault, the voltage data and the current data in the corresponding power source data frame are 0.