CN117389083A - Display panel and display device - Google Patents

Abstract

The present disclosure relates to a display panel, which includes a pixel electrode layer, the pixel electrode layer includes a blocking portion, the blocking portion covers one surface of a data trace far away from a substrate and wraps a side surface of the data trace, the blocking portion can protect the data trace, when etching liquid of the pixel electrode layer corrodes and dry etching gas of a first insulating layer bombards, the data trace is protected, thickness reduction of the data trace is avoided, a reference signal line is connected with the blocking portion through a via hole, and the reference signal line is conducted with the data trace. It can be understood that the display panel can effectively avoid the thickness reduction of the data wiring while not affecting the connection performance. The disclosure also provides a display device including the display panel.

Description

Display panel and display device

Technical Field

The disclosure relates to the technical field of display, in particular to a display panel and a display device.

Background

The application range of the liquid crystal panel is becoming wider and wider at present, and the liquid crystal panel is widely applied to automobile central control display screens, computer display screens, liquid crystal televisions, medical appliances and the like.

For the display panel which is firstly used as the source and drain metal layer and then used as the pixel electrode layer, the thickness of the data wiring can be reduced due to corrosion of the etching liquid of the pixel electrode layer and dry etching gas bombardment of the first insulating layer, so that the display effect is affected.

It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The disclosure aims to solve the problems that after etching liquid of a pixel electrode layer corrodes and dry etching gas of a first insulating layer bombards a data wire, the thickness of the data wire is reduced, and provides a display panel and a display device.

According to one aspect of the present disclosure, there is provided a display panel having a display region and a non-display region located at a periphery of the display region, the display panel further including a substrate, a driving circuit layer, a pixel electrode layer, a first insulating layer, and a common electrode layer: the driving circuit layer is arranged on one side of the substrate base plate, the driving circuit layer comprises a source-drain metal layer, the source-drain metal layer comprises a data wire, and the data wire is positioned in the non-display area; the pixel electrode layer is arranged on one side of the driving circuit layer, which is far away from the substrate, and comprises a blocking part, wherein the blocking part covers one surface of the data wire, which is far away from the substrate, and wraps the side surface of the data wire; the first insulating layer is arranged on one side of the pixel electrode layer, which is far away from the substrate base plate; the common electrode layer is arranged on one side, far away from the substrate, of the first insulating layer, the common electrode layer comprises a reference signal line, the reference signal line is located in the non-display area, and the reference signal line is connected with the blocking part through a via hole.

In an embodiment of the disclosure, the driving circuit layer further includes a second insulating layer, the second insulating layer is disposed between the substrate and the source-drain metal layer, and the blocking portion extends from a side surface of the data trace to overlap the second insulating layer.

In one embodiment of the disclosure, the pixel electrode layer further includes a plurality of pixel electrodes arranged in an array, the driving circuit layer further includes a plurality of driving transistors, the plurality of pixel electrodes and the driving transistors are located in the display area, a third insulating layer is disposed between the pixel electrode layer and the source drain metal layer, the pixel electrode is connected with a drain electrode of the driving transistor through a via hole, and the drain electrode of the driving transistor is located in the source drain metal layer.

In one embodiment of the disclosure, the driving circuit layer further includes a gate layer disposed between the substrate and the second insulating layer, the gate layer includes a scan line extending along the row direction, the scan line is disposed between two adjacent rows of pixel electrodes, and the scan line is connected to a gate of the driving transistor to which one row of pixel electrodes is connected.

In one embodiment of the present disclosure, at least one set of dummy signal lines is provided along at least one side of the edges of the plurality of pixel electrodes in the column direction, each set of dummy signal lines includes two dummy signal lines, and the sum of the number of scan lines and the number of dummy signal lines is an integer multiple of 8, so that the scan line closest to the edges of the plurality of pixel electrodes in the column direction inputs the first clock signal.

In one embodiment of the present disclosure, the number of the scanning lines is an even number, and when the remainder of dividing the number of the scanning lines by 8 is greater than 4, a plurality of groups of virtual signal lines are disposed on the outer sides of the plurality of pixel electrodes along the column direction, and the plurality of groups of virtual signal lines are distributed on one side or both sides of the plurality of pixel electrodes along the column direction.

In one embodiment of the present disclosure, when a plurality of groups of dummy signal lines are distributed on both sides of a plurality of pixel electrodes along a column direction, a part of the dummy signal lines are located outside a first side of the plurality of pixel electrodes, another part of the dummy signal lines are located outside a second side of the plurality of pixel electrodes, the second side is disposed opposite to the first side along the column direction, and the number of groups of dummy signal lines outside the plurality of pixel electrodes is equal or unequal.

In one embodiment of the present disclosure, the scan lines scan in a sequence from the first side to the second side in the column direction, or the scan lines scan in a sequence from the second side to the first side in the column direction.

In one embodiment of the present disclosure, two dummy signal lines in each set of dummy signal lines are located on the same straight line in the row direction.

According to still another aspect of the present disclosure, there is provided a display device including the display panel provided according to any one of the other aspects of the present disclosure.

The display panel comprises a pixel electrode layer, wherein the pixel electrode layer comprises a blocking part, the blocking part covers one surface of a data wire far away from a substrate base plate and wraps the side surface of the data wire, the blocking part can protect the data wire, when etching liquid of the pixel electrode layer corrodes and dry etching gas of a first insulating layer bombards, the data wire is protected, the reduction of the thickness of the data wire is avoided, a reference signal wire is connected with the blocking part through a through hole, and the reference signal wire is conducted with the data wire. It can be understood that the display panel can effectively avoid the thickness reduction of the data wiring while not affecting the connection performance.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.

Fig. 1 is a schematic cross-sectional view of a display area of a display panel according to an embodiment of the present disclosure.

Fig. 2 is a schematic cross-sectional view of a non-display region of a display panel according to an embodiment of the disclosure when the pixel electrode layer does not include a barrier.

Fig. 3 is a schematic cross-sectional view of a non-display region of a display panel according to an embodiment of the disclosure when a pixel electrode layer includes a barrier.

Fig. 4 is a schematic plan view of a display panel according to an embodiment of the disclosure when a plurality of scan lines are integer multiples of 8 and scan in a sequence from a first side to a second side in a column direction.

Fig. 5 is a schematic plan view of a display panel according to an embodiment of the disclosure when the plurality of scanning traces are not an integer multiple of 8 and the plurality of scanning traces are scanned in a sequence from a first side to a second side in a column direction.

Fig. 6 is a schematic plan view of a display panel according to an embodiment of the disclosure when the plurality of scanning traces are not an integer multiple of 8 and the plurality of scanning traces are scanned in the order from the second side to the first side in the column direction.

In the figure: 1-substrate, 2-driving circuit layer, 21-gate layer, 211-gate, 22-second insulating layer, 23-active layer, 231-active part, 24-source drain metal layer, 241-data wiring, 242-source, 243-drain, 201-driving transistor, 25-third insulating layer, 3-pixel layer, 31-pixel electrode layer, 311-pixel electrode, 312-barrier part, 32-first insulating layer, 33-common electrode layer, 331-common electrode, 332-reference signal line, 34-liquid crystal layer, 35-color film layer, 351-black matrix, 352-first color block, 353-second color block, 354-third color block, -sub-pixel, 4-packaging layer, 100-display area, 200-non-display area.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification for convenience only, such as in terms of the orientation of the examples described in the figures. It will be appreciated that if the device of the icon is flipped upside down, the recited "up" component will become the "down" component. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

The terms "a," "an," "the," "said" and "at least one" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and do not limit the number of their objects.

The application range of the liquid crystal panel is becoming wider and wider at present, and the liquid crystal panel is widely applied to automobile central control display screens, computer display screens, liquid crystal televisions, medical appliances and the like. As shown in fig. 1 and 2, in general, when manufacturing a display panel, the source-drain metal layer 24 is formed first, then the pixel electrode layer 31 is formed on a side far away from the substrate, and the first insulating layer 32 is formed on the side far away from the substrate 1 of the pixel electrode layer 31, so that the thickness of the source-drain metal layer 24 is reduced due to the etching liquid of the pixel electrode layer 31 and the dry etching gas bombardment of the first insulating layer 32, thereby affecting the display effect.

Based on this, the embodiment of the present disclosure provides a display panel. As shown in fig. 1 and 3 to 6, the display panel has a display region 100 and a non-display region 200 located at the periphery of the display region 100, and further includes a substrate 1, a driving circuit layer 2, a pixel electrode layer 31, a first insulating layer 32, and a common electrode layer 33: the driving circuit layer 2 is arranged on one side of the substrate 1, the driving circuit layer 2 comprises a source-drain metal layer 24, the source-drain metal layer 24 comprises a data wire 241, and the data wire 241 is positioned in the non-display area 200; the pixel electrode layer 31 is arranged on one side of the driving circuit layer 2 away from the substrate 1, the pixel electrode layer 31 comprises a blocking part 312, and the blocking part 312 covers one surface of the data wire 241 away from the substrate 1 and wraps the side surface of the data wire 241; the first insulating layer 32 is provided on a side of the pixel electrode layer 31 remote from the substrate 1; the common electrode layer 33 is disposed on a side of the first insulating layer 32 away from the substrate 1, and the common electrode layer 33 includes a reference signal line 332, where the reference signal line 332 is located in the non-display area 200, and the reference signal line is connected to the barrier 312 through a via hole.

The pixel electrode layer 31 includes a blocking portion 312, the blocking portion 312 covers a surface of the data trace 241 away from the substrate 1 and wraps a side surface of the data trace 241, the blocking portion 312 can protect the data trace 241, and when etching liquid of the pixel electrode layer 31 corrodes and dry etching gas of the first insulating layer 32 bombards, protection is formed on the data trace 241, thickness reduction of the data trace 241 is avoided, and the reference signal line 332 is connected with the blocking portion 312 through a via hole to conduct the reference signal line 332 with the data trace 241. It can be appreciated that the thickness of the data trace 241 is effectively prevented from being reduced while the connection performance is not affected.

The display panel according to the embodiment of the present disclosure will be described in detail with reference to specific examples.

As shown in fig. 1 and 3, the display panel may include a substrate 1, a driving circuit layer 2, and a pixel layer 3, which are sequentially stacked, the driving circuit layer 2 being disposed on one side of the substrate 1, and the pixel layer 3 being disposed on one side of the driving circuit layer 2 away from the substrate 1.

The substrate 1 may be an inorganic substrate 1 or an organic substrate 1. For example, in one embodiment of the present disclosure, the material of the substrate base plate 1 may be a glass material such as soda-lime glass (soda-lime glass), quartz glass, sapphire glass, or may be a metal material such as stainless steel, aluminum, nickel, or the like.

In another embodiment of the present disclosure, the material of the substrate base 1 may be polymethyl methacrylate (Polymemmhyl memmhacrylamme, PMMA), polyvinyl alcohol (Polyvinyl alcohol, PVA), polyvinyl phenol (PVP), polyethersulfone (Polyemmher sulfone, PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (Polyemmhylene mmerephmmhalamme, PEmm), polyethylene naphthalate (Polyemmhylene naphmmhalamme, PEN), or a combination thereof.

In another embodiment of the present disclosure, the substrate 1 may also be a flexible substrate 1, for example, the material of the substrate 1 may be Polyimide (PI). The substrate 1 may also be a composite of multiple layers of materials, for example, in one embodiment of the present disclosure, the substrate 1 may include a base Film layer (boom Film), a pressure-sensitive adhesive layer, a first polyimide layer, and a second polyimide layer, which are sequentially stacked.

The driving circuit layer 2 includes a driving transistor, which may be selected from a top gate thin film transistor, a bottom gate thin film transistor, or a double gate thin film transistor. The thin film transistor may have a first terminal, a second terminal, and a control terminal, one of the first terminal and the second terminal may be a source 242 of the driving transistor, and the other may be a drain 243 of the driving transistor, and the control terminal may be a gate 211 of the driving transistor. It will be appreciated that the source 242 and drain 243 of the drive transistor are two opposite and interchangeable concepts; the source 242 and drain 243 of the drive transistor may be interchanged when the operating state of the drive transistor is changed, for example when the direction of the current is changed.

In the present disclosure, the driving circuit layer 2 may include a gate layer 21, an active layer 23, a source drain metal layer 24, a second insulating layer 22, and a third insulating layer 25 sequentially stacked on the substrate 1. The positional relationship of the respective film layers may be determined according to the film layer structure of the thin film transistor. In the present disclosure, the driving circuit layer 2 may include a gate layer 21, a second insulating layer 22, an active layer 23, a source drain metal layer 24, and a third insulating layer 25 sequentially stacked on the substrate 1, and thus the thin film transistor formed is a top gate thin film transistor.

The gate layer 21 may be used to form a scan line, and may also be used to form the gate 211 of the driving transistor. The source drain metal layer 24 may be used to form the data trace 241, and may also be used to form the source 242 and drain 243 of the driving transistor. The active layer 23 may be used to form an active portion 231 of the driving transistor.

The active part 231 includes a channel region and source and drain regions located at both sides of the channel region; wherein the channel region may maintain semiconductor characteristics and the semiconductor material of the source and drain regions is partially or fully conductive.

The driving transistor is disposed in the display area 100, the orthographic projection of the gate electrode 211 on the substrate 1 covers the orthographic projection of the channel region of the active portion 231 on the substrate 1, the second insulating layer 22 covers the gate electrode 211, the source electrode 242 overlaps the source region of the active portion 231 and extends to the surface of the second insulating layer 22 along the source region, and the drain electrode 243 overlaps the drain region of the active portion 231 and extends to the surface of the second insulating layer 22 along the drain region. The third insulating layer 25 covers the source electrode 242 and the drain electrode 243.

In some embodiments, the material of the active layer 23 may be an amorphous silicon semiconductor material, a low temperature polysilicon semiconductor material, a metal oxide semiconductor material, an organic semiconductor material, or other types of semiconductor materials; the thin film transistor may be an N-type thin film transistor or a P-type thin film transistor.

The display panel further comprises a pixel layer 3, the pixel layer 3 comprises a pixel electrode layer 31, a first insulating layer 32, a common electrode layer 33 and a liquid crystal layer 34, the pixel electrode layer 31 is arranged on one side, far away from the substrate 1, of the driving circuit layer 2, the first insulating layer 32 is arranged on one side, far away from the substrate 1, of the pixel electrode layer 31, the common electrode layer 33 is arranged on one side, far away from the substrate 1, of the first insulating layer 32, and the liquid crystal layer 34 is arranged on one side, far away from the substrate 1, of the common electrode layer 33.

The pixel electrode layer 31 includes a plurality of pixel electrodes 311 arranged in an array, the pixel electrodes 311 are located in the display region 100, and the pixel electrodes 311 are connected to the drain electrodes 243 of the driving transistors through vias on the third insulating layer 25. The common electrode layer 33 includes a common electrode 331, and an orthographic projection of the common electrode 331 on the substrate 1 overlaps with an orthographic projection of the pixel electrode 311 on the substrate 1. The pixel electrode 311 and the common electrode 331 each have a driving surface, so that the liquid crystal layer 34 may be considered to be located between the pixel electrode 311 and the common electrode 331, each of the pixel electrode 311, the common electrode 331, and the liquid crystal layer 34 located between the pixel electrode 311 and the common electrode 331 may form one sub-pixel, and a plurality of the pixel electrodes 311 may form a plurality of sub-pixels.

The side of the liquid crystal layer 34 far away from the substrate 1 is provided with a color film layer 35, the color film layer 35 comprises a black matrix 351, the black matrix 351 is provided with a plurality of openings, a first color block 352, a second color block 353 and a third color block 354 are respectively arranged in the openings, the first color block 352 is red, the second color block 353 is green, and the third color block 354 is blue. The encapsulation layer 4 may be provided on the side of the color film layer 35 remote from the substrate 1.

The source drain metal layer 24 includes a data trace 241, and the data trace 241 is located in the non-display area 200. The pixel electrode layer 31 includes a blocking portion 312, the blocking portion 312 covers a surface of the data trace 241 away from the substrate 1, the blocking portion 312 wraps the side blocking portion 312 of the data trace 241, and extends from the side of the data trace 241 to overlap the second insulating layer 22. The distance between the edge of the blocking portion 312 and the edge of the data trace 241 may be greater than 2.25um. The common electrode layer 33 further includes a reference signal line 332, the reference signal line 332 is located in the non-display area 200, and the reference signal line 332 is connected to the barrier 312 through a via hole and is connected to the scan line through the via hole.

As shown in fig. 4 to 6, the scan line is located between two adjacent rows of pixel electrodes 311, and the scan line is connected to the gate electrode 211 of the driving transistor to which one row of pixel electrodes 311 is connected. The data trace 241 is located between two adjacent columns of pixel electrodes 311, the scan trace is connected to the source 242 of one of the columns of driving transistors, and the drain 243 of the driving transistor is connected to one of the adjacent columns of pixel electrodes 311.

The number of rows of the scan lines is generally an integer multiple of 8, but there are some scan lines of the GOA circuit that have a number other than an integer multiple of 8, so the present embodiment ensures that the number of lines of the GOA circuit is an integer multiple of 8 by adding the dummy signal lines, and the scan line closest to the edges of the plurality of pixel electrodes 311 along the column direction inputs the first clock signal.

The plurality of pixel electrodes 311 have a first side and a second side disposed opposite to each other in the column direction, and a set of dummy signal lines is disposed outside the first side or the second side of the edges of the plurality of pixel electrodes 311 in the column direction. When the GOA circuit includes multiple groups of dummy signal lines, when the multiple groups of dummy signal lines are distributed on both sides of the plurality of pixel electrodes 311 along the column direction, a part of the dummy signal lines are located outside a first side of the plurality of pixel electrodes 311, and another part of the dummy signal lines are located outside a second side of the plurality of pixel electrodes 311, and the groups of the dummy signal lines outside the plurality of pixel electrodes 311 are equal or unequal. Each group of virtual signal lines comprises two virtual signal lines, and the two virtual signal lines in each group of virtual signal lines are positioned on the same straight line along the row direction.

As shown in fig. 4, scan lines G1, G2, G3...g8n are sequentially disposed along a first side to a second side in the column direction, the scan lines have first and second ends opposite in the row direction, a first clock signal GLK1 may be input from the first end of the scan line G1, a second clock signal GLK2 may be input from the second end of the scan line G2, a third clock signal GLK3 may be input from the first end of the scan line G3, and an eighth clock signal GLK8 may be input from the second end of the scan line G8, n is a natural number 0, 1, 2. The first and second groups Dummy signal lines Dummy3, dummy4, dummy1, dummy2 are provided outside the first side of the plurality of pixel electrodes 311, and the third and fourth groups Dummy signal lines Dummy5, dummy6, dummy7, dummy8 are provided outside the second side of the plurality of pixel electrodes 311 in the display area.

In fig. 4, the first group Dummy signal lines Dummy3, dummy4 and the second group Dummy signal lines Dummy1, dummy2 are sequentially disposed in a direction away from the display area. The two Dummy signal lines Dummy3, dummy4 of the first group of Dummy signal lines respectively input the seventh clock signal GLK7 and the eighth clock signal GLK8, and the two Dummy signal lines Dummy1, dummy2 of the second group of Dummy signal lines respectively input the fifth clock signal GLK5 and the sixth clock signal GLK6. The two Dummy signal lines Dummy5, dummy6 of the third group of Dummy signal lines respectively input the first clock signal GLK1 and the second clock signal GLK2, and the two Dummy signal lines Dummy7, dummy8 of the fourth group of Dummy signal lines respectively input the third clock signal GLK3 and the fourth clock signal GLK4.

Since the two dummy signal lines of each group of dummy signal lines are not turned on, they are not actually input into the GOA circuit, but the order of the clock signals is changed, so that the scan line nearest to the second side of the plurality of pixel electrodes 311 in the column direction inputs the first clock signal, thereby facilitating the transmission of the gate driving signal (GOA signal). Since the number of scan lines in fig. 4 is an integer multiple of 8, the dummy signal lines may be provided or not provided.

As shown in fig. 5, scan lines G1, G2, G3...g8n-2 are sequentially disposed along a first side to a second side in the column direction, the scan lines have first and second ends opposite in the row direction, a first clock signal GLK1 may be input from the first end of the scan line G1, a second clock signal GLK2 may be input from the second end of the scan line G2, a third clock signal GLK3 may be input from the first end of the scan line G3, and a sixth clock signal GLK6 may be input from the second end of the scan line G8n-2, n is a natural number 0, 1, 2.

The remainder of dividing the number of scanning lines by 8 is 6, and the fifth group of signal lines is added, so that the sum of the number of scanning lines and the number of dummy signal lines is an integer multiple of 8, so that the scanning line closest to the edges of the plurality of pixel electrodes 311 in the column direction inputs the first clock signal, and the transmission of the gate driving signal (GOA signal) is facilitated. The first group Dummy signal lines Dummy3, dummy4 and the second group Dummy signal lines Dummy1, dummy2 are sequentially disposed on the outer side of the first side of the plurality of pixel electrodes 311 of the display area 100 in a direction away from the display area 100, and the third group Dummy signal lines Dummy5, dummy6, the fourth group Dummy signal lines Dummy7, dummy8 and the fifth group Dummy signal lines Dummy9, dummy10 are sequentially disposed on the outer side of the second side of the plurality of pixel electrodes 311 of the display area 100 in a direction away from the display area 100.

In fig. 5, two Dummy signal lines Dummy3, dummy4 of the first group of Dummy signal lines respectively input a seventh clock signal GLK7 and an eighth clock signal GLK8, and two Dummy signal lines Dummy1, dummy2 of the second group of Dummy signal lines respectively input a fifth clock signal GLK5 and a sixth clock signal GLK6. The two Dummy signal lines Dummy5, dummy6 of the third group of Dummy signal lines respectively input the seventh clock signal GLK7 and the eighth clock signal GLK8, the two Dummy signal lines Dummy7, dummy8 of the fourth group of Dummy signal lines respectively input the first clock signal GLK1 and the second clock signal GLK2, and the two Dummy signal lines Dummy9, dummy10 of the fifth group of Dummy signal lines respectively input the third clock signal GLK3 and the fourth clock signal GLK4.

As shown in fig. 6, scanning lines G1, G2, G3...g8n-2 are provided in this order along the second side to the first side in the column direction, and scanning is performed in this order along the second side to the first side in the column direction. The first-side outer sides of the plurality of pixel electrodes 311 of the display area 100 are sequentially provided with a first group Dummy signal lines Dummy5, dummy6, a second group Dummy signal lines Dummy7, dummy8, and a third group Dummy signal lines Dummy9, dummy10 in a direction away from the display area 100, and the second-side outer sides of the plurality of pixel electrodes 311 of the display area 100 are sequentially provided with a first group Dummy signal lines Dummy3, dummy4, and a second group Dummy signal lines Dummy1, dummy2 in a direction away from the display area 100.

In fig. 6, two Dummy signal lines Dummy5, dummy6 of the first group of Dummy signal lines respectively input a seventh clock signal GLK7 and an eighth clock signal GLK8, and two Dummy signal lines Dummy7, dummy8 of the second group of Dummy signal lines respectively input a first clock signal GLK1 and a second clock signal GLK2. The two Dummy signal lines Dummy9, dummy10 of the third group of Dummy signal lines respectively input the third clock signal GLK3 and the fourth clock signal GLK4, the two Dummy signal lines Dummy3, dummy4 of the fourth group of Dummy signal lines respectively input the seventh clock signal GLK7 and the eighth clock signal GLK8, and the two Dummy signal lines Dummy1, dummy2 of the fifth group of Dummy signal lines respectively input the fifth clock signal GLK5 and the sixth clock signal GLK6.

It will be appreciated that in fig. 4 and 5, the plurality of scan lines are scanned in the column direction in order from the first side to the second side. In fig. 6, the plurality of scan lines sequentially scan along the second side to the first side in the column direction.

When the remainder of dividing the number of scanning lines by 8 is greater than 4, the plurality of groups of dummy signal lines may be distributed on both sides of the plurality of pixel electrodes 311 in the column direction, or may be distributed on one side of the plurality of pixel electrodes 311 in the column direction. Whether the plurality of groups of virtual signal lines are distributed on one side or two sides of the plurality of pixel electrodes 311 along the column direction, the first clock signal needs to be input to the scanning trace closest to the second side of the plurality of pixel electrodes 311 along the column direction.

The embodiment of the disclosure also provides a display device. The display device may include a display panel of any of the above embodiments of the present disclosure. The specific structure and advantageous effects of the display panel have been described in detail above, and thus, will not be described here again.

It should be noted that, the display device includes other necessary components and components besides the display panel, such as a circuit board, a power cord, etc., and those skilled in the art can correspondingly supplement the components and components according to the specific usage requirements of the display device, which is not described herein.

The display device may be a conventional electronic device, for example: cell phones, computers, televisions, projectors and camcorders, but also emerging wearable devices, such as VR glasses, are not listed here.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims (10)

1. A display panel having a display area and a non-display area located at a periphery of the display area, the display panel further comprising:

a substrate base;

the driving circuit layer is arranged on one side of the substrate base plate and comprises a source-drain metal layer, the source-drain metal layer comprises a data wire, and the data wire is positioned in the non-display area;

the pixel electrode layer is arranged on one side, far away from the substrate, of the driving circuit layer, and comprises a blocking part, wherein the blocking part covers one side, far away from the substrate, of the data wire and wraps the side face of the data wire;

the first insulating layer is arranged on one side of the pixel electrode layer, which is far away from the substrate base plate;

and the common electrode layer is arranged on one side, far away from the substrate, of the first insulating layer, and comprises a reference signal line, wherein the reference signal line is positioned in the non-display area and is connected with the blocking part through a via hole.

2. The display panel of claim 1, wherein the driving circuit layer further comprises a second insulating layer disposed between the substrate and the source-drain metal layer, and the barrier portion extends from a side surface of the data trace to overlap the second insulating layer.

3. The display panel according to claim 2, wherein the pixel electrode layer further comprises a plurality of pixel electrodes arranged in an array, the driving circuit layer further comprises a plurality of driving transistors, the plurality of pixel electrodes and the driving transistors are located in the display area, a third insulating layer is arranged between the pixel electrode layer and the source-drain metal layer, the pixel electrodes are connected with the drain electrodes of the driving transistors through vias, and the drain electrodes of the driving transistors are located in the source-drain metal layer.

4. A display panel according to claim 3, wherein the drive circuit layer further comprises a gate layer disposed between the substrate base and the second insulating layer, the gate layer comprising a scan line extending in a row direction, the scan line being located between two adjacent rows of pixel electrodes, the scan line being connected to a gate of a drive transistor to which one of the rows of pixel electrodes is connected.

5. The display panel according to claim 4, wherein at least one side of the edges of the plurality of pixel electrodes is provided with at least one set of dummy signal lines in a column direction, each set of dummy signal lines includes two dummy signal lines, a sum of the number of the scan lines and the number of the dummy signal lines is an integer multiple of 8, and the scan line closest to the edges of the plurality of pixel electrodes in the column direction inputs the first clock signal.

6. The display panel according to claim 5, wherein the number of the scan lines is an even number, and when a remainder of dividing the number of the scan lines by 8 is greater than 4, a plurality of groups of the dummy signal lines are disposed outside the plurality of pixel electrodes in the column direction, and the plurality of groups of the dummy signal lines are distributed on one side or both sides of the plurality of pixel electrodes in the column direction.

7. The display panel according to claim 6, wherein when a plurality of sets of dummy signal lines are distributed on both sides of the plurality of pixel electrodes in the column direction, a part of the dummy signal lines are located outside a first side of the plurality of pixel electrodes and another part of the dummy signal lines are located outside a second side of the plurality of pixel electrodes, the second side being disposed opposite to the first side in the column direction, and the number of sets of the dummy signal lines outside the plurality of pixel electrodes is equal or unequal.

8. The display panel according to claim 5, wherein a plurality of the scan lines scan in the column direction in order from the first side to the second side, or a plurality of the scan lines scan in the column direction in order from the second side to the first side.

9. The display panel according to claim 5, wherein two of the dummy signal lines in each group of dummy signal lines are located on the same straight line in a row direction.

10. A display device comprising the display panel according to any one of claims 1 to 9.