CN117377311A - Memory structure - Google Patents

Abstract

The present disclosure provides a memory structure comprising: the semiconductor device comprises a substrate, a first grid structure, a second grid structure, a third grid structure and a plurality of channel bodies. The first gate structure, the second gate structure and the third gate structure are arranged on the substrate, are separated from each other along the first direction and extend along the second direction and the third direction respectively. The first gate includes a first island structure, a second island structure, and a third island structure extending along a third direction and separated from each other along a second direction, respectively, and the third gate includes a fourth island structure, a fifth island structure, and a sixth island structure extending along the third direction and separated from each other along the second direction, respectively. The channel bodies are separated from each other and pass through the first gate structure, the second gate structure and the third gate structure along the first direction.

Description

Memory structure

Technical Field

The present disclosure relates to semiconductor structures, and more particularly, to memory structures.

Background

In conventional DRAM (Dynamic random access memories; DRAMs), each bit of data requires a transistor (1T) and a capacitor (1C) to process, i.e., a 1T1C DRAM. However, in order to meet the market demand, the size of the memory structure needs to be smaller and smaller, and the 1t1c DRAM also faces more challenges such as leakage current, complex process and increased cost.

Accordingly, the structure of conventional DRAM is still further optimized to reduce the size of the memory structure while maintaining the performance of the memory structure.

Disclosure of Invention

The present disclosure relates to a thyristor-based memory architecture for operating machines with the advantages of high scalability and fast operating speeds.

According to an embodiment of the present disclosure, there is provided a memory structure including: a substrate, a first gate structure, a second gate structure, a third gate structure and a plurality of channel bodies. The substrate has an upper surface. The first gate structure, the second gate structure and the third gate structure are arranged on the substrate, are separated from each other along a first direction and extend along a second direction and a third direction respectively. The first direction, the second direction and the third direction are staggered with each other. The second gate structure is disposed between the first gate structure and the third gate structure, the first gate structure comprises a first island structure, a second island structure and a third island structure, the third gate structure comprises a fourth island structure, a fifth island structure and a sixth island structure, and the first island structure, the second island structure and the third island structure extend along the third direction respectively and are separated from each other along the second direction. The fourth island structure, the fifth island structure, and the sixth island structure extend along the third direction, respectively, and are separated from each other along the second direction. The channel bodies are separated from each other and pass through the first gate structure, the second gate structure and the third gate structure along the first direction.

For a better understanding of the above and other aspects of the disclosure, reference is made to the following detailed description of embodiments, which is to be taken in conjunction with the accompanying drawings.

Drawings

FIG. 1 is a schematic diagram illustrating a memory structure according to an embodiment of the disclosure;

FIGS. 2-18 illustrate the results of operating the memory structure of FIG. 1 by a thyristor (thyristor) machine turn;

FIG. 19 is a schematic perspective view of a memory structure according to another embodiment of the disclosure;

FIG. 20 is an equivalent circuit diagram of a memory structure according to another embodiment of the present disclosure;

FIG. 21 is a band diagram showing the "PGM" state and the "ERS" state of a memory structure based on thyristor-operated machine turning operations;

fig. 22 to 24 show experimental results of the memory structure based on the thyristor-operated machine operation.

Description of the drawings:

10, 20: a memory structure;

100, 200: a substrate;

100a,200a: an upper surface;

100d,120d,300d,320d: a region;

112, 212, 312: a first gate structure;

114, 214, 314: a second gate structure;

116, 216: a third gate structure;

120, 220, 320: a channel body;

120a,220a: a first end;

120b,220b: a second end;

122, 222: a dielectric film;

132: a first plug;

134: a second plug;

136: a third plug;

140, 240: a first side plug;

250: a second side plug;

2121: a first island structure;

2122: a second island structure;

2123: a third island structure;

2161: a fourth island structure;

2162: a fifth island structure;

2163: a sixth island structure;

BP: a second side pad;

BL: a bit line;

BL1: a first bit line;

BL2: a second bit line;

BR1: an electron barrier;

BR2: a hole barrier;

CA, CB, CS: a storage unit;

CP: a first side pad;

e1: a first state;

e2: a second state;

e3: a third state;

ec: conduction band

Ev: a valence band;

FWD: forward bias;

h1 H2, H3: height of the steel plate;

HW: a hysteresis window;

LR1: a first landing zone;

LR2: a second landing zone;

LR3: a third landing zone;

MA: a memory array region;

PW1, PW2: pulse width;

r1 to R4: a landing zone;

read: a read mode of operation;

RIW: a read current window;

SA: a stepped region;

CSL: sharing a source line;

TA1 to TA3, TB1 to TB3, TS1 to TS3: a transistor;

ERS: an erase operation mode;

PGM: a programming mode of operation;

REV: reverse bias;

WD11, WD12, WD13, WD2, WD31, WD32, WD33: width of the material.

Detailed Description

Related embodiments are provided below to describe in detail the memory structure provided by the present disclosure with reference to the accompanying drawings. However, the disclosure is not limited thereto. The description of the embodiments, such as the details of the structure, the steps of the manufacturing method, and the application of materials, is for illustrative purposes only, and the scope of the present disclosure is not limited to the described aspects.

Also, it should be noted that the present disclosure does not show all possible embodiments. Variations and modifications in the construction and method of manufacture of the embodiments may occur to those skilled in the relevant art without departing from the spirit and scope of the disclosure as desired for practical use. Thus, other implementations not proposed by the present disclosure may also be applicable. Furthermore, the drawings are simplified to clearly illustrate the contents of the embodiments, and the dimensional proportions on the drawings are not drawn to scale for actual products. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense. The same or similar reference numerals are used to denote the same or similar elements.

To meet the demand for miniaturization in size, various alternatives to capacitor-less DRAM (capacitor-less DRAM) have been studied in the art. For example, a one-transistor DRAM (1T DRAM) has been proposed. A conventional 1T DRAM is composed of a single MOSFET fabricated on a partial SOI substrate, which utilizes a floating body effect (floating body effect) to generate excess holes by impact ionization (impact ionization) and store them in a neutral body, which state is defined as a logic "1". On the other hand, when the cavity is positively biased to sweep out the neutral body, the cavity is in a logic "0" state. After that, a Thyristor RAM (TRAM) is proposed, which exploits the bistable nature of PNPN thyristors without applying a large bias to induce impact ionization as in a typical 1T DRAM.

The memory architecture provided by the present disclosure is an architecture derived from 1T DRAM operation, performing optimized TRAM operations. Compared to a typical 1T DRAM, a memory structure and operation according to the present disclosure may have a high current (e.g., 60 μA) sense margin between the logic "1" and logic "0" states. The pulse width can be shortened (e.g., 50 ns) without decreasing the window. The retention time (retention time) of room temperature may be high (e.g., up to 3 seconds), and the read-free-disturb time (read-free time) may be increased (e.g., up to 2 seconds). These characteristics turn the memory structure of the present disclosure and its operating machine into promising DRAM candidates with high scalability and fast operating speed.

The present disclosure provides a three-dimensional memory structure including 3 transistors (3T) (as shown in memory structures 10 and 20 of fig. 1 and 19) for 3D DRAM characteristics and thyristor operation.

Fig. 1 is a schematic perspective view of a memory structure 10 according to an embodiment of the disclosure. In the present embodiment, the Z direction indicates a first direction, the Y direction indicates a second direction, and the X direction indicates a third direction, as shown in fig. 1. The first direction, the second direction and the third direction are staggered, for example, perpendicular, i.e., the Z direction, the Y direction and the X direction may be perpendicular.

Referring to fig. 1, the memory structure 10 includes a substrate 100, a first gate structure 112, a second gate structure 114, a third gate structure 116, a plurality of channel bodies 120, a plurality of dielectric films 122, a first plug 132, a second plug 134, a third plug 136 and a first side plug 140. The substrate 100 has an upper surface 100a, the upper surface 100a is parallel to the second direction (e.g. Y direction) and the third direction (e.g. X direction), and the normal direction of the upper surface 100a is parallel to the first direction (e.g. Z direction). A dopant may be implanted in the region 100D of the substrate 100 adjacent to the upper surface 100 a. In one embodiment, the region 100D of the substrate 100 adjacent to the upper surface 100a has a first conductivity type, such as N-type (n+), with high concentration doping. The region 100D in the substrate 100 may serve as a common source line.

The first gate structure 112, the second gate structure 114 and the third gate structure 116 are disposed on the substrate 100, sequentially stacked along a first direction (e.g. Z direction) and separated from each other, and respectively extend along a second direction (e.g. Y direction) and a third direction (e.g. X direction), wherein the second gate structure 114 is disposed between the first gate structure 112 and the third gate structure 116, and some insulating materials are omitted in fig. 1 for brevity of drawing, for example, insulating materials between the substrate 100, the first gate structure 112, the second gate structure 114 and the third gate structure 116 are omitted. In some embodiments, the first gate structure 112, the second gate structure 114, and the third gate structure 116 may each be a word line.

The channel bodies 120 are separated from each other along a second direction (e.g., Y direction) and a third direction (e.g., X direction) and pass through the first gate structure 112, the second gate structure 114, and the third gate structure 116 along a first direction (e.g., Z direction) and extend to the substrate 100, e.g., the channel bodies 120 are electrically contacted with the substrate 100 to form a vertical channel structure. The channel body 120 forms a transistor with each intersection of each gate structure (i.e., the first gate structure 112, the second gate structure 114, and the third gate structure 116). Each channel body 120 has a first end 120A electrically contacting the upper surface 100A of the substrate 100 and a second end 120B remote from the upper surface 100A, and the second end 120B is opposite to the first end 120A. A dopant may be implanted in the channel body 120 in a region 120D adjacent to the second end 120B.

In this embodiment, for example, a thyristor (thyristor) is used as an operating element, and the region 120D of the channel body 120 adjacent to the second end 120B has a second conductivity type, for example, a P-type (p+) with a high concentration of dopant. Region 100D may function as a source and region 120D may function as a drain, although the disclosure is not limited thereto.

Dielectric films 122 are disposed between the first gate structure 112 and the channel body 120, between the second gate structure 114 and the channel body 120, and between the third gate structure 116 and the channel body 120. That is, the dielectric film 122 extends along a first direction (e.g., Z-direction) around the side surfaces of the channel body 120 to separate the first gate structure 112 and the channel body 120 from each other, separate the second gate structure 114 and the channel body 120 from each other, and separate the third gate structure 116 and the channel body 120 from each other.

The first gate structure 112, the second gate structure 114, and the third gate structure 116 surround each dielectric film 122 and each channel body 120, and are also referred to as gate-all-around (GAA) structures. Also, each channel body 120 may be controlled by 3 gates (i.e., first gate structure 112, second gate structure 114, and third gate structure 116).

The first side plug 140 extends along a first direction (e.g., Z direction) and a third direction (e.g., X direction) and is electrically contacted with the substrate 100. The first side plug 140 is electrically connected to the substrate 100 and the channel body 120, for example.

The substrate 100 corresponds to a memory array region MA and a step region SA, the channel body 120 is disposed in the memory array region MA, the step region SA is adjacent to the memory array region MA, and the first gate structure 112, the second gate structure 114 and the third gate structure 116 form a step structure in the step region SA, and expose a first landing region LR1, a second landing region LR2 and a third landing region LR3, respectively. A first plug 132, a second plug 134 and a third plug 136 are disposed on the first landing area LR1, the second landing area LR2 and the third landing area LR3, respectively, and extend along a first direction (e.g. Z direction) to electrically contact the first gate structure 112, the second gate structure 114 and the third gate structure 116, respectively.

In some embodiments, the substrate 100 may comprise a semiconductor substrate, such as a bulk silicon (bulk silicon) substrate. In this embodiment, the channel body 120 may be formed by a selective epitaxial growth (selective epitaxial growth) process, and the material of the channel body 120 may comprise monocrystalline silicon. During operation (e.g., programming or erasing) of the memory device 10, the channel body 120 can be used to store carriers (e.g., electrons or holes). The dielectric film 122 need not have a function of storing carriers (e.g., electrons or holes), so the dielectric film 122 does not include a charge storage structure (charge storage structure), such as an oxide-nitride-oxide (ONO) structure. In one embodiment, the material of the dielectric film 122 includes a dielectric material, such as an oxide, and the dielectric film 122 may have a single-layer structure. In one embodiment, the material of the dielectric film 122 may include a high-k material (high dielectric constant material). In an embodiment, the materials of the first plug 132, the second plug 134, the third plug 136, the first side plug 140, the first gate structure 112, the second gate structure 114, and the third gate structure 116 may include semiconductor materials or metal materials. In this embodiment, the first gate structure 112 may comprise polysilicon, and the second gate structure 114 and the third gate structure 116 may comprise metal, respectively. It should be understood that the materials of the above elements of the present disclosure are not limited thereto.

Fig. 2-18 illustrate the result of operating the memory structure 10 shown in fig. 1 by mechanical turning of thyristors.

FIG. 2 is a graph showing the relationship between the bit line bias and the bit line current (also referred to as drain current) in embodiments 1-4, wherein the X-axis represents the bit line bias in volts (V); the Y-axis represents bit line current in amperes (A). The solid curve represents the forward bias FWD (e.g., scanned from left to right) and the dashed curve represents the reverse bias REV (e.g., scanned from right to left). In embodiments 1-4, the second gate structure 114 and the third gate structure 116 are both applied with 3V, and the first gate structure 112 is applied with different voltages. The first gate structure 112 of example 1 is applied at-3V, the first gate structure 112 of example 2 is applied at-2.5V, the first gate structure 112 of example 3 is applied at-2V, and the first gate structure 112 of example 4 is applied at-1.5V.

As shown in fig. 2, examples 1 to 4 show hysteresis curves (hysteresis curves) respectively, with the forward bias FWD being scanned from 0V to 4V and then the reverse bias REV being scanned from 4V to 0V, and the distance between the solid curve and the dotted curve under the same bit line current represents the size of the hysteresis window (hysteresis window). The hysteresis windows of examples 1-4 have different sizes under the same bit line current, e.g., the hysteresis windows of examples 1-2 have smaller sizes than the hysteresis window HW of example 3 and the hysteresis window of example 4 has larger sizes than the hysteresis window HW of example 3 under bit line current adjacent to 10-8A. That is, by fixing the voltages of the second gate structure 114 and the third gate structure 116 and changing the voltage of the first gate structure 112, the size of the hysteresis window can be regulated, so that the operation effect of the thyristor can be achieved. By reading the voltage (e.g., 2V) within the hysteresis window, different current levels can be obtained, and thus a logical "1" can be distinguished from a logical "0".

In conventional thyristor operation, since there is only one gate, it is often necessary to use a complex doping structure to achieve the effect of adjusting the hysteresis window, for example, forming a plurality of doped regions of different conductivity types (N-type and P-type) in the memory structure (e.g., N/P/N/P structure). In contrast, in the thyristor operation of the embodiments of the present disclosure (e.g., embodiments 1-4), the hysteresis curve needs to be adjusted by applying different gate biases only, the size of the hysteresis window is controlled, and no complex doping structure needs to be formed.

Fig. 3 shows simulation results of band diagrams (band diagnostics) of the first state E1, the second state E2, and the third state E3 of the embodiment 3 shown in fig. 2, for example, the simulation results are observed through computer simulation using a scientific computer aided design (Technology Computer Aided Design, TCAD) tool. In fig. 3, the X-axis represents the position between the region 100D and the region 120D (for example, the schematic diagram of the elements such as the region 100D and the region 120D shown in the uppermost part of fig. 3) in micrometers (μm); the Y-axis represents energy in electron volts (eV). "Ec" means a conduction band (conduction band). "Ev" means valance band (valance band).

Referring to fig. 2 and 3, the bias voltages of the first gate structure 112 in the first state E1 to the third state E3 are all-2V, the bias voltages of the second gate structure 114 are all 3V, and the bias voltages of the third gate structure 116 are all 3V. The first state E1 is a high-resistance state, the bit line bias is 2.3V, the electron barrier BR1 and the hole barrier BR2 are both relatively high, electrons cannot cross the electron barrier BR1, and holes cannot cross the hole barrier BR2.

The second state E2 is a low resistance state and the bit line bias is 3.5V. When the bit line bias voltage is gradually increased from the first state E1 to the second state E2, the hole potential barrier BR2 is gradually decreased, so that a part of holes can flow to the inside of the channel body 120 beyond the potential barrier, and thus the electron potential barrier BR1 is also decreased, so that a part of electrons can flow to the inside of the channel body 120 beyond the electron potential barrier BR1, and similarly, a part of electrons can flow to the inside of the channel body 120 to decrease the hole potential barrier BR2. Thus, positive feedback (positive feedback) is formed, so that the electron barrier BR1 and the hole barrier BR2 are influenced and gradually reduced, and more electrons and holes can flow into the channel body 120, so that the electron barrier BR1 and the hole barrier BR2 are hardly present in the second state E2, have a large current, and induce latch-up.

The third state E3 is also a low resistance state with a bit line bias of 2.3V. When the second state E2 is changed from the third state E3, the voltages of the first gate structure 112 to the third gate structure 116 are not changed, and only the bit line bias is changed, so that the electron barrier BR1 and the hole barrier BR2 are still almost absent, and a large current is still maintained in the third state E3, and the latch-up effect is still maintained.

Different biases listed in table 1 below may be applied to the first gate structure 112, the second gate structure 114, the third gate structure 116, the region 120D (which is equipotential with the bit line BL) and the region 100D (which is equipotential with the source line SL) as shown in fig. 1 to perform different operation modes, such as programming, erasing or reading operation modes. In this embodiment and the accompanying drawings, "PGM" is an abbreviation for programming operation mode, representing an operation mode that programs the storage of the memory structure 10 to an information state of "1" (i.e., to a logic "1"); "ERS" is an abbreviation for erase mode of operation, representing the mode of operation that programs the storage of memory structure 10 to an information state of "0" (i.e., to a logic "0"); "Read" is an abbreviation for Read mode of operation, which refers to a mode of operation in which the storage of the memory structure 10 is Read to confirm the state of the individually stored voltage information.

TABLE 1

FIG. 4 shows the experimental results of the program/erase cycle (P/E cycle) showing the waveforms of the voltage-operated memory structure 10 according to Table 1.

Referring to both table 1 and fig. 4, in "PGM", the voltage applied to the first gate structure 112 is less than 0 (e.g., -2V), the voltage applied to the second gate structure 114 and the third gate structure 116 is greater than 0 (e.g., 3V), and a large bit line bias (e.g., 3V) induces a thyristor latch-up, so that the memory structure 10 starts to assume a low resistance state. In "ERS", in order to suppress the latch-up effect, a reset gate voltage is required, so voltages (i.e., word line bias voltages) applied to the first gate structure 112, the second gate structure 114, and the third gate structure 116 are restored to 0V, and a bit line BL bias voltage of 0V is applied. Thereafter, the voltages applied to the word lines (i.e., first gate structure 112, second gate structure 114, and third gate structure 116) may be increased to return the memory structure 10 to the high-power state. Through the above-described operations, a cycle of "PGM" → "Read" → "ERS" → "Read" as shown in fig. 4 can be formed. The "PGM" and "ERS" states have pulse widths PW1 and PW2, respectively.

FIG. 5 shows the measurement results of the source current under different states.

Referring to fig. 5, the x-axis represents time in microseconds (μs); the Y-axis represents source current in microamperes (μA). The read current window (read current window) RIW between the "PGM" state and the "ERS" state can be greater than 60 microamps. This large read current window may be attributed to a large hysteresis window.

FIG. 6 is a graph showing the relationship between the source current variation and the pulse width.

Referring to fig. 6, the x-axis represents pulse width in nanoseconds (ns); the Y-axis represents source current variation (i.e., current window) in microamperes (μA). Even if the pulse width drops to 50 nanoseconds (measurement limit), the sensing boundary (sensing margin) of the current window of 60 microamps can be preserved.

FIG. 7 shows tolerance (tolerance) according to an embodiment A of the present disclosure. Fig. 8 shows the energy band diagrams of the PGM state and ERS state of example a. FIG. 9 shows the tolerance (tolerance) according to comparative example A. Fig. 10 is a schematic diagram showing electron/hole transport states of the "PGM" state and the "ERS" state of comparative example a.

Embodiment a may be applied to a memory structure 10 as shown in fig. 1, with thyristors as operating mechanism. The difference between the comparative example a and the example a is that the region 120D' serving as the drain electrode and the region 100D serving as the source electrode in the comparative example a have the same first conductivity type and also have the N type (n+) doped with high concentration, for example, the floating body cell (floating body cell) is used as the operation machine.

Referring to FIG. 7, the X-axis represents the number of P/E cycles, and the Y-axis represents the read current in microamperes (μA). In the operation of the P/E cycle, since the present disclosure does not operate using hot carriers (hot carrier), the memory structure of the present disclosure is not damaged by hot carriers, and has superior tolerance compared to the comparative example (e.g., comparative example a) operating using hot carriers, there is no difference in the P/E cycle of the read current in the "PGM" state and the "ERS" state up to 1010.

Referring to fig. 8, in the PGM operation, for example, 0V is applied to the region 100D and 3V is applied to the region 120D, the positive feedback can be used to reduce or eliminate the electron barrier and the hole barrier, and no hot carrier operation is involved. Since the potential barrier is removed, electrons and holes can move toward the middle of the channel body 120. In order to recover the electron barrier and the hole barrier in the "ERS" operation, for example, 0V is applied to the region 100D, 0V is applied to the region 120D, and voltages are applied to the first gate structure 112 to the third gate structure 116 in the manner described in table 1, and the hot carrier operation is not involved. Since the potential barrier is established, electrons and holes cannot move toward the channel body 120.

Referring to FIG. 9, the X-axis represents the number of P/E cycles, and the Y-axis represents the read current in microamperes (μA). In the operation of the P/E cycle, the memory structure is more easily damaged by the hot carrier because the floating body unit is used as the operation machine in the comparative example A to operate by using the hot carrier. For example, in the operation of "PGM", comparative example a generates holes with band-to-band tunneling (band to band tunneling), which are stored in the channel body 120. However, in the "PGM" state, the P/E cycle drops rapidly when the read current is still not yet 103, and it can be seen that the tolerance of comparative example a is significantly poorer than that of example a.

Referring to fig. 10, in the "PGM" operation, for example, 1V is applied to the third gate structure 116 and 5V is applied to the region 120D' to generate holes (i.e., hot carriers) by band-to-band tunneling machine and to create interface traps (interface traps) Tr. As such, the electric field (electric field) decreases, and the read current of comparative example a in the "PGM" state is smaller than that of example a in the "PGM" state. In an "ERS" operation, for example, 4V is applied to the third gate structure 116 and-5V is applied to the region 120D', so that holes stored in the channel body 120 are moved out of the channel body 120.

Fig. 11-13 illustrate a hold state of a memory structure (e.g., memory structure 10) according to an embodiment of the present disclosure for a thyristor-based operator.

The operation mode of the memory structure 10 may further include a Hold operation, which is an abbreviation of a Hold operation, representing an operation mode for maintaining a stored voltage information state of the memory structure 10.

Referring to fig. 11, a graph of time and voltage of the bit line BL, the first gate structure 112, the second gate structure 114 and the third gate structure 116 in different states is shown. "Hold" may be performed after "PGM" or "ERS" is completed, and "Read" may be performed after "Hold" is completed. In operation "Hold", different voltages may be applied to the first gate structure 112 to the third gate structure 116 to maintain the "PGM" or "ERS" state, for example, -2.5V may be applied to the first gate structure 112, -1V to the second gate structure 114, 3V to the third gate structure 116, and 0V to the bit line BL.

Referring to fig. 12, which shows a graph of the sustain time of "PGM" and "ERS" at normal temperature versus the read current, the X-axis represents the sustain time in seconds (sec); the Y-axis represents read current in microamperes (μA). For example, at normal temperature, the difference in read current between "PGM" and "ERS" can still be maintained at 40 microamps when the holding time is 3 seconds, as shown by double arrow (double arrow) in fig. 12.

Referring to FIG. 13, a graph showing the relationship between the sustain time and the read current of "PGM" and "ERS" at 85 ℃ is shown, wherein the X-axis represents the sustain time in seconds (sec); the Y-axis represents read current in microamperes (μA). For example, at 85 ℃, the difference in read current between "PGM" and "ERS" can still be maintained at 60 microamps when the maintenance time is 10 "1 seconds (i.e., 100 ms), as shown by the double arrow of fig. 13.

As can be seen from the results of fig. 12 to 13, the memory structure of the present disclosure can have a reasonable retention time (e.g., 3s or 100 ms) no matter at normal temperature or 85 ℃ as long as a proper retention bias is applied, which is superior to the DRAM (retention time is, for example, 64 ms) used in the prior art.

Fig. 14-18 illustrate the results of read disturb (read disturb) of a memory structure (e.g., memory structure 10) in accordance with an embodiment of the present disclosure for a thyristor-based operator. Read disturb can be used to detect how long the Read time can be maintained during "Read" and the data (data) is not corrupted.

In general, 1T1C DRAM as currently used in the art is a destructive Read, i.e., the state disappears after the "Read" is completed, requiring a re-write.

Referring to FIG. 14, a memory structure of the present disclosure is shown in which data can be repeatedly Read (e.g., 7 consecutive times of "Read") without re-writing, which proves that the memory structure of the present disclosure belongs to non-destructive Read (non-destructive Read).

Referring to FIG. 15, the results of consecutive reads after "PGM" and "ERS" are shown, for example, to extend the time of "Read" to measure how long "Read" can be maintained in the case where data is still present.

Referring to FIG. 16, a graph showing the relationship between the Read time and the Read current of "PGM" and "ERS" when the Read voltage (Read VBL) of the bit line is 2.5V is shown, wherein the X-axis represents the Read time in seconds (sec); the Y-axis is the read current in microamperes (μA). When the read time is 10-3 seconds (i.e., 1 ms), the read current difference between "PGM" and "ERS" is maintained at 65 microamps, as shown by the double arrow in fig. 16. When the read time is greater than 1ms, the current of "ERS" rises rapidly and increases to the same current as "PGM" due to positive feedback.

Referring to FIG. 17, a graph showing the relationship between the read time and the read current of "PGM" and "ERS" when the read voltage of the bit line is 2.1V is shown, wherein the X-axis represents the read time in seconds (sec); the Y-axis is the read current in microamperes (μA). When the read time was 2 seconds, the read current difference between "PGM" and "ERS" remained at 33 microamps, as shown by the double arrow of fig. 17. When the read time is greater than 2 seconds, the current of "ERS" rises rapidly and increases to the same current as "PGM" due to positive feedback. Although the read current difference between "PGM" and "ERS" is smaller in the embodiment of fig. 17 compared to the embodiment of fig. 16, the read time may be maintained longer.

Referring to FIG. 18, a band diagram of the read voltages of the bit lines in the ERS state of embodiment B and embodiment C is shown. The structures of embodiment B and embodiment C are the same as that of embodiment A, but the read voltages of the bit lines of embodiment B and embodiment C are different. In embodiment B, the read voltage of the bit line is 2.5V. In embodiment C, the read voltage of the bit line is 2.1V. As shown in fig. 18, the lower read voltage of the bit line (i.e., embodiment C) can raise the hole barrier, and the leakage current is less likely to occur due to the crossing of the hole barrier, so that the time for positive feedback can be delayed.

Therefore, if the read-free time is to be extended, the read voltage of the bit line can be reduced, so that the probability of inducing positive feedback in ERS is reduced.

Fig. 19 is a schematic perspective view of a memory structure 20 according to another embodiment of the disclosure. In the present embodiment, the Z direction indicates the third direction, the Y direction indicates the second direction, and the X direction indicates the first direction, as shown in fig. 19.

Referring to fig. 19, the memory structure 20 includes a substrate 200, a first gate structure 212, a second gate structure 214, a third gate structure 216, a plurality of channel bodies 220, a plurality of dielectric films 222, a first side plug 240, a second side plug 250, a first side pad CP and a second side pad BP. The substrate 200 has an upper surface 200a, the upper surface 200a is parallel to a first direction (e.g. X direction) and a second direction (e.g. Y direction), and a normal direction of the upper surface 200a is parallel to a third direction (e.g. Z direction).

The first gate structure 212, the second gate structure 214, and the third gate structure 216 are disposed on the substrate 200 along a first direction (e.g., an X direction), are separated from each other along the first direction (e.g., the X direction), and extend along a second direction (e.g., a Y direction) and a third direction (e.g., a Z direction), respectively, wherein the second gate structure 214 is disposed between the first gate structure 212 and the third gate structure 216, and the first direction, the second direction and the third direction are staggered with each other, e.g., perpendicular to each other, i.e., the Z direction, the Y direction and the X direction may be perpendicular to each other. The first gate 212 includes a first island 2121, a second island 2122, and a third island 2123 that are separated from each other, and the third gate 216 includes a fourth island 2161, a fifth island 2162, and a sixth island 2163 that are separated from each other. The first island 2121, the second island 2122, and the third island 2123 extend along a third direction, and are separated from each other along the second direction, respectively; the fourth, fifth and sixth island structures 2161, 2162, 2163 respectively extend along the third direction and are separated from each other along the second direction. Further, the first island 2121, the second island 2122, and the third island 2123 are each independently controlled; the fourth island 2161, the fifth island 2162, and the sixth island 2163 are each independently controlled.

In an embodiment, a height H1 of the first island 2121, the second island 2122, or the third island 2123 in the third direction is equal to a height H2 of the second gate structure 214 in the third direction, and a width WD11, WD12, or WD13 of the first island 2121, the second island 2122, or the third island 2123 in the second direction is smaller than a width WD2 of the second gate structure 214 in the second direction. The height H3 of the fourth, fifth, or sixth island-like structures 2161, 2162, or 2163 in the third direction is equal to the height H2 of the second gate structure 214 in the third direction, and the width WD31, WD32, or WD33 of the fourth, fifth, or sixth island-like structures 2161, 2162, or 2163 in the second direction is less than the width WD2 of the second gate structure 214 in the second direction, although the disclosure is not limited thereto. For simplicity, some insulating materials, such as insulating materials between the substrate 200, the first gate structure 212, the second gate structure 214, and the third gate structure 216, insulating materials between the first island 2121, the second island 2122, and the third island 2123, and insulating materials between the fourth island 2161, the fifth island 2162, and the sixth island 2163 are omitted in fig. 19. The width WD11, WD12, or WD13 of the first island 2121, the second island 2122, or the third island 2123 in the second direction may be equal to the width WD31, WD32, or WD33 of the fourth island 2161, the fifth island 2162, or the sixth island 2163 in the second direction. In some embodiments, the first gate structure 212, the second gate structure 214, and the third gate structure 216 may each be a word line.

The channel bodies 220 are separated from each other along a second direction (e.g., Y-direction) and a third direction (e.g., Z-direction) and pass through the first gate structure 212, the second gate structure 214, and the third gate structure 216 along a first direction (e.g., X-direction), that is, the extending direction of the channel bodies 220 is parallel to the upper surface 200a of the substrate 200, forming a horizontal channel structure. Each channel body 220 has a first end 220A and a second end 220B, the first end 220A is adjacent to the first gate structure 212 and is distant from the third gate structure 216, the second end 220B is adjacent to the third gate structure 216 and is distant from the first gate structure 212, and the second end 220B is opposite to the first end 220A.

The first side pads CP are stacked along a third direction (e.g., Z-direction) and separated from each other along the third direction (e.g., Z-direction), and each of the first side pads CP is connected to a corresponding first end 220A in the channel body 220. The second side pads BP are stacked along a third direction (e.g., Z-direction) and separated from each other along the third direction (e.g., Z-direction), and each of the second side pads BP is connected to a corresponding second end 220B in the channel body 220. The dopants may be implanted into the first and second side pads CP and BP.

In this embodiment, a thyristor (thyristor) is used as an operating machine, the first side pad CP has a first conductivity type, for example, N-type (n+) with high-concentration doping, and the second side pad BP has a second conductivity type, for example, P-type (p+) with high-concentration doping.

In one embodiment, the first side pad CP may serve as a source and the second side pad BP may serve as a drain, but the disclosure is not limited thereto.

Dielectric films 222 are disposed between the first gate structure 212 and the channel body 220, between the second gate structure 214 and the channel body 220, and between the third gate structure 216 and the channel body 220. That is, the dielectric film 222 extends along a first direction (e.g., X-direction) around the side surfaces of the channel body 220 to separate the first gate structure 212 and the channel body 220 from each other, separate the second gate structure 214 and the channel body 220 from each other, and separate the third gate structure 216 and the channel body 220 from each other. In one embodiment, the dielectric films 222 surrounding the different channel bodies 220 are connected to each other, and extend along the second direction (e.g., Y direction) and the third direction (e.g., Z direction), covering the first gate structure 212, the second gate structure 214, and the third gate structure 216 (not shown).

The first gate structure 212, the second gate structure 214, and the third gate structure 216 surround each dielectric film 222 and each channel body 220, and also extend into the space between the channel bodies 220 adjacent to each other along the second direction (e.g., Y-direction) and the third direction (e.g., Z-direction). Since the first, second and third gate structures 212, 214 and 216 surround the entire side surfaces of the corresponding positions of the channel body 220 (i.e., the crossing positions between the first, second and third gate structures 212, 214 and 216 and the channel body 220), they are also called gate-all-around (GAA) structures. Also, each channel body 220 may be controlled by 3 gates (i.e., first gate structure 212, second gate structure 214, and third gate structure 216). Specifically, the channel body 220 corresponding to the first island 2121 may be controlled by the first island 2121, the second gate 214, and the fourth island 2161, the channel body 220 corresponding to the second island 2122 may be controlled by the second island 2122, the second gate 214, and the fifth island 2162, and the channel body 220 corresponding to the third island 2123 may be controlled by the third island 2123, the second gate 214, and the sixth island 2163. The intersection of the channel body 220 with each gate structure forms a transistor.

The first side plug 240 extends along a second direction (e.g., Y direction) and a third direction (e.g., Z direction), and is electrically contacted to the substrate 200 and the first side pad CP. The first side plug 240 is electrically connected to the substrate 200 and the channel body 220, for example.

The second side plugs 250 are separated from each other along a second direction (e.g., Y direction), and extend along a third direction (e.g., Z direction) to electrically contact the plurality of landing areas R1 to R4 on the second side pads BP, respectively. In the present embodiment, the height of the second side plug BP in the third direction (e.g. Z direction) increases gradually along the second direction (e.g. Y direction), and the landing areas R1 to R4 form a step-like structure, but the disclosure is not limited thereto. The top of the second side plugs 250 may be connected to a bit line (not shown), respectively. The second, different, side plugs 250 are connected to different bit lines (not shown). That is, the same level of channel bodies 220 may be electrically connected to the same second side plug 250 and corresponding bit line (not shown). The number of the second side plugs 250 may be the same as the number of the first side pads CP, the channel body 220, and the second side pads BP along the third direction (e.g., the Z direction), respectively, for example, 4, but the disclosure is not limited thereto. For example, in other embodiments, the number of second side plugs 250, the number of first side pads CP along the third direction (e.g., Z direction), the channel body 220, and the second side pads BP may be greater than 4.

In some embodiments, the substrate 200 may comprise a semiconductor substrate, such as a bulk silicon (bulk silicon) substrate. In this embodiment, the channel body 220 may be formed by an epitaxial growth (epi) process, and the material of the channel body 220 may include monocrystalline silicon. During operation (e.g., programming or erasing) of the memory device 20, the channel body 220 can be used to store carriers (e.g., electrons or holes). The dielectric film 222 need not have a function of storing carriers (e.g., electrons or holes), so the dielectric film 222 does not include a charge storage structure, such as an oxide-nitride-oxide (ONO) structure. In other words, no ONO structure is present in the space between the channel body 220 and the gate structures (i.e., the first gate structure 212, the second gate structure 214, and the third gate structure 216). In one embodiment, the material of the dielectric film 222 includes a dielectric material, such as an oxide, and the dielectric film 222 may have a single-layer structure. In one embodiment, the material of the dielectric film 222 may include a high-k material (high dielectric constant material). In one embodiment, the materials of the first side plug 240, the second side plug 250, the first side pad CP, the second side pad BP, the first gate structure 212, the second gate structure 214, and the third gate structure 216 may comprise a semiconductor material or a metal material. For example, the first side pad CP, the second side pad BP, the first gate structure 212, the second gate structure 214, and the third gate structure 216 may include monocrystalline silicon or polycrystalline silicon or metal. It should be understood that the materials of the above elements of the present disclosure are not limited thereto.

According to some embodiments, the memory structure 20 may be formed by a stacked gate full-ring nanoplate metal oxide semiconductor process (stacked gate-all-around nanosheet CMOS process). The memory structure 20 with horizontal channels may stack more layers of channel bodies 220 than the memory structure 10 with vertical channels, so that more bits may be formed, having a higher storage density, which is advantageous for the miniaturization of the size of the memory structure.

In a comparison example B (not shown), the first gate structure 212 has the same shape as the second gate structure 214 (i.e., the first gate structure 212 does not include the first island 2121, the second island 2122, and the third island 2123), and the other structures of the comparison example B are the same as the memory structure 20 (i.e., the third gate structure 216 also includes the fourth island 2161-the sixth island 2163). Compared to comparative example B (not shown), since the memory structure 20 of the present disclosure includes the separated island-like structures in both the first gate structure 212 and the third gate structure 216, the control effect is better and the electrical characteristics are better when the operation of the memory structure is performed by the thyristor machine. For example, in one embodiment of the present disclosure, the island structure of the first gate structure 212 and the third gate structure 216, which are both separate, can provide a more flexible write and erase voltage operation design, which can help to raise the memory window between the "1" and "0" states, while also helping to suppress leakage current from non-selected memories.

Fig. 20 is an equivalent circuit diagram of a memory structure 20 according to another embodiment of the present disclosure.

Referring to fig. 19 and 20, fig. 20 schematically illustrates 4 adjacent channel bodies 220 in fig. 19, for example, each crossing position of the channel body 220 and the first island 2121 and the second island 2122 in the first gate structure 212, and each crossing position of the fourth island 2161 and the fifth island 2162 in the second gate structure 214 and the third gate structure 216 form a transistor. As shown in fig. 20, the transistors TA1, TA2 and TA3 connected by the same channel body 220 form a memory cell CA; transistors TB1, TB2 and TB3 connected through the same channel body 220 commonly form a memory cell CB; the transistors TS1, TS2 and TS3 connected through the same channel body 220 commonly form a memory cell CS. The first end 220A of the channel body 220 is connected to the corresponding first side pad CP, and the first side pads CP of different layers are electrically connected to a first side plug 240 and electrically connected to the source line, so that the memory cells CA, CB and CS are connected to the common source line CSL (i.e. are at the same potential). The second end 220B of the channel body 220 is connected to the corresponding second side pad BP, the second side pads BP of different levels are electrically contacted to the second side plugs 250, and the second side plugs 250 are electrically connected to different bit lines, for example, the memory cells CB and CS of the same level are electrically connected to the first bit line BL1. The memory cell CA is electrically connected to the second bit line BL2. The memory cells CA, CB, and CS share the second gate structure 214. Memory cells CA and CS share a second island 2122 in first gate structure 212 and a fifth island 2162 in third gate structure 216.

In this embodiment, the memory cell CS is a memory cell to be selected, and the other memory cells CA and CB are unselected memory cells (for example, suppressed memory cells). In other words, the memory cell CS corresponds to the selected second island 2122, the selected second gate 214, and the selected fifth island 2162, and is electrically connected to the selected first bit line BL1. The unselected memory cells CB may correspond to the unselected first island 2121 and the unselected fourth island 2161. The second bit line BL2 is an unselected bit line. Also, different bias voltages may be applied to the first island 2121, the second island 2122, the second gate structure 214, the fourth island 2161, the fifth island 2162, the first bit line BL1, the second bit line BL2, and the common source line CSL according to the following Table 2, for example, the operation modes of "PGM", "ERS", or "Read" similar to those described in the relevant paragraphs of Table 1.

TABLE 2

Fig. 21 shows band diagrams of the "PGM" state and the "ERS" state of the thyristor-operated machine operated memory structure 20.

Referring to fig. 21, in the PGM operation, for example, 0V is applied to the first side pad CP and 3V is applied to the second side pad BP, the positive feedback can be used to reduce or eliminate the electron barrier and the hole barrier, and no hot carrier operation is involved. Since the potential barrier is removed, electrons and holes can move toward the middle of the channel body 220. In order to recover the electron barrier and the hole barrier in the "ERS" operation, for example, 0V is applied to the first side pad CP, 0V is applied to the second side pad BP, and voltages are applied to the first gate 212 to the third gate 216 in the manner described in table 2, and the hot carrier operation is not involved. Since the potential barrier is established, electrons and holes cannot move toward the channel body 220.

Fig. 22 to 24 show experimental results of operating the memory structure 20 based on the thyristor-operated machine.

Referring to fig. 22, the x-axis represents programming time in microseconds (μs); the Y-axis represents read current in microamperes (μA). In the "PGM" operation, the selected memory cell CS has a large current, and the unselected memory cells CA and CB are suppressed without a current.

Referring to fig. 23, the x-axis represents erase time in microseconds (μs); the Y-axis represents read current in microamperes (μA). After the "ERS" operation is performed, the selected memory cell CS has no current, and the unselected memory cells CA and CB maintain a large current.

It can be seen that the memory cell CS can be selected reliably and the memory cells CA and CB can be suppressed, regardless of whether "PGM" or "ERS".

Referring to fig. 24, the x-axis represents the bias voltage of the third gate structure 216 in volts (V); the Y-axis represents the read current in microamperes (μA) for the "PGM" state. In "Read," 2V is applied to the first gate structure 212, 3V is applied to the second gate structure 214, and 2.5V is applied to the first bit line BL1. After the "Read" operation, since the selected memory cell CS and the unselected memory cell CB are connected to the same bit line (i.e., the first bit line BL 1), the memory cell CB must be turned off to avoid the contribution of current by the memory cell CB, otherwise, a leakage current is generated, and a sneak path is formed. Therefore, a sufficiently high bias voltage (e.g., greater than 4.5V, as indicated by the arrow, e.g., 5V) must be applied to the unselected third gate structures 216 (e.g., fourth island structures 2161) to avoid the formation of a potential via and to properly read the selected memory cell CS.

According to an embodiment of the present disclosure, the first gate structure and the third gate structure of the memory structure have 3 island structures, and the memory structure of the present disclosure is operated by the operation machine of the thyristor, so that it can be found that the memory structure of the present disclosure has high expandability and fast operation speed, and various electrical characteristics are better than those of the DRAM in the present technical field.

In summary, while the present disclosure has been disclosed in terms of embodiments, it is not intended to limit the disclosure. Those skilled in the art will appreciate that various modifications and adaptations can be made without departing from the spirit and scope of the present disclosure. Accordingly, the scope of the present disclosure is defined by the scope of the appended claims.

Claims (10)

1. A memory structure, comprising:

a substrate having an upper surface;

a first gate structure, a second gate structure and a third gate structure disposed on the substrate, separated from each other along a first direction and extending along a second direction and a third direction respectively; and

a plurality of channel bodies separated from each other and passing through the first gate structure, the second gate structure and the third gate structure along the first direction,

The first direction, the second direction and the third direction are staggered, the upper surface is parallel to the first direction and the second direction, and the normal direction of the upper surface is parallel to the third direction;

the second gate structure is disposed between the first gate structure and the third gate structure, the first gate structure comprises a first island structure, a second island structure and a third island structure, the third gate structure comprises a fourth island structure, a fifth island structure and a sixth island structure, the first island structure, the second island structure and the third island structure extend along the third direction respectively and are separated from each other along the second direction; the fourth island structure, the fifth island structure and the sixth island structure extend along the third direction and are separated from each other along the second direction, respectively.

2. The memory structure of claim 1, further comprising:

a plurality of dielectric films disposed between the first gate structure and the plurality of channel bodies, between the second gate structure and the plurality of channel bodies, and between the third gate structure and the plurality of channel bodies, wherein the first gate structure, the second gate structure, and the third gate structure surround each of the dielectric films and each of the channel bodies, and the plurality of dielectric films do not include a charge trapping structure; and

And the first side plug is electrically connected with the substrate and the plurality of channel bodies.

3. The memory structure of claim 2, wherein each channel body has a first end and a second end, the first end being adjacent to the first gate structure, the second end being adjacent to the third gate structure, and the second end being opposite to the first end.

4. The memory structure of claim 3, further comprising:

a plurality of first side pads stacked along the third direction and separated from each other along the third direction, each of the first side pads being connected to a corresponding one of the first ends of the plurality of channel bodies; and

and a plurality of second side pads stacked along the third direction and separated from each other along the third direction, each second side pad being connected to a corresponding second end of the plurality of channel bodies.

5. The memory structure of claim 4, further comprising a plurality of second side plugs separated from each other along the second direction, each extending along the third direction to electrically contact a plurality of landing areas on the plurality of second side pads.

6. The memory structure of claim 4, wherein the first plurality of side pads has a first conductivity type and the second plurality of side pads has a second conductivity type.

7. The memory structure of claim 1, wherein a height of the first island structure, the second island structure, or the third island structure in the third direction is equal to a height of the second gate structure in the third direction, and a width of the first island structure, the second island structure, or the third island structure in the second direction is smaller than a width of the second gate structure in the second direction.

8. The memory structure of claim 7, wherein a height of the fourth island structure, the fifth island structure, or the sixth island structure in the third direction is equal to a height of the second gate structure in the third direction, and a width of the fourth island structure, the fifth island structure, or the sixth island structure in the second direction is smaller than a width of the second gate structure in the second direction.

9. The memory structure of claim 8, wherein a width of the first island, the second island, or the third island in the second direction is equal to a width of the fourth island, the fifth island, or the sixth island in the second direction.

10. The memory structure of claim 1, wherein an operating mechanism of the memory structure is thyristor-based.