CN117376442B - Remote data concentrator protocol conversion method and equipment based on hardware processing architecture - Google Patents
Remote data concentrator protocol conversion method and equipment based on hardware processing architecture Download PDFInfo
- Publication number
- CN117376442B CN117376442B CN202311672356.5A CN202311672356A CN117376442B CN 117376442 B CN117376442 B CN 117376442B CN 202311672356 A CN202311672356 A CN 202311672356A CN 117376442 B CN117376442 B CN 117376442B
- Authority
- CN
- China
- Prior art keywords
- data
- protocol
- frame
- afdx
- channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000006243 chemical reaction Methods 0.000 title claims abstract description 62
- 238000000034 method Methods 0.000 title claims abstract description 59
- 238000012545 processing Methods 0.000 title claims abstract description 53
- 238000007781 pre-processing Methods 0.000 claims abstract description 37
- 108091006146 Channels Proteins 0.000 claims description 81
- 230000008569 process Effects 0.000 claims description 28
- 238000009432 framing Methods 0.000 claims description 15
- 230000005540 biological transmission Effects 0.000 claims description 14
- 238000004458 analytical method Methods 0.000 claims description 12
- 238000001914 filtration Methods 0.000 claims description 12
- 238000013507 mapping Methods 0.000 claims description 10
- 238000012544 monitoring process Methods 0.000 claims description 6
- 230000002159 abnormal effect Effects 0.000 claims description 5
- 230000000903 blocking effect Effects 0.000 claims description 3
- 238000004364 calculation method Methods 0.000 claims description 3
- 239000008186 active pharmaceutical agent Substances 0.000 claims 8
- 230000008901 benefit Effects 0.000 abstract description 9
- 238000010586 diagram Methods 0.000 description 6
- 238000004891 communication Methods 0.000 description 5
- 230000006870 function Effects 0.000 description 4
- 238000003672 processing method Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000004132 cross linking Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/08—Protocols for interworking; Protocol conversion
Abstract
The invention discloses a protocol conversion method and equipment of a remote data concentrator based on a hardware processing architecture, which belong to the field of protocol conversion and comprise a remote data concentrator, a protocol transceiver controller, a to-be-sent protocol data cache, a to-be-assembled frame data cache, a data preprocessing module, a baud rate controller, a polling module and a physical layer interface. The invention adopts the remote data concentrator protocol conversion method and the equipment based on the hardware processing architecture, adopts the hardware processing architecture to accelerate the hardware unloading of computation-intensive data stream processing such as data processing, protocol conversion and the like, and hands the computation tasks which are completed by software (CPU) in the traditional architecture and consume time and resources to the hardware architecture for processing, and simultaneously reserves the advantage of configuration flexibility under part of the software processing architecture by setting a configuration register.
Description
Technical Field
The present invention relates to the field of protocol conversion technologies, and in particular, to a method and an apparatus for remote data concentrator protocol conversion based on a hardware processing architecture.
Background
The backbone network of modern civil aircraft is basically unified as an avionics full duplex switched Ethernet (AFDX) network, which is a standard of an aviation data network defined in the ARINC664 protocol part 7 and meets the requirements of interconnection communication of all systems on the civil aircraft.
The modern civil aircraft interconnection architecture takes AFDX as a backbone network, subsystems using other buses exist at the same time, and meanwhile, a Remote Data Concentrator (RDC) is adopted to concentrate a plurality of bus protocol data on the backbone network for transmission and scheduling, so that the original line is replaced, the length and the weight of wiring on an aircraft are reduced, the layout of sensors and actuators on the aircraft is optimized, the cross-linking relation of each system is simplified, and the data transmission efficiency is improved. The RDC should include an A429 signal, an A825 signal and a discrete/analog communication interface to perform the conversion between these signals and the AFDX signal in the RDC. Based on the above characteristics, the remote data concentrator is widely applied to avionics systems of IMA architecture aircraft, 21 remote data concentrators are arranged on B787, 8 remote data concentrators are used in A380, 16 Remote Data Interface Units (RDIU) are arranged on domestic large aircraft C919 in China, and the function of the remote data concentrator is the same as that of RDC.
Most of researches at present have the problem that definition of rules and data formats of protocol conversion is fuzzy, and detection and specific processing methods of certain abnormal conditions are not considered; the method has the advantages that the specific design and implementation scheme of the protocol conversion function of the existing remote data concentrator are less in research, the protocol conversion and data processing process is basically completed by using a general embedded processor based on a software processing architecture, precious computing resources are consumed, meanwhile, the protocol conversion processing can only be sequentially executed under the condition that multiple paths of signals need to be processed, and the problems of low efficiency and poor instantaneity exist.
Along with the increasing tasks and functions required by the aircraft, the scale and complexity of the avionics system are rapidly increased, the computing resources on the aircraft are more precious and scarce, the traditional remote data concentrators mostly adopt a software processing architecture to complete the protocol conversion process, a great deal of computing resources are consumed by adopting the conversion mode, and meanwhile, a certain delay is brought to the protocol conversion by the serial processing mode of the software.
Disclosure of Invention
In order to solve the problems, the invention provides a remote data concentrator protocol conversion method and equipment based on a hardware processing architecture, which adopts the hardware processing architecture to accelerate hardware unloading of computation-intensive data stream processing such as data processing and protocol conversion, and the like, and hands the time-consuming and resource-consuming computation tasks completed by software (CPU) in the traditional architecture to the hardware architecture for processing, and meanwhile, the advantage of configuration flexibility under part of the software processing architecture is reserved through setting a configuration register.
In order to achieve the above object, the present invention provides a remote data concentrator protocol conversion method based on a hardware processing architecture, comprising the steps of:
s1, setting configuration parameters of a configuration register of a channel to be used, and configuring a transceiving ID of an A825 signal channel;
s2, protocol conversion:
s21, converting the device data signal into AFDX:
s211, receiving external serial data, performing receiving control processing according to an interface protocol, and completing serial-parallel conversion to form a data packet;
s212, receiving the data packet formed in the step S211, preprocessing the data packet, and storing the preprocessed data packet into a data buffer of the frame to be assembled;
s213, monitoring the data in the data buffer of the frame to be assembled in the step S212, and sending a framing starting signal to the framing module when the data packet in the data buffer of the frame to be assembled reaches an event triggering condition or a period triggering condition;
s214, framing operation: firstly, according to AFDX protocol and the value in the configuration register, the MAC header, the IP header and the UDP header are sent, then the Payload is sent, in S213, the data buffer of the frame to be assembled is realized in the form of FIFO, so that 4 data packets are sequentially read from the data FIFO buffer of the frame to be assembled and put into a, b, c and d four registers, the data format in the data FIFO buffer of the frame to be assembled is 8bit FS+32 bit/64bit DS, the corresponding 4 FS values are obtained according to the data in the four registers, firstly, the FS values corresponding to the a, b, c and d registers are sent in the form of 32bit data packets, so as to complete the sending of 4 FS in the FSS, and then DS data in the four registers of a, b, c and d are sequentially sent until the data buffer of the frame to be assembled is empty, the sending of the Payload is completed in the form of 32bits data packets, and the data packets are temporarily stored in the frame to be sent AFDX data frame;
s215, generating a sending request when a complete AFDX data frame exists in the to-be-sent AFDX data frame buffer, and sending an application sending signal to the polling module;
s216, aiming at the application sending signals in the step S215, a polling module polls the sending requests of all channels in sequence, and if the application sending signals in the step S215 in the conversion process of a certain channel are detected in the inquiry process, the buffer memory of the data frames of the to-be-sent AFDX of the channel is read until the buffer memory is empty, and the next channel is continuously inquired and cycled. Completing the conversion from a device data signal to a complete AFDX data frame in the form of a 32bits data packet when each channel reads the space, writing the complete AFDX data frame into the Uvload_fifo, and waiting for the subsequent processing of a terminal system;
s22, AFDX converting device data signals:
s221, receiving an AFDX data frame formed by a 32bit data packet output by a downlink_fifo, performing frame analysis operation on the AFDX data frame, respectively analyzing an MAC header, an IP header and a UDP header of the AFDX data frame, checking whether the MAC destination address, the Ethernet protocol type, the IP protocol number, the IP header checksum, the IP destination address, the UDP destination address and the UDP checksum meet receiving conditions, filtering the frame which does not meet the receiving conditions, storing the MAC source address, the IP source address and the UDP source address information into corresponding registers of a target channel to wait for a processor to read, finishing channel selection according to the UDP destination address of the frame, and transmitting the Payload in the AFDX data frame to a transmitting data preprocessing module of the corresponding channel;
s222, each channel receives payload data from the step S221 and performs data preprocessing, each FDS is converted into 1-4 data packets of a to-be-sent protocol according to data formats defined by different protocols, wherein for A429 data, calculation and replacement of a novel parity bit are completed in the process, the data packets of the protocol corresponding to the data packets after preprocessing are written into a to-be-sent protocol data cache, and the data packet formats are the same as those of the data packets sent to a data receiving preprocessing module by a protocol transceiver controller receiving part in the process of converting device data signals into AFDX;
s223, completing the control of the baud rate of the data packet written into the data cache of the protocol to be sent in the step S222 by the baud rate controller according to the configuration of the sending baud rate in the configuration register;
s224, the protocol transceiver controller internally receives the data read from the protocol data cache to be sent in step S223, completes the filling of the complete protocol data according to the logic in the protocol transceiver controller according to the value in the corresponding configuration register and the received data packet, and outputs the complete protocol data in the form of serial signals after processing.
Preferably, in step S1, the asynchronous serial port data format written into the configuration register is defined as 8bits of write address+32 bits of write data, and then the configuration parameters are set according to the write address of the configuration register.
Preferably, in step S211, for the a429 signal, the number of bits of the a429 data word corresponding to the a429 serial data receiving sequence is 7-0,8-31, and the a429 data word received each time is put into a 32-bit data packet and sent to the received data preprocessing module;
for the A825 signal, after the identification and the reception of the A825 signal are completed, filtering an A825 CAN message which is not matched with the configuration ID and a message which does not pass the CRC check, putting the FSB and the DLC in the rest messages meeting the conditions into the upper five bits of the 69bit Data packet, putting the Data into the lower 64bits, and sending the Data packet which is completed to be filled into a received Data preprocessing module;
and for UART signals, after the start bit and the stop bit are identified, extracting UART transmitted data, wherein the number of UART parallel data bits corresponding to the UART serial data transmission sequence is 0-7, sequentially putting bytes received each time into a 40bit/72bit data packet from the high bit, and then transmitting the bytes to a received data preprocessing module.
Preferably, the step S212 specifically includes the following steps:
s2121, checking the content of each received data packet, wherein for A429 data, checking whether the parity check bit is correct, for UART data, checking whether the value of the status word is in the enumeration range, and for A825 CAN data, checking whether the DLC is in the enumeration range;
s2122, performing FS mapping on the abnormal situation checked in the step S2121, wherein the FS mapping is to discard the data of 0x00 and set DS in the data of 0x03 to be 32'b0/64' b0;
s2123, converting effective data in the received data into a form of 8bit FS+32 bit/64bit DS, forming a data packet with 40bit/72bit, and storing the data packet into a data buffer of a frame to be assembled.
Preferably, the maximum event triggering condition configurable in step S213 is that 64 data packets are received, and the maximum receiving period is 320ms;
the frame data to be assembled is buffered into a FIFO memory with a width of 40bit/72bit and a depth of 64.
Preferably, in step S214, a two-byte padding signal is added between header information of the MAC header, the IP header, and the UDP header and the Payload to align data.
Preferably, in step S215, considering the boundary condition, it is assumed that each channel simultaneously sends a sending request to the polling module, and the maximum AFDX data frame does not cause data blocking, the buffer depth of the to-be-sent AFDX data frame of the 32-bit data word channel is set to 128, and the buffer depth of the to-be-sent AFDX data frame of the 64-bit data word channel is set to 256.
Preferably, in step S221, the external input should perform flow control on the data input to each channel, and when a certain channel does not output serial data, the data preprocessing of the next AFDX data frame will not be performed;
in step S223, the to-be-transmitted protocol data buffer receives at most 64 data words of the channel, and the data entering the buffer is read to the transmitting part of the protocol transceiver controller according to the configured transmission baud rate;
in step S224, the data format of the data packet to be transmitted, which is input to the transmitting section of the protocol transceiver controller, is the same as the data packet format output from the receiving section of the protocol transceiver controller.
An apparatus for a remote data concentrator protocol conversion method based on a hardware processing architecture, comprising:
the configuration register module is used for receiving the serial port data and converting the serial port data into a configuration structural form;
the physical layer receiving interface is used for receiving standard level signals of three serial data in the process of converting the device data signals into AFDX protocol, converting the standard level signals into digital signals which can be recognized by a digital system, and finishing level conversion of signals sent by a sending part of a protocol transceiver controller and transmission of target devices;
the receiving part of the protocol transceiver controller is used for completing signal receiving and converting into a parallel data frame form according to the protocol time sequence and the protocol format requirement when the digital signal after the level conversion is entered;
the frame data to be assembled is cached, and is used for preprocessing the received data according to a set rule to form a data packet in the form of FS+DS, storing the data packet in the form of FS+DS, continuously monitoring the entering data packet, and carrying out framing operation by utilizing the cached data when the data packet reaches a trigger condition set during configuration;
the polling module is used for receiving a complete request after the framing of the AFDX data frames, and reading the AFDX data frames of the channel to be sent to the data FIFO to be uplink when the polling module inquires the sending request of the channel according to the channel sequence;
the frame analysis and filtering module is used for reading the data FIFO to be downlink in the process of converting the AFDX into the data signal of the equipment, and sending the application data obtained by analysis to the data preprocessing module of the corresponding channel through the destination UDP address after the analysis and the filtering are completed;
the sending data preprocessing module is used for analyzing the FSS field and the DS field corresponding to the FSS field of the application data to form a data packet in the form of FS+DS and storing the data packet in a waiting protocol data cache;
the baud rate controller is used for matching with the serial output rate, continuously reading the data in the data cache of the protocol to be transmitted according to the set baud rate, and transmitting the data to the transmitting part of the protocol transceiver controller according to the calculated corresponding interval time of the set baud rate;
and the transmitting part of the protocol transceiver controller is used for transmitting the data from the protocol data cache to be transmitted, completing the filling of the complete protocol data according to the value in the corresponding configuration register, converting the complete protocol data into a serial signal form and outputting the serial signal form to the physical layer transmitting interface.
The invention has the following beneficial effects:
1. the method is characterized in that logic implementation is carried out based on visible Hardware Description Language (HDL), and development implementation has the advantages of realizability, controllability, visible code, easiness in use and the like compared with the prior art;
2. considering the complex situation of avionic equipment in the actual use process, the ARINC standard is referred to provide data format definition of each protocol and specific protocol conversion rules, and the abnormal situation is explained and a processing method is provided, so that the method is more suitable for the complex environment in the actual use process;
3. in the process of protocol conversion, a hardware processing architecture is adopted to complete data processing, meanwhile, the configuration flexibility advantage of the original software processing architecture is combined, a configuration register is added into the system architecture, when the data processing such as protocol conversion can be completed by using hardware, the configuration and management of the system can be completed by writing data into the configuration register according to the use requirement, the processing architecture has the advantages of small conversion delay, high efficiency, processor task unloading, operating system burden alleviation and the like, and compared with the specific implementation method of the conventional RDC, the system architecture integrates multi-type multi-channel interfaces, and has stronger universality;
4. the hardware unloading acceleration is carried out in the AFDX protocol encapsulation and disassembly process of the user transmission data, so that the burden of an upper operating system is reduced, the use efficiency of hardware is improved, and the data transmission speed is increased;
5. by arranging the multi-type multi-channel communication interface, various potential situations and specific processing operations of the device in the working process are defined, and compared with the traditional architecture, the multi-channel communication interface has stronger universality.
The technical scheme of the invention is further described in detail through the drawings and the embodiments.
Drawings
FIG. 1 is a schematic block diagram of a remote data concentrator protocol conversion method based on a hardware processing architecture of the present invention;
FIG. 2 is an application diagram of a remote data concentrator protocol conversion method based on a hardware processing architecture of the present invention;
FIG. 3 is a diagram illustrating a message format according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating a429 data-to-AFDX mapping transformation according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating mapping conversion between A825 data and AFDX according to an embodiment of the present invention;
fig. 6 is a schematic diagram of UART Message and AFDX mapping conversion between 32bits and 64bits according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the detailed description and specific examples, while indicating the embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present application based on the embodiments herein. Examples of the embodiments are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements throughout or elements having like or similar functionality.
It should be noted that the terms "comprises" and "comprising," along with any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or server that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed or inherent to such process, method, article, or apparatus, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present invention, it should be noted that, directions or positional relationships indicated by terms such as "upper", "lower", "inner", "outer", etc., are directions or positional relationships based on those shown in the drawings, or those that are conventionally put in use, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the apparatus or elements to be referred to must have a specific direction, be constructed and operated in a specific direction, and thus should not be construed as limiting the present invention.
In the description of the present invention, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "mounted," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
As shown in fig. 1, the remote data concentrator protocol conversion method based on the hardware processing architecture comprises the following steps:
s1, setting configuration parameters of a configuration register of a channel to be used, and configuring a transceiving ID of an A825 signal channel;
preferably, in step S1, the asynchronous serial port data format written into the configuration register is defined as 8bits of write address+32 bits of write data, and then the configuration parameters are set according to the write address of the configuration register.
The configuration parameters include the transmit-receive baud rate of each channel interface, the receiving mode (periodical receiving and event triggered receiving) of each channel when the device data signal is converted into the AFDX data frame, the receiving period (5-320 ms), the number of events triggering receiving (1-64 channel data words), each field of the IP destination address, the UDP destination address, the virtual link number of the MAC multicast address, the type of a429 data words (BCD, BNR, discrete) received by all a429 channels, the acceptable ID number of all a825 channels, the acceptable ID wild mask, the ID number when transmitting a825 serial signals.
In this embodiment, the corresponding conditions and detailed information of the configuration register address and the configuration parameter are shown in the following table:
table 1 UART channel register configuration address allocation table
；
Table 2 a429 channel register configuration address allocation table
；
Table 3 a825 channel register configuration address allocation table
；
S2, protocol conversion:
s21, converting the device data signal into AFDX:
s211, receiving external serial data, performing receiving control processing according to an interface protocol, and completing serial-parallel conversion to form a data packet; s212, receiving the data packet formed in the step S211, preprocessing the data packet, and storing the preprocessed data packet into a data buffer of the frame to be assembled;
s213, monitoring the data in the data buffer of the frame to be assembled in the step S212, and sending a framing starting signal to the framing module when the data packet in the data buffer of the frame to be assembled reaches an event triggering condition or a period triggering condition;
s214, framing operation: firstly, according to AFDX protocol and the value in the configuration register, the MAC header, the IP header and the UDP header are sent, then the Payload is sent, in S213, the data buffer of the frame to be assembled is realized in the form of FIFO, so that 4 data packets are sequentially read from the data FIFO buffer of the frame to be assembled and put into a, b, c and d four registers, the data format in the data FIFO buffer of the frame to be assembled is 8bit FS+32 bit/64bit DS, the corresponding 4 FS values are obtained according to the data in the four registers, firstly, the FS values corresponding to the a, b, c and d registers are sent in the form of 32bit data packets, so as to complete the sending of 4 FS in the FSS, and then DS data in the four registers of a, b, c and d are sequentially sent until the data buffer of the frame to be assembled is empty, the sending of the Payload is completed in the form of 32bits data packets, and the data packets are temporarily stored in the frame to be sent AFDX data frame;
s215, generating a sending request when a complete AFDX data frame exists in the to-be-sent AFDX data frame buffer, and sending an application sending signal to the polling module;
s216, aiming at the application sending signals in the step S215, a polling module polls the sending requests of all channels in sequence, and if the application sending signals in the step S215 in the conversion process of a certain channel are detected in the inquiry process, the buffer memory of the data frames of the to-be-sent AFDX of the channel is read until the buffer memory is empty, and the next channel is continuously inquired and cycled. Completing the conversion from a device data signal to a complete AFDX data frame in the form of a 32bits data packet when each channel reads the space, writing the complete AFDX data frame into the Uvload_fifo, and waiting for the subsequent processing of a terminal system;
s22, AFDX converting device data signals:
s221, receiving an AFDX data frame formed by a 32bit data packet output by a downlink_fifo, performing frame analysis operation on the AFDX data frame, respectively analyzing an MAC header, an IP header and a UDP header of the AFDX data frame, checking whether the MAC destination address, the Ethernet protocol type, the IP protocol number, the IP header checksum, the IP destination address, the UDP destination address and the UDP checksum meet receiving conditions, filtering the frame which does not meet the receiving conditions, storing the MAC source address, the IP source address and the UDP source address information into corresponding registers of a target channel to wait for a processor to read, finishing channel selection according to the UDP destination address of the frame, and transmitting the Payload in the AFDX data frame to a transmitting data preprocessing module of the corresponding channel;
s222, each channel receives payload data from the step S221 and performs data preprocessing, each FDS is converted into 1-4 data packets of a to-be-sent protocol according to data formats defined by different protocols, wherein for A429 data, calculation and replacement of a novel parity bit are completed in the process, the data packets of the protocol corresponding to the data packets after preprocessing are written into a to-be-sent protocol data cache, and the data packet formats are the same as those of the data packets sent to a data receiving preprocessing module by a protocol transceiver controller receiving part in the process of converting device data signals into AFDX;
s223, completing the control of the baud rate of the data packet written into the data cache of the protocol to be sent in the step S222 by the baud rate controller according to the configuration of the sending baud rate in the configuration register;
s224, the protocol transceiver controller internally receives the data read from the protocol data cache to be sent in step S223, completes the filling of the complete protocol data according to the logic in the protocol transceiver controller according to the value in the corresponding configuration register and the received data packet, and outputs the complete protocol data in the form of serial signals after processing.
Preferably, in step S1, the asynchronous serial port data format written into the configuration register is defined as 8bits of write address+32 bits of write data, and then the configuration parameters are set according to the write address of the configuration register.
Preferably, in step S211, for the a429 signal, the number of bits of the a429 data word corresponding to the a429 serial data receiving sequence is 7-0,8-31, and the a429 data word received each time is put into a 32-bit data packet and sent to the received data preprocessing module;
for the A825 signal, after the identification and the reception of the A825 signal are completed, filtering an A825 CAN message which is not matched with the configuration ID and a message which does not pass the CRC check, putting the FSB and the DLC in the rest messages meeting the conditions into the upper five bits of the 69bit Data packet, putting the Data into the lower 64bits, and sending the Data packet which is completed to be filled into a received Data preprocessing module;
and for UART signals, after the start bit and the stop bit are identified, extracting UART transmitted data, wherein the number of UART parallel data bits corresponding to the UART serial data transmission sequence is 0-7, sequentially putting bytes received each time into a 40bit/72bit data packet from the high bit, and then transmitting the bytes to a received data preprocessing module.
Preferably, the step S212 specifically includes the following steps:
s2121, checking the content of each received data packet, wherein for A429 data, checking whether the parity check bit is correct, for UART data, checking whether the value of the status word is in the enumeration range, and for A825 CAN data, checking whether the DLC is in the enumeration range;
s2122, performing FS mapping on the abnormal situation checked in the step S2121, wherein the FS mapping is to discard the data of 0x00 and set DS in the data of 0x03 to be 32'b0/64' b0;
s2123, converting effective data in the received data into a form of 8bit FS+32 bit/64bit DS, forming a data packet with 40bit/72bit, and storing the data packet into a data buffer of a frame to be assembled.
Preferably, the maximum event triggering condition configurable in step S213 is that 64 data packets are received, and the maximum receiving period is 320ms;
the frame data to be assembled is buffered into a FIFO memory with a width of 40bit/72bit and a depth of 64.
Preferably, in step S214, a two-byte padding signal is added between header information of the MAC header, the IP header, and the UDP header and the Payload to align data.
Preferably, in step S215, considering the boundary condition, it is assumed that each channel simultaneously sends a sending request to the polling module, and the maximum AFDX data frame does not cause data blocking, the buffer depth of the to-be-sent AFDX data frame of the 32-bit data word channel is set to 128, and the buffer depth of the to-be-sent AFDX data frame of the 64-bit data word channel is set to 256.
Preferably, in step S221, the external input should perform flow control on the data input to each channel, and when a certain channel does not output serial data, the data preprocessing of the next AFDX data frame will not be performed;
in step S223, the to-be-transmitted protocol data buffer receives at most 64 data words of the channel, and the data entering the buffer is read to the transmitting part of the protocol transceiver controller according to the configured transmission baud rate;
in step S224, the data format of the data packet to be transmitted, which is input to the transmitting section of the protocol transceiver controller, is the same as the data packet format output from the receiving section of the protocol transceiver controller.
An apparatus for a remote data concentrator protocol conversion method based on a hardware processing architecture, comprising:
the configuration register module is used for receiving the serial port data and converting the serial port data into a configuration structural form;
the physical layer receiving interface is used for receiving standard level signals of three serial data in the process of converting the device data signals into AFDX protocol, converting the standard level signals into digital signals which can be recognized by a digital system, and finishing level conversion of signals sent by a sending part of a protocol transceiver controller and transmission of target devices;
the receiving part of the protocol transceiver controller is used for completing signal receiving and converting into a parallel data frame form according to the protocol time sequence and the protocol format requirement when the digital signal after the level conversion is entered;
the frame data to be assembled is cached, and is used for preprocessing the received data according to a set rule to form a data packet in the form of FS+DS, storing the data packet in the form of FS+DS, continuously monitoring the entering data packet, and carrying out framing operation by utilizing the cached data when the data packet reaches a trigger condition set during configuration;
the polling module is used for receiving a complete request after the framing of the AFDX data frames, and reading the AFDX data frames of the channel to be sent to the data FIFO to be uplink when the polling module inquires the sending request of the channel according to the channel sequence;
the frame analysis and filtering module is used for reading the data FIFO to be downlink in the process of converting the AFDX into the data signal of the equipment, and sending the application data obtained by analysis to the data preprocessing module of the corresponding channel through the destination UDP address after the analysis and the filtering are completed;
the sending data preprocessing module is used for analyzing the FSS field and the DS field corresponding to the FSS field of the application data to form a data packet in the form of FS+DS and storing the data packet in a waiting protocol data cache;
the baud rate controller is used for matching with the serial output rate, continuously reading the data in the data cache of the protocol to be transmitted according to the set baud rate, and transmitting the data to the transmitting part of the protocol transceiver controller according to the calculated corresponding interval time of the set baud rate;
and the transmitting part of the protocol transceiver controller is used for transmitting the data from the protocol data cache to be transmitted, completing the filling of the complete protocol data according to the value in the corresponding configuration register, converting the complete protocol data into a serial signal form and outputting the serial signal form to the physical layer transmitting interface.
The remote data concentrator is provided with 8 ARINC429 signal input/output channels (8 different A429 devices CAN be connected), 4A 825 signal input/output channels (4 different CAN bus devices CAN be connected), 4 analog/discrete signal input/output channels (4 different devices using UART serial ports such as RS485/RS422/RS232 CAN be connected).
As shown in fig. 2, in this embodiment, the data link layer of the a429, CAN and analog/discrete signals is to be processed, and when the signals are input, the signals are converted to obtain digital signals through a physical layer interface or a transceiver, then the digital signals are processed through the implementation part of the present invention, and finally the processed data are put into an AFDX data frame transmission buffer to wait for the subsequent operation of the end system; when the AFDX data frame receiving buffer has data which needs to be converted into the signals to be transmitted, the realization part of the invention reads the data of the AFDX data frame receiving buffer and carries out protocol conversion processing, and finally, a digital signal which accords with the protocol is transmitted to a physical layer interface or a transceiver to be output to a signal line after the level conversion is completed.
The standard format of the AFDX data frame is described in the ARINC related standard, and the format of the application message is defined for better information interaction with the upper operating system and the resident function, and the AFDX data frame format and the application message format shown in fig. 3 are specified for the above requirements.
As can be seen from fig. 3, the application message contains one and only one reserved word (Rsvd), occupies the first word (bit 0 to bit 31) of the whole message, the length of the message must be a multiple of 32bits, and the message which does not meet the requirement should consider using padding in DS;
FDS, functional Data Set, functional dataset: a functional data set consisting of a Functional State Set (FSS) and its overlaid associated Data Set (DS), each Functional Data Set (FDS) comprising a Functional State Set (FSS); at least one Data Set (DS), at most not more than four Data Sets (DS);
FSS, functional Status Set, set of functional states: it is a 32-bit field consisting of four 8-bit Functional Status (FS) fields. And an nth Functional Status (FS) field for identifying a status (n.ltoreq.4) of an nth Data Set (DS);
FS, functional Status, functional status: providing an indication for each dataset in the FDS, wherein FS is an 8-bit enumeration type field, and four states are defined in total;
DS, data Set, dataset: the length of the actually transmitted data must be a multiple of 32bits, in this embodiment, the DS length of the AFDX data frame in each channel is specified, the DS of the a429 channel is fixed to 32bits, the DS of the a825 channel is fixed to 64bits, the DS of the 2 UART channels is fixed to 32bits, and the DS of the 2 UART channels is fixed to 64bits, which considers that a data word in one DS corresponds to only one status field identification, and if a status field identification corresponding to one data word is invalid, the whole DS is marked invalid, so that the fixing the DS length of each channel can improve efficiency and reduce the cost of data error.
While each channel has data bits representing its associated state for the protocol signal to be converted into an AFDX data frame, these data bits form a mutual mapping with the FS field in the AFDX data frame as shown in fig. 4-6.
It can be known that the method for processing the protocol conversion of the remote data concentrator based on the hardware processing architecture is designed by taking the domestic trend of the large aircraft airborne equipment and the autonomous controllable target of the aviation industry into consideration and taking the AFDX as a main network as the basis, and has the advantages of high efficiency, configurability, good instantaneity, strong universality and the like.
Therefore, the method and the device for protocol conversion of the remote data concentrator based on the hardware processing architecture are adopted, the hardware processing architecture is adopted to accelerate hardware unloading of computation-intensive data stream processing such as data processing, protocol conversion and the like, time-consuming and resource-consuming computing tasks completed by software (CPU) in the traditional architecture are processed by the hardware architecture, and meanwhile, the advantage of configuration flexibility under part of the software processing architecture is reserved through setting a configuration register.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention and not for limiting it, and although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that: the technical scheme of the invention can be modified or replaced by the same, and the modified technical scheme cannot deviate from the spirit and scope of the technical scheme of the invention.
Claims (9)
1. The remote data concentrator protocol conversion method based on the hardware processing architecture is characterized by comprising the following steps of: the method comprises the following steps:
s1, setting configuration parameters of a configuration register of a channel to be used, and configuring a transceiving ID of an A825 signal channel;
s2, protocol conversion:
s21, converting the device data signal into AFDX:
s211, receiving external serial data, performing receiving control processing according to an interface protocol, and completing serial-parallel conversion to form a data packet;
s212, receiving the data packet formed in the step S211, preprocessing the data packet, and storing the preprocessed data packet into a data buffer of the frame to be assembled;
s213, monitoring the data in the data buffer of the frame to be assembled in the step S212, and sending a framing starting signal to the framing module when the data packet in the data buffer of the frame to be assembled reaches an event triggering condition or a period triggering condition;
s214, framing operation: firstly, according to AFDX protocol and the value in the configuration register, the MAC header, the IP header and the UDP header are sent, then the Payload is sent, in S213, the data buffer of the frame to be assembled is realized in the form of FIFO, so that 4 data packets are sequentially read from the data FIFO buffer of the frame to be assembled and put into a, b, c and d four registers, the data format in the data FIFO buffer of the frame to be assembled is 8bit FS+32 bit/64bit DS, the corresponding 4 FS values are obtained according to the data in the four registers, firstly, the FS values corresponding to the a, b, c and d registers are sent in the form of 32bit data packets, so as to complete the sending of 4 FS in the FSS, and then DS data in the four registers of a, b, c and d are sequentially sent until the data buffer of the frame to be assembled is empty, the sending of the Payload is completed in the form of 32bits data packets, and the data packets are temporarily stored in the frame to be sent AFDX data frame;
s215, generating a sending request when a complete AFDX data frame exists in the to-be-sent AFDX data frame buffer, and sending an application sending signal to the polling module;
s216, aiming at the application sending signals in the step S215, a polling module polls the sending requests of all channels in sequence, and if the application sending signals in the step S215 in the conversion process of a certain channel are detected in the inquiry process, the to-be-sent AFDX data frame buffer memory of the channel is read until the to-be-sent AFDX data frame buffer memory is empty, and the next channel is continuously inquired and reciprocated in a circulating way; completing the conversion from a device data signal to a complete AFDX data frame in the form of a 32bits data packet when each channel reads the space, writing the complete AFDX data frame into the Uvload_fifo, and waiting for the subsequent processing of a terminal system;
s22, AFDX converting device data signals:
s221, receiving an AFDX data frame formed by a 32bit data packet output by a downlink_fifo, performing frame analysis operation on the AFDX data frame, respectively analyzing an MAC header, an IP header and a UDP header of the AFDX data frame, checking whether the MAC destination address, the Ethernet protocol type, the IP protocol number, the IP header checksum, the IP destination address, the UDP destination address and the UDP checksum meet receiving conditions, filtering the frame which does not meet the receiving conditions, storing the MAC source address, the IP source address and the UDP source address information into corresponding registers of a target channel to wait for a processor to read, finishing channel selection according to the UDP destination address of the frame, and transmitting the Payload in the AFDX data frame to a transmitting data preprocessing module of the corresponding channel;
s222, each channel receives payload data from the step S221 and performs data preprocessing, each FDS is converted into 1-4 data packets of a to-be-sent protocol according to data formats defined by different protocols, wherein for A429 data, calculation and replacement of a novel parity bit are completed in the process, the data packets of the protocol corresponding to the data packets after preprocessing are written into a to-be-sent protocol data cache, and the data packet formats are the same as those of the data packets sent to a data receiving preprocessing module by a protocol transceiver controller receiving part in the process of converting device data signals into AFDX;
s223, completing the control of the baud rate of the data packet written into the data cache of the protocol to be sent in the step S222 by the baud rate controller according to the configuration of the sending baud rate in the configuration register;
s224, the protocol transceiver controller internally receives the data read from the protocol data cache to be sent in step S223, completes the filling of the complete protocol data according to the logic in the protocol transceiver controller according to the value in the corresponding configuration register and the received data packet, and outputs the complete protocol data in the form of serial signals after processing.
2. The hardware processing architecture based remote data concentrator protocol conversion method of claim 1, wherein: in step S1, the asynchronous serial port data format written into the configuration register is defined as 8bits of written address+32 bits of written data, and then configuration parameters are set according to the written address of the configuration register.
3. The hardware processing architecture based remote data concentrator protocol conversion method of claim 1, wherein: in step S211, for the a429 signal, the number of bits of the a429 data word corresponding to the a429 serial data receiving sequence is 7-0,8-31, and the a429 data word received each time is put into a 32bit data packet and sent to the received data preprocessing module;
for the A825 signal, after the identification and the reception of the A825 signal are completed, filtering an A825 CAN message which is not matched with the configuration ID and a message which does not pass the CRC check, putting the FSB and the DLC in the rest messages meeting the conditions into the upper five bits of the 69bit Data packet, putting the Data into the lower 64bits, and sending the Data packet which is completed to be filled into a received Data preprocessing module;
and for UART signals, after the start bit and the stop bit are identified, extracting UART transmitted data, wherein the number of UART parallel data bits corresponding to the UART serial data transmission sequence is 0-7, sequentially putting bytes received each time into a 40bit/72bit data packet from the high bit, and then transmitting the bytes to a received data preprocessing module.
4. The hardware processing architecture based remote data concentrator protocol conversion method of claim 1, wherein: step S212 specifically includes the following steps:
s2121, checking the content of each received data packet, wherein for A429 data, checking whether the parity check bit is correct, for UART data, checking whether the value of the status word is in the enumeration range, and for A825 CAN data, checking whether the DLC is in the enumeration range;
s2122, performing FS mapping on the abnormal situation checked in the step S2121, wherein the FS mapping is to discard the data of 0x00 and set DS in the data of 0x03 to be 32'b0/64' b0;
s2123, converting effective data in the received data into a form of 8bit FS+32 bit/64bit DS, forming a data packet with 40bit/72bit, and storing the data packet into a data buffer of a frame to be assembled.
5. The hardware processing architecture based remote data concentrator protocol conversion method of claim 1, wherein: the maximum event triggering condition that can be configured in step S213 is that 64 data packets are received, and the maximum receiving period is 320ms;
the frame data to be assembled is buffered into a FIFO memory with a width of 40bit/72bit and a depth of 64.
6. The hardware processing architecture based remote data concentrator protocol conversion method of claim 1, wherein: in step S214, a two-byte padding signal is added between header information of the MAC header, the IP header, and the UDP header and the Payload to align data.
7. The hardware processing architecture based remote data concentrator protocol conversion method of claim 1, wherein: in step S215, considering the boundary condition, assuming that each channel simultaneously sends a sending request to the polling module and the maximum AFDX data frame does not cause data blocking, the buffer depth of the to-be-sent AFDX data frame of the 32-bit data word channel is set to 128, and the buffer depth of the to-be-sent AFDX data frame of the 64-bit data word channel is set to 256.
8. The hardware processing architecture based remote data concentrator protocol conversion method of claim 1, wherein: in step S221, the external input should perform flow control on the data input to each channel, and when a certain channel does not output serial data, the data preprocessing of the next AFDX data frame will not be performed;
in step S223, the to-be-transmitted protocol data buffer receives at most 64 data words of the channel, and the data entering the buffer is read to the transmitting part of the protocol transceiver controller according to the configured transmission baud rate;
in step S224, the data format of the data packet to be transmitted, which is input to the transmitting section of the protocol transceiver controller, is the same as the data packet format output from the receiving section of the protocol transceiver controller.
9. The apparatus of the hardware processing architecture based remote data concentrator protocol conversion method of any of the preceding claims 1-8, wherein: comprising the following steps:
the configuration register module is used for receiving the serial port data and converting the serial port data into a configuration structural form;
the physical layer receiving interface is used for receiving standard level signals of three serial data in the process of converting the device data signals into AFDX protocol, converting the standard level signals into digital signals which can be recognized by a digital system, and finishing level conversion of signals sent by a sending part of a protocol transceiver controller and transmission of target devices;
the receiving part of the protocol transceiver controller is used for completing signal receiving and converting into a parallel data frame form according to the protocol time sequence and the protocol format requirement when the digital signal after the level conversion is entered;
the frame data to be assembled is cached, and is used for preprocessing the received data according to a set rule to form a data packet in the form of FS+DS, storing the data packet in the form of FS+DS, continuously monitoring the entering data packet, and carrying out framing operation by utilizing the cached data when the data packet reaches a trigger condition set during configuration;
the polling module is used for receiving a complete request after the framing of the AFDX data frames, and reading the AFDX data frames of the channel to be sent to the data FIFO to be uplink when the polling module inquires the sending request of the channel according to the channel sequence;
the frame analysis and filtering module is used for reading the data FIFO to be downlink in the process of converting the AFDX into the data signal of the equipment, and sending the application data obtained by analysis to the data preprocessing module of the corresponding channel through the destination UDP address after the analysis and the filtering are completed;
the sending data preprocessing module is used for analyzing the FSS field and the DS field corresponding to the FSS field of the application data to form a data packet in the form of FS+DS and storing the data packet in a waiting protocol data cache;
the baud rate controller is used for matching with the serial output rate, continuously reading the data in the data cache of the protocol to be transmitted according to the set baud rate, and transmitting the data to the transmitting part of the protocol transceiver controller according to the calculated corresponding interval time of the set baud rate;
and the transmitting part of the protocol transceiver controller is used for transmitting the data from the protocol data cache to be transmitted, completing the filling of the complete protocol data according to the value in the corresponding configuration register, converting the complete protocol data into a serial signal form and outputting the serial signal form to the physical layer transmitting interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311672356.5A CN117376442B (en) | 2023-12-07 | 2023-12-07 | Remote data concentrator protocol conversion method and equipment based on hardware processing architecture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311672356.5A CN117376442B (en) | 2023-12-07 | 2023-12-07 | Remote data concentrator protocol conversion method and equipment based on hardware processing architecture |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117376442A CN117376442A (en) | 2024-01-09 |
| CN117376442B true CN117376442B (en) | 2024-03-08 |
Family
ID=89406279
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311672356.5A Active CN117376442B (en) | 2023-12-07 | 2023-12-07 | Remote data concentrator protocol conversion method and equipment based on hardware processing architecture |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117376442B (en) |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102143185A (en) * | 2011-03-31 | 2011-08-03 | 北京经纬恒润科技有限公司 | Data transmission method and data transmission device |
| CN102209000A (en) * | 2011-07-05 | 2011-10-05 | 北京航空航天大学 | Avionics full duplex switched Ethernet (AFDX) network terminal system simulator with layered fault injection and fault analysis functions |
| CN103024042A (en) * | 2012-12-13 | 2013-04-03 | 中国航空无线电电子研究所 | Avionics full duplex switched Ethernet (AFDX) terminal protocol stack, and data receiving and sending method thereof |
| CN203759493U (en) * | 2013-11-13 | 2014-08-06 | 中电科航空电子有限公司 | Integration monitoring system based on AFDX bus |
| CN108462642A (en) * | 2018-03-16 | 2018-08-28 | 西安电子科技大学 | UDP/IP hardware protocol stacks based on FPGA and implementation method |
| CN108768841A (en) * | 2018-04-23 | 2018-11-06 | 西北工业大学 | AFDX security gateway systems and its transmission method |
| CN109246081A (en) * | 2018-08-07 | 2019-01-18 | 中国航空无线电电子研究所 | Aerial Electronic Equipment AFDX bus and A429, RS422 bus data conversion method |
| CN112269803A (en) * | 2020-10-21 | 2021-01-26 | 中国商用飞机有限责任公司北京民用飞机技术研究中心 | Data set filling method and system |
| CN114884887A (en) * | 2022-03-24 | 2022-08-09 | 中国民航大学 | Security-oriented AFDX switch credit dynamic management system and method |
| CN115695567A (en) * | 2022-08-26 | 2023-02-03 | 中国商用飞机有限责任公司北京民用飞机技术研究中心 | Reconfigurable remote data interface unit, test system and computer equipment |
| CN115903569A (en) * | 2022-10-13 | 2023-04-04 | 中国航空无线电电子研究所 | Full-digital comprehensive modular avionics system |
| CN116647423A (en) * | 2023-05-15 | 2023-08-25 | 上海大学 | ARINC825 node machine and digital gateway-based design and implementation method |
| CN116647490A (en) * | 2023-04-03 | 2023-08-25 | 中航西安飞机工业集团股份有限公司 | Aviation AFDX network data detection system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2532773A (en) * | 2014-11-27 | 2016-06-01 | Airbus Operations Sas | Improvements in or relating to avionics networks |
-
2023
- 2023-12-07 CN CN202311672356.5A patent/CN117376442B/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102143185A (en) * | 2011-03-31 | 2011-08-03 | 北京经纬恒润科技有限公司 | Data transmission method and data transmission device |
| CN102209000A (en) * | 2011-07-05 | 2011-10-05 | 北京航空航天大学 | Avionics full duplex switched Ethernet (AFDX) network terminal system simulator with layered fault injection and fault analysis functions |
| CN103024042A (en) * | 2012-12-13 | 2013-04-03 | 中国航空无线电电子研究所 | Avionics full duplex switched Ethernet (AFDX) terminal protocol stack, and data receiving and sending method thereof |
| CN203759493U (en) * | 2013-11-13 | 2014-08-06 | 中电科航空电子有限公司 | Integration monitoring system based on AFDX bus |
| CN108462642A (en) * | 2018-03-16 | 2018-08-28 | 西安电子科技大学 | UDP/IP hardware protocol stacks based on FPGA and implementation method |
| CN108768841A (en) * | 2018-04-23 | 2018-11-06 | 西北工业大学 | AFDX security gateway systems and its transmission method |
| CN109246081A (en) * | 2018-08-07 | 2019-01-18 | 中国航空无线电电子研究所 | Aerial Electronic Equipment AFDX bus and A429, RS422 bus data conversion method |
| CN112269803A (en) * | 2020-10-21 | 2021-01-26 | 中国商用飞机有限责任公司北京民用飞机技术研究中心 | Data set filling method and system |
| CN114884887A (en) * | 2022-03-24 | 2022-08-09 | 中国民航大学 | Security-oriented AFDX switch credit dynamic management system and method |
| CN115695567A (en) * | 2022-08-26 | 2023-02-03 | 中国商用飞机有限责任公司北京民用飞机技术研究中心 | Reconfigurable remote data interface unit, test system and computer equipment |
| CN115903569A (en) * | 2022-10-13 | 2023-04-04 | 中国航空无线电电子研究所 | Full-digital comprehensive modular avionics system |
| CN116647490A (en) * | 2023-04-03 | 2023-08-25 | 中航西安飞机工业集团股份有限公司 | Aviation AFDX network data detection system |
| CN116647423A (en) * | 2023-05-15 | 2023-08-25 | 上海大学 | ARINC825 node machine and digital gateway-based design and implementation method |
Non-Patent Citations (5)
| Title |
|---|
| AFDX总线网络数据传输分析;徐科华;;民用飞机设计与研究(第03期);全文 * |
| 基于AFDX总线的A320模拟器硬件仿真方案研究;王勇;钱文高;;测控技术(第01期);全文 * |
| 基于FPGA IP核的AFDX与ARINC429总线转换接口设计;刘连生;梁林林;《计算机测量与控制》;20150825;第23卷(第08期);全文 * |
| 基于短帧优先调度的AFDX端系统发送策略;吴桓;葛红娟;倪建丽;徐媛媛;;航空计算技术;20121115(第06期);全文 * |
| 基于结构优化的环形振荡器硬件木马检测;王鹏等;微电子学;第53卷(第03期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117376442A (en) | 2024-01-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4554863B2 (en) | Network adapter and communication method with reduced hardware | |
| US5247626A (en) | Fddi controller having flexible buffer management | |
| Ray | Performance evaluation of medium access control protocols for distributed digital avionics | |
| US10628357B2 (en) | Network controller—sideband interface port controller | |
| EP0724794A1 (en) | Error detection and correction apparatus for an asynchronous transfer mode (atm) network device | |
| CN106953853A (en) | A kind of network-on-chip gigabit Ethernet resource node and its method of work | |
| US9893990B2 (en) | Network controller-sideband interface port controller | |
| CN103023784A (en) | System and method for safety communications between aeronautical data bus and Ethernet | |
| US10218635B2 (en) | Network controller-sideband interface port controller | |
| CN117376442B (en) | Remote data concentrator protocol conversion method and equipment based on hardware processing architecture | |
| US6353619B1 (en) | Circuit to integrate a host processor with special packet-handling logic for use with a DSL modem | |
| CN110098869B (en) | Optical fiber channel message transmission method | |
| CN116647423A (en) | ARINC825 node machine and digital gateway-based design and implementation method | |
| CN103618683A (en) | AFDX interchanger terminal protocol stack structure and method for receiving and sending data thereof | |
| Molina et al. | Implementation of an AFDX interface with Zynq SoC board in FPGA | |
| US11909850B1 (en) | Dynamic improvement of a communication channel | |
| Wang | Research on multi-interface conversion design technology based on network | |
| Zhang et al. | Research and software design of high reliability communication of CAN bus ID dynamically configurable on satellite | |
| CN109189711A (en) | Serial console interface and its application method based on Ethernet | |
| Suvorova | An Approach to Designing Heterogeneous Networks for High Performance Computing Systems Based on a Unified Reconfigurable Router Core | |
| US20230396555A1 (en) | Split packet router for time sensitive networking | |
| Chuan-Sheng et al. | Implementation of a general ethernet interface for embedded system | |
| Tang et al. | Performance Analysis of Critical Traffic of Airborne Integration TTE Network | |
| Simon et al. | Comparison of Real-Time, Mobile Data Bus Architectures | |
| Zhao et al. | FlexRay Bus-Based Integrated Technology on Airborne Utility Management Computer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |