CN117375592A - Device with parasitic capacitance releasing circuit and parasitic capacitance releasing circuit - Google Patents

Device with parasitic capacitance releasing circuit and parasitic capacitance releasing circuit Download PDF

Info

Publication number
CN117375592A
CN117375592A CN202311309554.5A CN202311309554A CN117375592A CN 117375592 A CN117375592 A CN 117375592A CN 202311309554 A CN202311309554 A CN 202311309554A CN 117375592 A CN117375592 A CN 117375592A
Authority
CN
China
Prior art keywords
circuit
voltage
parasitic capacitance
resistor
pmos tube
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202311309554.5A
Other languages
Chinese (zh)
Inventor
陈波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Core Microelectronics Kunshan Co ltd
Original Assignee
Core Microelectronics Kunshan Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Core Microelectronics Kunshan Co ltd filed Critical Core Microelectronics Kunshan Co ltd
Priority to CN202311309554.5A priority Critical patent/CN117375592A/en
Publication of CN117375592A publication Critical patent/CN117375592A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching
    • H03K17/041—Modifications for accelerating switching without feedback from the output circuit to the control circuit
    • H03K17/04106—Modifications for accelerating switching without feedback from the output circuit to the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0081—Power supply means, e.g. to the switch driver

Abstract

The embodiment of the application provides a device with a parasitic capacitance releasing circuit and the parasitic capacitance releasing circuit. The device comprises a parasitic capacitance releasing circuit, a driving circuit and a device circuit body; the positive voltage end of the driving circuit is connected with the positive voltage PVDD, the negative voltage end of the driving circuit is connected with the negative voltage NVDD, and the driving circuit is connected with the device circuit body to supply power for the device circuit body; the parasitic capacitance releasing circuit is connected with the positive pressure end and the negative pressure end of the driving circuit; the parasitic capacitance releasing circuit is used for starting when the device is powered down, and parasitic capacitance in the device circuit body is released through the positive pressure end and the negative pressure end of the driving circuit. The embodiment of the application solves the technical problem that the traditional device needs to wait for a very long time when being restarted due to parasitic capacitance in the device circuit body after the power supply is powered down.

Description

Device with parasitic capacitance releasing circuit and parasitic capacitance releasing circuit
Technical Field
The application relates to the technical field of radio frequency components, in particular to a device with a parasitic capacitance releasing circuit and the parasitic capacitance releasing circuit.
Background
Radio frequency switches and tuners are the most commonly used radio frequency components. The wireless communication system is used for channel switching and receiving and transmitting state switching in a radio frequency link, and is widely applied to the fields of Internet of things, communication base stations, small base stations, repeater stations, test instruments, radars, wiFi, RFID and the like. The radio frequency antenna switch is connected between the antenna and the radio frequency processing circuit and used for switching the working state of the antenna, switching the frequency band and receiving and transmitting signals. Through the switch, signals with different frequency bands and different systems can be separated and then output to different systems of the mobile phone for processing, so that mutual interference among different signals is reduced, and signal receiving sensitivity is improved. The radio frequency switch is an essential key device of the radio frequency front end of the mobile phone, and the quality of the performance directly determines the signal quality of the mobile phone terminal. The SOI process has advantages that are not comparable to GaAs processes due to its high speed, high isolation characteristics, and excellent radiation resistance characteristics. In recent years, in the field of wireless communication, SOI technology has become the preferred technology for radio frequency switches. The rf switch and Tuner require driving a large-sized semiconductor switch, which has a large parasitic capacitance, and thus the rf switch and Tuner often wait for a very long time when they are restarted after power is turned off.
The Chinese language of SOI technology is called as insulator-on-silicon technology, and SOI CMOS technology. The Chinese language of the GaAs process is called the gallium arsenide process, also called the GaAs MMIC process, and is an important process for preparing microwave and millimeter wave devices.
Therefore, the conventional rf switch and Tuner need to wait a very long time when they are restarted due to parasitic capacitance in the device circuit body after the power is turned off, which is a technical problem that those skilled in the art need to solve.
The above information disclosed in the background section is only for enhancement of understanding of the background of the application and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.
Disclosure of Invention
The embodiment of the application provides a device with a parasitic capacitance releasing circuit and the parasitic capacitance releasing circuit, so as to solve the technical problem that a traditional device needs to wait for a very long time when being restarted due to parasitic capacitance in a device circuit body after power is powered down.
The embodiment of the application provides a device with a parasitic capacitance releasing circuit, which comprises a parasitic capacitance releasing circuit, a driving circuit and a device circuit body; the positive voltage end of the driving circuit is connected with the positive voltage PVDD, the negative voltage end of the driving circuit is connected with the negative voltage NVDD, and the driving circuit is connected with the device circuit body to supply power for the device circuit body;
the parasitic capacitance releasing circuit is connected with the positive pressure end and the negative pressure end of the driving circuit;
the parasitic capacitance releasing circuit is used for starting when the device is powered down, and parasitic capacitance in the device circuit body is released through the positive pressure end and the negative pressure end of the driving circuit.
In an implementation, the release parasitic capacitance circuit includes a positive voltage release circuit, the positive voltage release circuit including:
an inverter INV1;
a source end of the fifth PMOS tube MP5 is connected with the positive pressure PVDD, and a control end and a drain end of the fifth PMOS tube MP5 are connected with a power supply of the inverter INV1;
the drain terminal of the fourth NMOS tube MN4 is connected with the positive pressure PVDD, and the source terminal of the fourth NMOS tube MN4 is grounded;
the input end of the inverter INV1 is connected to the enable signal EN, and the output end of the inverter INV1 is connected to the control end of the fourth NMOS MN 4.
The parasitic capacitance releasing circuit further comprises a negative pressure first releasing circuit, and the negative pressure first releasing circuit comprises:
the control end of the first NMOS tube MN1 is grounded, and the source end of the first NMOS tube MN1 is connected with the negative pressure end of the driving circuit;
the drain end of the first NMOS tube MN1 is connected with the drain end of the second PMOS tube MP 2;
the source end of the second PMOS tube MP2 is connected with the drain end of the first PMOS tube MP1, and the source end of the first PMOS tube MP1 is grounded;
when the device enters a closing state, the first NMOS tube MN1 is kept on, the second PMOS tube MP2 is controlled to be on, the first PMOS tube MP1 is controlled to be on, and the negative pressure first release circuit is discharged.
In implementation, when the device works normally, the first NMOS tube MN1 is turned on, the second PMOS tube MP2 is controlled to be turned off, the first PMOS tube MP1 is controlled to be turned off, and the negative pressure first release circuit is turned off.
In practice, the device with the free parasitic capacitance circuit further comprises:
the first bias circuit comprises a first resistor R1 and a second resistor R2 which are sequentially connected in series between a positive voltage PVDD and a negative voltage NVDD, wherein the voltage at the joint of the first resistor R1 and the second resistor R2 is used as a first bias voltage VB1; the control end of the first PMOS tube MP1 is connected with a first bias voltage VB1;
the second bias circuit comprises a third resistor R3 and a fourth resistor R4 which are sequentially connected in series between an input voltage VDDIN and a negative voltage NVDD, wherein the voltage at the joint of the third resistor R3 and the fourth resistor R4 is used as a second bias voltage VB2; the control end of the second PMOS tube MP2 is connected with a second bias voltage VB2.
In implementation, the resistance of the first resistor R1 is equal to the resistance of the second resistor R2, and the resistance of the third resistor R3 is equal to the resistance of the fourth resistor R4;
positive voltage pvdd= -negative voltage NVDD, input voltage VDDIN < positive voltage PVDD.
In practice, the device with the free parasitic capacitance circuit further comprises:
an input voltage VDDIN generating circuit controlled by an enable signal EN, connected to a power supply voltage VDD and outputting the input voltage VDDIN;
a positive voltage PVDD generating circuit connected between the power supply voltage VDD and the ground to generate a positive voltage PVDD;
and a negative voltage NVDD generating circuit connected between the power supply voltage VDD and the ground to generate a negative voltage NVDD.
The embodiment of the application also provides the following technical scheme:
the parasitic capacitance releasing circuit is used for being connected with a positive pressure end and a negative pressure connecting end of an external device, wherein the positive pressure end of the device is connected with a positive pressure PVDD and the negative pressure connecting end of the device is connected with a negative pressure NVDD;
the parasitic capacitance releasing circuit is used for starting when the device is powered down, and parasitic capacitance in the device circuit body is released through the positive pressure end and the negative pressure end of the driving circuit.
In an implementation, the parasitic capacitance releasing circuit includes a negative pressure first releasing circuit, the negative pressure first releasing circuit includes:
the control end of the first NMOS tube MN1 is grounded, and the source end of the first NMOS tube MN1 is connected with the negative pressure end of the driving circuit;
the drain end of the first NMOS tube MN1 is connected with the drain end of the second PMOS tube MP 2;
the source end of the second PMOS tube MP2 is connected with the drain end of the first PMOS tube MP1, and the source end of the first PMOS tube MP1 is grounded;
when the device enters a closing state, the first NMOS tube MN1 is kept on, the second PMOS tube MP2 is controlled to be on, the first PMOS tube MP1 is controlled to be on, and the negative pressure first release circuit is discharged;
when the device works normally, the first NMOS tube MN1 is conducted, the second PMOS tube MP2 is controlled to be closed, the first PMOS tube MP1 is controlled to be closed, and the negative pressure first release circuit is closed.
In an implementation, the release parasitic capacitance circuit further includes:
the first bias circuit comprises a first resistor R1 and a second resistor R2 which are sequentially connected in series between a positive voltage PVDD and a negative voltage NVDD, wherein the voltage at the joint of the first resistor R1 and the second resistor R2 is used as a first bias voltage VB1; the control end of the first PMOS tube MP1 is connected with a first bias voltage VB1;
the second bias circuit comprises a third resistor R3 and a fourth resistor R4 which are sequentially connected in series between an input voltage VDDIN and a negative voltage NVDD, wherein the voltage at the joint of the third resistor R3 and the fourth resistor R4 is used as a second bias voltage VB2; the control end of the second PMOS tube MP2 is connected with a second bias voltage VB2;
the resistance value of the first resistor R1 is equal to the resistance value of the second resistor R2, and the resistance value of the third resistor R3 is equal to the resistance value of the fourth resistor R4; positive voltage pvdd= -negative voltage NVDD, input voltage VDDIN < positive voltage PVDD.
By adopting the technical scheme, the embodiment of the application has the following technical effects:
the parasitic capacitance releasing circuit is connected with the positive pressure end and the negative pressure end of the driving circuit and is started when the device is powered down, and parasitic capacitance in the device circuit body is released through the positive pressure end and the negative pressure end of the driving circuit. The positive electricity of the positive voltage end and the negative electricity of the negative voltage end of the driving circuit are released through the nodes of the positive voltage end and the negative voltage end of the driving circuit, so that parasitic capacitance in the device circuit body is released. Therefore, the parasitic capacitance in the device can be discharged in a short time after the power supply is powered down, so that the device can be quickly started again.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
FIG. 1 is a schematic diagram of a device with a free-standing parasitic capacitance circuit as a Tuner/RF switch in an embodiment of the present application;
FIG. 2 is a schematic diagram of a negative pressure first release circuit, a first bias circuit, and a second bias circuit of the release parasitic capacitance circuit shown in FIG. 1;
FIG. 3 is a schematic diagram of a negative pressure second release circuit of the parasitic capacitance release circuit shown in FIG. 1;
FIG. 4 is a schematic diagram of a positive voltage discharge circuit of the discharge parasitic capacitance circuit of FIG. 1;
FIG. 5 is an output waveform of a Tuner/RF switch power down and power up control voltage with a free parasitic capacitance circuit;
FIG. 6 is a diagram showing the output waveform of a conventional Tuner/RF switch power-down and power-up control voltage;
FIG. 7 is a waveform diagram showing a Tuner/RF switch with a parasitic capacitance releasing circuit powered down and then powered up for a second start up;
FIG. 8 is a waveform diagram showing a conventional Tuner/RF switch powered down and then powered up for a second start;
fig. 9 is a waveform diagram of a conventional Tuner/rf switch with failed secondary start-up after power down and power up.
Detailed Description
In order to make the technical solutions and advantages of the embodiments of the present application more apparent, the following detailed description of exemplary embodiments of the present application is given with reference to the accompanying drawings, and it is apparent that the described embodiments are only some of the embodiments of the present application and not exhaustive of all the embodiments. It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other.
Example 1
Embodiments of the present application provide a device with a free parasitic capacitance circuit. The device may be a radio frequency switch with a free parasitic capacitance circuit as shown in fig. 1, or a Tuner with a free parasitic capacitance circuit. The device with the parasitic capacitance release circuit according to the embodiment of the present application is not limited to the radio frequency switch and Tuner, and the parasitic capacitance release circuit may be provided as a device with the parasitic capacitance release circuit as long as the device is turned on in a short time after power is turned off.
As shown in fig. 1, the device with the parasitic capacitance releasing circuit includes:
releasing the parasitic capacitance circuit;
a positive pressure PVDD generation circuit;
a negative pressure NVDD generation circuit;
the drive circuit and the radio frequency switch core are formed by circuits such as a radio frequency switch core; the driving circuit is connected between the positive pressure PVDD and the negative pressure NVDD, the driving circuit is connected with the device circuit body to supply power for the device circuit body, and the radio frequency switch core tube is used as the device circuit body.
The radio frequency switch with the parasitic capacitance releasing circuit shown in fig. 1 is based on the conventional radio frequency switch, and the parasitic capacitance releasing circuit is added. When the radio frequency switch shown in fig. 1 is powered down, the parasitic capacitance releasing circuit (fast discharge circuit) is started to release the charges in the parasitic capacitance in the core tube (RF switch core) of the radio frequency switch, so that the voltage of each node after the radio frequency switch is powered down can be quickly recovered.
In practice, as shown in fig. 1, a positive voltage PVDD generating circuit is connected between a power supply voltage VDD and ground to generate a positive voltage PVDD;
and a negative voltage NVDD generating circuit connected between the power supply voltage VDD and the ground to generate a negative voltage NVDD.
In practice, as shown in fig. 1, a parasitic capacitance releasing circuit is connected to a positive voltage end and a negative voltage end of the driving circuit;
the parasitic capacitance releasing circuit is used for starting when the device is powered down, and parasitic capacitance in the device circuit body is released through the positive pressure end and the negative pressure end of the driving circuit.
The parasitic capacitance releasing circuit is connected with the positive pressure end and the negative pressure end of the driving circuit and is started when the device is powered down, and parasitic capacitance in the device circuit body is released through the positive pressure end and the negative pressure end of the driving circuit. The positive electricity of the positive voltage end and the negative electricity of the negative voltage end of the driving circuit are released through the nodes of the positive voltage end and the negative voltage end of the driving circuit, so that parasitic capacitance in the device circuit body is released. Therefore, the parasitic capacitance in the device can be discharged in a short time after the power supply is powered down, so that the device can be quickly started again.
The free parasitic capacitance circuit includes fig. 2 and 3.
In implementation, as shown in fig. 1, the positive voltage end of the driving circuit is connected with the positive voltage PVDD and the negative voltage end is connected with the negative voltage NVDD.
As shown in fig. 2, the discharge parasitic capacitance circuit includes a negative pressure first discharge circuit.
As shown in fig. 2, the negative pressure first release circuit DS1 includes:
the control end of the first NMOS tube MN1 is grounded, and the source end of the first NMOS tube MN1 is connected with the negative pressure end of the driving circuit;
the drain end of the first NMOS tube MN1 is connected with the drain end of the second PMOS tube MP 2; the control end of the second PMOS tube MP2 is connected with a second bias voltage VB2;
the source end of the second PMOS tube MP2 is connected with the drain end of the first PMOS tube MP1, the source end of the first PMOS tube MP1 is grounded, and the control end of the first PMOS tube MP1 is connected with a first bias voltage VB1;
when the device enters a closing state, the first NMOS tube MN1 is kept on, the second bias voltage VB2 controls the second PMOS tube MP2 to be on, and the first bias voltage VB1 controls the first PMOS tube MP1 to be on, so that the negative pressure first release circuit discharges.
The device with the free parasitic capacitance circuit of the embodiments of the present application,
when the device works normally:
the positive pressure end of the driving circuit is connected with the positive pressure PVDD and the negative pressure end is connected with the negative pressure NVDD. When the device works normally, the source end of the first NMOS tube MN1 is connected with the negative pressure end of the driving circuit, the control end of the first NMOS tube MN1 is grounded, and at the moment, the first NMOS tube MN1 is conducted. The second bias voltage VB2 controls the second PMOS tube MP2 to be turned off, and the first bias voltage VB1 controls the first PMOS tube MP1 to be turned off. That is, when the device works normally, the first NMOS tube MN1 is turned on, the second PMOS tube MP2 is turned off, the first PMOS tube MP1 is turned off, the whole negative pressure first release circuit is turned off, and the negative pressure end of the driving circuit cannot leak electricity to the ground through the negative pressure first release circuit DS 1.
When the device enters the off state, the positive voltage PVDD and the input voltage VDDIN are both pulled to zero potential by the enable signal EN, and the change speed of the negative voltage end of the driving circuit is slow. The source end connection of the first NMOS tube MN1 still keeps negative pressure, the control end of the first NMOS tube MN1 is grounded, and at the moment, the first NMOS tube MN1 is kept on. The second bias voltage VB2 controls the second PMOS tube MP2 to be conducted, and the first bias voltage VB1 controls the first PMOS tube MP1 to be conducted, so that the negative pressure first release circuit discharges. When the device enters a closed state, the first NMOS tube MN1 is kept on, the second PMOS tube MP2 is controlled to be on, the first PMOS tube MP1 is controlled to be on, the whole negative pressure first release circuit is communicated, the negative pressure end of the driving circuit is connected with the ground so that the potential is reduced to zero, namely the node of the negative pressure end of the driving circuit is rapidly discharged. The driving circuit is connected with the device circuit body, so that the driving circuit and the device circuit body are used as a whole to carry out negative pressure rapid discharge through the negative pressure first release circuit. Therefore, the parasitic capacitance in the device can be discharged in a short time after the power supply is powered down, so that the device can be quickly started again.
In practice, as shown in fig. 2, the parasitic capacitance releasing circuit further includes:
the first bias circuit comprises a first resistor R1 and a second resistor R2 which are sequentially connected in series between a positive voltage PVDD and a negative voltage NVDD, wherein the resistance value of the first resistor R1 is equal to that of the second resistor R2, and the voltage at the joint of the first resistor R1 and the second resistor R2 is used as a first bias voltage VB1; the control end of the first PMOS tube MP1 is connected with a first bias voltage VB1;
the second bias circuit comprises a third resistor R3 and a fourth resistor R4 which are sequentially connected in series between an input voltage VDDIN and a negative voltage NVDD, wherein the resistance value of the third resistor R3 is equal to that of the fourth resistor R4, and the voltage at the joint of the third resistor R3 and the fourth resistor R4 is used as a second bias voltage VB2; the control end of the second PMOS tube MP2 is connected with a second bias voltage VB2;
positive voltage pvdd= -negative voltage NVDD, input voltage VDDIN < positive voltage PVDD.
Correspondingly, vb1= (pvdd+nvdd)/2, vb2= (vddin+nvdd)/2.
For the negative pressure first release circuit DS1, when the device is operating normally:
because the source end of the first NMOS tube MN1 is connected with the negative pressure end of the driving circuit, the control end of the first NMOS tube MN1 is grounded, and at the moment, the first NMOS tube MN1 is conducted;
since positive pressure pvdd= -negative pressure NVDD, vb1= (pvdd+nvdd)/2=0, i.e. when the first PMOS tube MP1 is closed;
because the input voltage VDDIN is less than the positive voltage PVDD, the second bias voltage VB2 is less than the first bias voltage VB1, VB2 is less than 0, and the second PMOS transistor MP2 is turned off.
That is, when the device with the parasitic capacitance releasing circuit works normally, the first NMOS tube MN1 is turned on, the first PMOS tube MP1 is turned off, the second PMOS tube MP2 is turned off, and the whole negative pressure first releasing circuit DS1 is turned off. Thus, the negative voltage end of the driving circuit and the negative voltage NVDD do not leak to the ground through the negative voltage first release circuit DS 1.
For the negative pressure first release circuit DS1, when the device enters the off state:
both positive voltage PVDD and input voltage VDDIN are pulled quickly to zero by enable signal EN, and the negative voltage NVDD changes slowly. Therefore, vb1= (pvdd+nvdd)/2= (0+nvdd)/2=nvdd/2, i.e. when the first PMOS tube MP1 is turned on;
VB 2= (VDDIN+NVDD)/2= (0+NVDD)/2=NVDD/2, and then the second PMOS tube MP2 is turned on;
because the source end of the first NMOS tube MN1 is connected with the negative pressure end of the driving circuit, the change speed of the negative pressure NVDD is slower, so that the first NMOS tube MN1 is kept on.
When the device enters a closed state, the first NMOS tube MN1 is conducted, the first PMOS tube MP1 is conducted, the second PMOS tube MP2 is conducted, and the whole negative pressure first release circuit DS1 is conducted, so that the negative pressure end of the driving circuit and the negative pressure NVDD are connected with the ground to enable the potential to be reduced, namely the node of the negative pressure end of the driving circuit is rapidly discharged. When the drop is zero, the first NMOS transistor MN1 is turned off.
In implementation, as shown in fig. 3, the parasitic capacitance releasing circuit further includes a negative pressure second releasing circuit DS2, where the negative pressure second releasing circuit DS2 includes:
the drain end of the third NMOS tube MN3 is connected with the drain end of the fourth PMOS tube MP4, the source end of the third NMOS tube MN3 is connected with the negative pressure end of the driving circuit, and the control ends of the third NMOS tube MN3 and the fourth PMOS tube MP4 are grounded;
the drain end of the third PMOS tube MP3 is connected with the drain end of the second NMOS tube MN2, the source end of the third PMOS tube MP3, the control end of the third PMOS tube MP3 and the control end of the second NMOS tube MN2 are connected with an input voltage VDDIN, and the source end of the second NMOS tube MN2 is grounded;
the drain end of the third PMOS MP3 is connected to the source end of the fourth PMOS MP 4.
For the negative-pressure second discharging circuit DS2, when the device having the discharging parasitic capacitance circuit operates normally:
the positive pressure end of the driving circuit is connected with the positive pressure PVDD and the negative pressure end is connected with the negative pressure NVDD. When the device works normally, the source end of the third NMOS tube MN3 is connected with the negative pressure end of the driving circuit, the control end of the third NMOS tube MN3 is grounded, and at the moment, the third NMOS tube MN3 is conducted.
The third PMOS transistor MP3 is turned off, the second NMOS transistor MN2 is in a turned-on state, and the output voltage of the inverter formed by the third PMOS transistor MP3 and the second NMOS transistor MN2 is 0V, that is, the source input of the fourth PMOS transistor MP4 is zero, so that the fourth PMOS transistor MP4 is in a turned-off state.
That is, when the device with the parasitic capacitance releasing circuit works normally, the third PMOS transistor MP3 is turned off, the second NMOS transistor MN2 is turned on, the fourth PMOS transistor MP4 is turned off, the third NMOS transistor MN3 is turned on, and the whole negative pressure second releasing circuit DS2 is turned off. Thus, the negative voltage NVDD does not leak the input voltage VDDin through the negative voltage second release circuit DS 2.
When the device with the parasitic capacitance releasing circuit enters the off state, both the positive voltage PVDD and the input voltage VDDIN are pulled quickly to zero potential by the enable signal EN. In the process that the input voltage VDDIN is pulled down to zero, the third PMOS MP3 is turned on briefly, so that the fourth PMOS MP4 is turned on. The second NMOS transistor MN2 is in a conducting state, the third NMOS transistor MN3 is in a conducting state, and the whole negative pressure second release circuit DS2 is conducted. In this way, a discharge process of the negative pressure end of the driving circuit and the negative pressure NVDD through the negative pressure second discharging circuit DS2 is achieved.
In practice, as shown in fig. 4, the parasitic capacitance releasing circuit further includes a positive voltage releasing circuit, and the positive voltage releasing circuit includes:
an inverter INV1;
a source end of the fifth PMOS tube MP5 is connected with a positive voltage end of the driving circuit, and a control end and a drain end of the fifth PMOS tube MP5 are connected with a power supply of the inverter INV1;
the drain end of the fourth NMOS tube MN4 is connected with the positive pressure end of the driving circuit, and the source end of the fourth NMOS tube MN4 is grounded;
the input end of the inverter INV1 is connected to the enable signal EN, and the output end of the inverter INV1 is connected to the control end of the fourth NMOS MN 4.
The positive voltage PVDD discharges to the ground through three devices of a fourth NMOS tube MN4, a fifth PMOS tube MP5 and an inverter INV1 of the power supply power-down release circuit.
When the device with the parasitic capacitance releasing circuit works normally, the voltage Ven of the enable signal EN is high voltage, at this time, the output of the output end of the inverter INV1 is 0V, and the fourth NMOS transistor MN4 is in the off state. The positive voltage end of the driving circuit cannot discharge through the power supply power-down release circuit.
When the power supply of the device with the parasitic capacitance releasing circuit enters the power-down state, the voltage Ven of the enable signal EN is 0V, and at this time, the output voltage of the output end of the inverter INV1 is pvdd—the threshold voltage Vth of the fifth PMOS transistor MP5, so that the fourth NMOS transistor MN4 enters the on state, and the positive voltage end of the driving circuit rapidly discharges to the ground. I.e. the positive voltage end of the driving circuit is discharged quickly. The driving circuit is connected with the device circuit body, so that the driving circuit and the device circuit body are used as a whole to carry out positive pressure rapid discharge through the positive pressure release circuit. Therefore, the parasitic capacitance in the device can be discharged in a short time after the power supply is powered down, so that the device can be quickly started again.
In implementation, as shown in fig. 1, the parasitic capacitance releasing circuit further includes an input voltage VDDIN generating circuit, which is controlled by the enable signal EN, connected to the power supply voltage VDD and outputs the input voltage VDDIN.
In integrated circuits, powering down and powering down are two distinct operations. The power-down refers to that the power supply of the chip is turned off by controlling an external power supply or an internal power supply management circuit, and the chip is completely disconnected from the outside so that the chip does not work any more. Whereas shutdown generally refers to disabling some functions or modules of a chip by software or hardware control, thereby reducing power consumption and enhancing reliability.
Powering down in this application refers to powering down a device having a free parasitic capacitance circuit by controlling an external power supply or an internal power management circuit.
FIG. 5 is an output waveform of a Tuner/RF switch power down and power up control voltage with a free parasitic capacitance circuit; fig. 6 is a waveform of output voltage of a conventional Tuner/rf switch power-down and power-up control.
As can be seen from fig. 5, when the Tuner/rf switch with the stray capacitance releasing circuit is operating normally, the voltage of the NVDD is-2.7V and the time point is 50 microseconds. After the Tuner/radio switch with the stray capacitance releasing circuit is powered down, the voltage of the NVDD drops and drops to-1.263329 v at point 342.1947 us. I.e. the voltage of the NVDD drops by 2.7-1.263329 = 1.436671v in the time interval 342.1947-50= 292.1947 us.
In fig. 6, the voltage of NVDD drops by 2.7-1.557216 = 1.142784v for the time interval 345.9735-50= 295.9735 us.
Thus, in FIGS. 5 and 6, the voltage of the NVDD in FIG. 5 drops by a greater voltage in a shorter time. That is, the Tuner/radio frequency switch with the parasitic capacitance releasing circuit is used to power down and power up the control voltage to restore to the initial state more quickly at the same time interval.
Fig. 7 is a waveform diagram showing a Tuner/rf switch with a parasitic capacitance release circuit that is powered down and then powered up for a second start-up. As shown in fig. 7, the Tuner/rf switch with the parasitic capacitance releasing circuit is turned on twice on the falling edge of the enable signal, and the final start is successful, and the start voltage is relatively gentle.
Fig. 8 is a waveform diagram showing a conventional Tuner/rf switch powered down and then powered up for a second start. As shown in fig. 8, the conventional Tuner/rf switch is turned on twice at the falling edge of the enable signal, and the final start is successful, and the start voltage is steep.
As can be seen from fig. 7 and 8, the turn-on voltage of the Tuner/rf switch with the parasitic capacitance releasing circuit is smoother during the secondary start.
Fig. 9 is a waveform diagram of a conventional Tuner/rf switch with failed secondary start-up after power down and power up. As shown in fig. 9, the conventional Tuner/rf switch is turned on twice on the falling edge of the enable signal, and after the start of the second start, the voltage of the pvdd is not returned to-2.8V, and the voltage of the pvdd is not returned to 2.8V, so that the second start fails.
In the description of the present application and its embodiments, it should be understood that the terms "top," "bottom," "height," and the like indicate an orientation or positional relationship based on that shown in the drawings, and are merely for convenience of description and to simplify the description, rather than to indicate or imply that the devices or elements referred to must have a particular orientation, be configured and operated in a particular orientation, and thus should not be construed as limiting the present application.
In this application and in its embodiments, the terms "disposed," "mounted," "connected," "secured," and the like are to be construed broadly and include, for example, either permanently connected, removably connected, or integrally formed, unless otherwise explicitly stated and defined as such; the device can be mechanically connected, electrically connected and communicated; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.
In this application and in its embodiments, unless expressly stated or limited otherwise, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features not being in direct contact but being in contact with each other through additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is less level than the second feature.
The above disclosure provides many different embodiments or examples for implementing different structures of the present application. The components and arrangements of specific examples are described above in order to simplify the disclosure of this application. Of course, they are merely examples and are not intended to limit the present application. Furthermore, the present application may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not in themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present application provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize the application of other processes and/or the use of other materials.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.

Claims (11)

1. A device having a release parasitic capacitance circuit, comprising a release parasitic capacitance circuit, a drive circuit, and a device circuit body; the positive voltage end of the driving circuit is connected with the positive voltage PVDD, the negative voltage end of the driving circuit is connected with the negative voltage NVDD, and the driving circuit is connected with the device circuit body to supply power for the device circuit body;
the parasitic capacitance releasing circuit is connected with the positive pressure end and the negative pressure end of the driving circuit;
the parasitic capacitance releasing circuit is used for starting when the device is powered down, and parasitic capacitance in the device circuit body is released through the positive pressure end and the negative pressure end of the driving circuit.
2. The device of claim 1, wherein the release parasitic capacitance circuit comprises a positive voltage release circuit comprising:
an inverter INV1;
a source end of the fifth PMOS tube MP5 is connected with the positive pressure PVDD, and a control end and a drain end of the fifth PMOS tube MP5 are connected with a power supply of the inverter INV1;
the drain terminal of the fourth NMOS tube MN4 is connected with the positive pressure PVDD, and the source terminal of the fourth NMOS tube MN4 is grounded;
the input end of the inverter INV1 is connected to the enable signal EN, and the output end of the inverter INV1 is connected to the control end of the fourth NMOS MN 4.
3. The device with a release parasitic capacitance circuit of claim 2, wherein the release parasitic capacitance circuit further comprises a negative pressure first release circuit comprising:
the control end of the first NMOS tube MN1 is grounded, and the source end of the first NMOS tube MN1 is connected with the negative pressure end of the driving circuit;
the drain end of the first NMOS tube MN1 is connected with the drain end of the second PMOS tube MP 2;
the source end of the second PMOS tube MP2 is connected with the drain end of the first PMOS tube MP1, and the source end of the first PMOS tube MP1 is grounded;
when the device enters a closing state, the first NMOS tube MN1 is kept on, the second PMOS tube MP2 is controlled to be on, the first PMOS tube MP1 is controlled to be on, and the negative pressure first release circuit is discharged.
4. The device with a parasitic capacitance releasing circuit according to claim 3, wherein when the device is operating normally, the first NMOS transistor MN1 is turned on, the second PMOS transistor MP2 is controlled to be turned off, the first PMOS transistor MP1 is controlled to be turned off, so that the negative pressure first releasing circuit is turned off.
5. The device with a release parasitic capacitance circuit of claim 4, wherein the release parasitic capacitance circuit further comprises:
the first bias circuit comprises a first resistor R1 and a second resistor R2 which are sequentially connected in series between a positive voltage PVDD and a negative voltage NVDD, wherein the voltage at the joint of the first resistor R1 and the second resistor R2 is used as a first bias voltage VB1; the control end of the first PMOS tube MP1 is connected with a first bias voltage VB1;
the second bias circuit comprises a third resistor R3 and a fourth resistor R4 which are sequentially connected in series between an input voltage VDDIN and a negative voltage NVDD, wherein the voltage at the joint of the third resistor R3 and the fourth resistor R4 is used as a second bias voltage VB2; the control end of the second PMOS tube MP2 is connected with a second bias voltage VB2.
6. The device with a parasitic capacitance releasing circuit according to claim 5, wherein the resistance of the first resistor R1 is equal to the resistance of the second resistor R2, and the resistance of the third resistor R3 is equal to the resistance of the fourth resistor R4;
positive voltage pvdd= -negative voltage NVDD, input voltage VDDIN < positive voltage PVDD.
7. The device with a release parasitic capacitance circuit according to any one of claims 1 to 6, further comprising:
an input voltage VDDIN generating circuit controlled by an enable signal EN, connected to a power supply voltage VDD and outputting the input voltage VDDIN;
a positive voltage PVDD generating circuit connected between the power supply voltage VDD and the ground to generate a positive voltage PVDD;
and a negative voltage NVDD generating circuit connected between the power supply voltage VDD and the ground to generate a negative voltage NVDD.
8. The parasitic capacitance releasing circuit is characterized by being connected to a positive pressure end and a negative pressure connecting end of an external device, wherein the positive pressure end of the device is connected with a positive pressure PVDD and the negative pressure connecting end of the device is connected with a negative pressure NVDD;
the parasitic capacitance releasing circuit is used for starting when the device is powered down, and parasitic capacitance in the device circuit body is released through the positive pressure end and the negative pressure end of the driving circuit.
9. The free-standing parasitic capacitance circuit according to claim 8, further comprising a positive-voltage release circuit, the positive-voltage release circuit comprising:
an inverter INV1;
a source end of the fifth PMOS tube MP5 is connected with the positive pressure PVDD, and a control end and a drain end of the fifth PMOS tube MP5 are connected with a power supply of the inverter INV1;
the drain terminal of the fourth NMOS tube MN4 is connected with the positive pressure PVDD, and the source terminal of the fourth NMOS tube MN4 is grounded;
the input end of the inverter INV1 is connected to the enable signal EN, and the output end of the inverter INV1 is connected to the control end of the fourth NMOS MN 4.
10. The free-standing parasitic capacitance circuit according to claim 9, further comprising a negative-pressure first release circuit, the negative-pressure first release circuit comprising:
the control end of the first NMOS tube MN1 is grounded, and the source end of the first NMOS tube MN1 is connected with the negative pressure end of the driving circuit;
the drain end of the first NMOS tube MN1 is connected with the drain end of the second PMOS tube MP 2;
the source end of the second PMOS tube MP2 is connected with the drain end of the first PMOS tube MP1, and the source end of the first PMOS tube MP1 is grounded;
when the device enters a closing state, the first NMOS tube MN1 is kept on, the second PMOS tube MP2 is controlled to be on, the first PMOS tube MP1 is controlled to be on, and the negative pressure first release circuit is discharged;
when the device works normally, the first NMOS tube MN1 is conducted, the second PMOS tube MP2 is controlled to be closed, the first PMOS tube MP1 is controlled to be closed, and the negative pressure first release circuit is closed.
11. The free-standing parasitic capacitance circuit according to claim 10, further comprising:
the first bias circuit comprises a first resistor R1 and a second resistor R2 which are sequentially connected in series between a positive voltage PVDD and a negative voltage NVDD, wherein the voltage at the joint of the first resistor R1 and the second resistor R2 is used as a first bias voltage VB1; the control end of the first PMOS tube MP1 is connected with a first bias voltage VB1;
the second bias circuit comprises a third resistor R3 and a fourth resistor R4 which are sequentially connected in series between an input voltage VDDIN and a negative voltage NVDD, wherein the voltage at the joint of the third resistor R3 and the fourth resistor R4 is used as a second bias voltage VB2; the control end of the second PMOS tube MP2 is connected with a second bias voltage VB2;
the resistance value of the first resistor R1 is equal to the resistance value of the second resistor R2, and the resistance value of the third resistor R3 is equal to the resistance value of the fourth resistor R4; positive voltage pvdd= -negative voltage NVDD, input voltage VDDIN < positive voltage PVDD.
CN202311309554.5A 2023-10-11 2023-10-11 Device with parasitic capacitance releasing circuit and parasitic capacitance releasing circuit Pending CN117375592A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311309554.5A CN117375592A (en) 2023-10-11 2023-10-11 Device with parasitic capacitance releasing circuit and parasitic capacitance releasing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311309554.5A CN117375592A (en) 2023-10-11 2023-10-11 Device with parasitic capacitance releasing circuit and parasitic capacitance releasing circuit

Publications (1)

Publication Number Publication Date
CN117375592A true CN117375592A (en) 2024-01-09

Family

ID=89401577

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311309554.5A Pending CN117375592A (en) 2023-10-11 2023-10-11 Device with parasitic capacitance releasing circuit and parasitic capacitance releasing circuit

Country Status (1)

Country Link
CN (1) CN117375592A (en)

Similar Documents

Publication Publication Date Title
US8649741B2 (en) Radio frequency module having an isolation mode between transmission mode and power saving mode
US9111601B2 (en) Negative voltage generators
US9177182B2 (en) Semiconductor device for wireless communication
US8289072B2 (en) Semiconductor switch
WO2003107551A1 (en) High frequency switch circuit and mobile communication terminal device using the same
JP2010103971A (en) High-frequency semiconductor switch device
TWI647910B (en) Field effect transistor switching circuit
CN105024677A (en) Rf switch circuit
CN101098135A (en) Semiconductor integrated circuit device and RF moudle
US20150084702A1 (en) Electrostatic discharge (esd) circuitry
CN117097310B (en) Device with quick stabilizing circuit of powering down and quick stabilizing circuit of powering down
CN117375592A (en) Device with parasitic capacitance releasing circuit and parasitic capacitance releasing circuit
JP5358476B2 (en) Antenna switch and high-frequency module incorporating it
US10514742B2 (en) Power down signal generating circuit
CN216390968U (en) Radio frequency driving circuit, radio frequency switch and radio frequency chip
US11258445B2 (en) Radio frequency apparatus and voltage generating device thereof
JP2012186618A (en) Semiconductor switch and wireless device
Cho et al. Negative charge-pump based antenna switch controller using 0.18 µm SOI CMOS technology
Ferschischi et al. A power efficient 60-GHz super-regenerative oscillator with 10-GHz switching rate in 22-nm FD-SOI CMOS
CN104935316A (en) Radio frequency switch used for controlling sending and receiving path switching, radio frequency system and operation method
JP2013115790A (en) High-frequency semiconductor switch and terminal device
CN112054815B (en) Wireless device, transceiving radio frequency circuit thereof and ESD protection circuit thereof
CN111416584A (en) High-frequency amplifier circuit and semiconductor device
CN220711465U (en) SOI CMOS radio frequency switch circuit structure
EP2528022A1 (en) Transponder with a modulator

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination