CN117373924A - Gallium oxide field effect transistor and preparation method thereof - Google Patents
Gallium oxide field effect transistor and preparation method thereof Download PDFInfo
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- CN117373924A CN117373924A CN202311204809.1A CN202311204809A CN117373924A CN 117373924 A CN117373924 A CN 117373924A CN 202311204809 A CN202311204809 A CN 202311204809A CN 117373924 A CN117373924 A CN 117373924A
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- 229910001195 gallium oxide Inorganic materials 0.000 title claims abstract description 117
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 title claims abstract description 116
- 238000002360 preparation method Methods 0.000 title claims abstract description 21
- 238000002353 field-effect transistor method Methods 0.000 title description 2
- 238000005468 ion implantation Methods 0.000 claims abstract description 95
- 238000002513 implantation Methods 0.000 claims abstract description 62
- 230000005669 field effect Effects 0.000 claims abstract description 37
- 150000002500 ions Chemical class 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 18
- 230000008569 process Effects 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 229910052734 helium Inorganic materials 0.000 claims description 3
- 239000001307 helium Substances 0.000 claims description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 239000011777 magnesium Substances 0.000 claims description 3
- 229910052749 magnesium Inorganic materials 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 230000007423 decrease Effects 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 27
- 239000000969 carrier Substances 0.000 abstract description 22
- 239000010410 layer Substances 0.000 description 83
- 238000010586 diagram Methods 0.000 description 8
- 229910005191 Ga 2 O 3 Inorganic materials 0.000 description 6
- 239000000370 acceptor Substances 0.000 description 5
- 230000005684 electric field Effects 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 238000009826 distribution Methods 0.000 description 4
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 3
- 241001354791 Baliga Species 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 229910002601 GaN Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- -1 gallium oxide metal oxide Chemical class 0.000 description 2
- 210000001624 hip Anatomy 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 241000826860 Trapezium Species 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000002508 contact lithography Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000779 depleting effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical group [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- JUWSSMXCCAMYGX-UHFFFAOYSA-N gold platinum Chemical compound [Pt].[Au] JUWSSMXCCAMYGX-UHFFFAOYSA-N 0.000 description 1
- ZNKMCMOJCDFGFT-UHFFFAOYSA-N gold titanium Chemical compound [Ti].[Au] ZNKMCMOJCDFGFT-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 1
- 239000000395 magnesium oxide Substances 0.000 description 1
- AXZKOIWUVFPNLO-UHFFFAOYSA-N magnesium;oxygen(2-) Chemical compound [O-2].[Mg+2] AXZKOIWUVFPNLO-UHFFFAOYSA-N 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- DDBREPKUVSBGFI-UHFFFAOYSA-N phenobarbital Chemical compound C=1C=CC=CC=1C1(CC)C(=O)NC(=O)NC1=O DDBREPKUVSBGFI-UHFFFAOYSA-N 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 229910001258 titanium gold Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The embodiment of the invention provides a gallium oxide field effect transistor and a preparation method thereof, relating to the technical field of gallium oxide device preparation. Since the maximum value of the field strength between the electrodes of the transistor is determined by the number of carriers at each electrode. According to the invention, ion implantation is carried out on two sides of the fin-type channel, so that the lattice structure of the gallium oxide channel layer in the implantation region is damaged, the generation quantity of carriers is reduced, and the carrier concentration at each electrode is reduced, so that the quantity of carriers at each electrode is reduced, the maximum field intensity which can be born between the electrodes of each transistor is increased, and the breakdown voltage of the gallium oxide field effect transistor is further improved. Furthermore, after the ions are injected into the n-type gallium oxide channel layer, the injected ions can be used as carriers in an acceptor depletion channel in the gallium oxide, so that the concentration of the carriers is reduced, and the breakdown voltage of the gallium oxide field effect transistor is further improved.
Description
Technical Field
The invention relates to the technical field of gallium oxide device preparation, in particular to a gallium oxide field effect transistor and a preparation method thereof.
Background
The power electronic device is mainly used for power change and circuit control of power equipment, and is a core device for performing power (power) processing. The current problem of environmental resources in the global scope faces serious examination, and each country sequentially issues energy saving and emission reduction policies, so that the energy saving and emission reduction policies are used as core devices for controlling and converting electric energy of equipment such as industrial facilities, household appliances and the like, and the power semiconductor industry faces new technical challenges and development opportunities.
Silicon-based semiconductor devices are the most commonly used power devices in current power systems, and their performance is quite perfect and approaches the theoretical limit determined by their material properties, so that the increase of power density is in a saturation trend.
Ultra-wide band gap power electronic devices represented by gallium oxide have become an important development field of power semiconductor devices in recent years, and are expected to replace conventional silicon-based power devices in certain specific fields.
The ultra-wide band gap gallium oxide is used as a new semiconductor material, and has outstanding advantages in the aspects of breakdown field strength, baliga (Baliga) figure of merit, cost and the like. The barrega (Baliga) figure of merit is commonly used internationally to characterize the extent to which a material is suitable for a power device. For example, beta Ga 2 O 3 The material barbita figure of merit is 4 times that of gallium nitride material, 10 times that of silicon carbide material, and 3444 times that of silicon material. Beta Ga 2 O 3 Under the condition that the power device is the same as gallium nitride and silicon carbide devices in withstand voltage, the on-resistance is lower, the power consumption is smaller, and the electric energy loss during the operation of the device can be greatly reduced.
Since 2013 japanese information communication research institute (NICT) developed a first gallium oxide metal oxide semiconductor field effect transistor (Ga 2 O 3 MOSFET) device, scientific researchersBy increasing Ga 2 O 3 Crystal material quality, optimizing device manufacturing process, including optimizing channel layer doping, ohmic contact and schottky contact process, gate field plate structure and other methods, to continuously promote Ga 2 O 3 MOSFET device performance. In 2016, NICT was made of Al 2 O 3 As a gate dielectric and combined with a gate field plate structure, the prepared Ga 2 O 3 The breakdown voltage of the MOSFET device reaches 750V. In 2019, the ETRI adopts a source field plate structure, and meanwhile, air breakdown of the device is isolated through fluorinated liquid in the testing process, and the breakdown voltage of the device reaches 2320V. In 2020, buffalo passivated with SU8, and the device breakdown reached 8000V.
However, the breakdown voltage and turn-on characteristics of gallium oxide Field Effect Transistor (FET) devices that have been reported to date are still far below the expected values for the materials.
Disclosure of Invention
The embodiment of the invention provides a gallium oxide field effect transistor and a preparation method thereof, which are used for solving the problem of low breakdown voltage of the existing gallium oxide field effect transistor.
In a first aspect, an embodiment of the present invention provides a method for preparing a gallium oxide field effect transistor, including: an n-type gallium oxide channel layer is grown on the substrate. And a drain electrode and a source electrode are prepared on the n-type gallium oxide channel layer. And preparing a first implantation mask between the drain electrode and the source electrode on the upper surface of the n-type gallium oxide channel layer, wherein the first implantation mask comprises a fin type mask region, and two sides of the fin type mask region are hollowed out to form an unshielded region. And under the shielding of the first implantation mask, carrying out ion implantation on the n-type gallium oxide channel layer of the non-shielding region to obtain a fin-type channel region and an ion implantation region. And preparing a gate dielectric layer on the upper surfaces of the fin channel region and the ion implantation region. And preparing a gate electrode on the gate dielectric layer, wherein the vertical projection of the gate electrode on the n-type gallium oxide channel layer is vertical to the fin-type channel region.
In one possible implementation, the first implantation mask further includes a source side channel mask region. And the source side channel mask region covers the n-type gallium oxide channel layer and is biased to one side of the source electrode. The fin type mask region is arranged between the drain electrode and the source side channel mask region. And the channel layer area shielded by the source side channel mask area is a source side channel area. Correspondingly, the preparation of the gate electrode on the gate dielectric layer comprises the following steps: and preparing a gate electrode in a projection area of the connection part of the fin-type channel region and the source-side channel region to the gate dielectric layer.
In one possible implementation, the fin mask region is a plurality of fin mask regions. One end of each fin mask region is connected with the drain electrode, and the other end is connected with the source electrode. Correspondingly, under the shielding of the first implantation mask, performing ion implantation on the n-type gallium oxide channel layer of the unmasked region to obtain a fin channel region and an ion implantation region, wherein the steps of: and under the shielding of the first implantation mask, performing ion implantation on the two sides of each fin type mask region and the non-shielding region between two adjacent fin type mask regions, wherein a plurality of fin type channel regions are obtained corresponding to the shielding region of each fin type mask region, and a plurality of ion implantation regions are obtained corresponding to the non-shielding region of each fin type mask region.
In one possible implementation, the fin mask region has a trapezoid cross section pointing in the direction of the source electrode, wherein the cross section is parallel to the upper surface of the substrate.
In one possible implementation, the ion implantation region is divided into a plurality of stripe-shaped regions from the source electrode side to the drain electrode side. Correspondingly, under the shielding of the first implantation mask, performing ion implantation on the n-type gallium oxide channel layer of the unmasked region to obtain a fin-type channel region and an ion implantation region, and then further comprising: a second implantation mask is prepared in a first stripe-shaped region from the source electrode side to the drain electrode side of the ion implantation region. And under the shielding of the second implantation mask, carrying out ion implantation on the unmasked area of the ion implantation area. And repeatedly preparing a second implantation mask, shielding the plurality of strip-shaped areas one by one, and carrying out ion implantation on the non-shielded areas of the second implantation mask in the ion implantation area until the plurality of strip-shaped areas of the ion implantation area are shielded by the second implantation mask.
In one possible implementation, the ion material used for the ion implantation is any one of the following: boron, magnesium, nitrogen, helium and hydrogen.
In one possible implementation, the n-type doping concentration of the n-type gallium oxide channel layer gradually decreases from the lower layer toward the upper layer.
In one possible implementation manner, under the shielding of the first implantation mask, ion implantation is performed on the n-type gallium oxide channel layer of the unmasked area, so that after the fin-type channel area and the ion implantation area are obtained, the method further includes: and removing the first implantation mask after ion implantation based on a photoresist removing process to obtain a fin-type channel region and an ion implantation region after mask removal.
In one possible implementation manner, the material of the gate dielectric layer is one or more of the following: al (Al) 2 O 3 、HfO 2 And SiO 2 。
In a second aspect, an embodiment of the present invention provides a gallium oxide field effect transistor, which is prepared based on a preparation method of the gallium oxide field effect transistor as described in any one of the possible implementation manners.
The embodiment of the invention provides a gallium oxide field effect transistor and a preparation method thereof, relating to the technical field of gallium oxide device preparation. Since the maximum value of the field strength between the electrodes of the transistor is determined by the number of carriers at each electrode. According to the invention, ion implantation is carried out on two sides of the fin-type channel, so that the lattice structure of the gallium oxide channel layer in the implantation region is damaged, the generation quantity of carriers is reduced, and the carrier concentration at each electrode is reduced, so that the quantity of carriers at each electrode is reduced, the maximum field intensity which can be born between the electrodes of each transistor is increased, and the breakdown voltage of the gallium oxide field effect transistor is further improved. Furthermore, after the ions are injected into the n-type gallium oxide channel layer, the injected ions can be used as carriers in an acceptor depletion channel in the gallium oxide, so that the concentration of the carriers is reduced, and the breakdown voltage of the gallium oxide field effect transistor is further improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a preparation method of a gallium oxide field effect transistor according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a device structure after a channel layer is grown according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a device structure after a source/drain electrode is grown according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a device structure after a first implantation mask is prepared according to an embodiment of the present invention;
fig. 5 is a schematic view of a device structure after ion implantation according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a device structure after a gate dielectric layer is prepared according to an embodiment of the present invention;
fig. 7 is a schematic view of a device structure after a gate electrode is prepared according to an embodiment of the present invention.
Detailed Description
In order to make the present solution better understood by those skilled in the art, the technical solution in the present solution embodiment will be clearly described below with reference to the accompanying drawings in the present solution embodiment, and it is obvious that the described embodiment is an embodiment of a part of the present solution, but not all embodiments. All other embodiments, based on the embodiments in this solution, which a person of ordinary skill in the art would obtain without inventive faculty, shall fall within the scope of protection of this solution.
The term "comprising" in the description of the present solution and the claims and in the above-mentioned figures, as well as any other variants, means "including but not limited to", intended to cover a non-exclusive inclusion, and not limited to only the examples listed herein. Furthermore, the terms "first" and "second," etc. are used for distinguishing between different objects and not for describing a particular sequential order.
The implementation of the invention is described in detail below with reference to the specific drawings:
in the prior art, in order to increase the breakdown voltage of a gallium oxide field effect transistor, P-type dielectric layers are filled at two sides of a fin-type channel. For example, etching the gallium oxide channel layer under the shielding of a mask to prepare a fin-shaped channel; and growing and filling P-type oxide medium on two sides of the fin type channel. The P-type oxide medium is used for exhausting carriers in the channel, so that the peak field intensity of the gallium oxide field effect transistor is reduced, the threshold voltage is increased, and the breakdown voltage is improved. The breakdown voltage of the existing gallium oxide field effect transistor is still low.
The embodiment of the invention provides a gallium oxide field effect transistor and a preparation method thereof, wherein the lattice structure of a channel layer is destroyed by carrying out an ion implantation mode on two sides of a fin-type channel, so that the generation of carriers is reduced, the breakdown voltage is improved, and the problem of low breakdown voltage of the conventional gallium oxide field effect transistor is solved.
Fig. 1 is a flowchart of a preparation method of a gallium oxide field effect transistor according to an embodiment of the present invention.
Referring to fig. 1, the preparation method includes:
an n-type gallium oxide channel layer is grown on the substrate in step 101. And a drain electrode and a source electrode are prepared on the n-type gallium oxide channel layer.
Fig. 2 is a schematic diagram of a device structure after a channel layer is grown according to an embodiment of the present invention. Referring to fig. 2: the substrate is arranged below, and the n-type gallium oxide channel layer is arranged above. The embodiment of the invention can grow an n-type gallium oxide channel layer on the substrate below based on an epitaxial process.
In some embodiments, the substrate may be a high resistance gallium oxide substrate, a semi-insulating silicon carbide substrate, a magnesium oxide substrate, or a sapphire substrate.
In some embodiments, the n-type gallium oxide channel layer may be a single-layer or multi-layer structure formed by mixing gallium oxide and other doping elements.
Illustratively, the doping element may be silicon or tin. The concentration of doping elements in each of the n-type gallium oxide channel layers is different. Wherein the concentration of the doping element is 1.0X10 15 cm -3 Up to 1.0X10 20 cm -3 。
For example, the concentration of the doping element may be gradually reduced from the lower layer to the upper layer in the n-type gallium oxide channel layer. For example, the doping concentration of the n-type gallium oxide channel layer is graded in a direction away from the substrate.
Illustratively, the thickness of each of the n-type gallium oxide channel layers may be the same or different. Wherein the thickness of the n-type gallium oxide channel layer ranges from 10 nanometers to 1000 nanometers.
In some embodiments, prior to growing the n-type gallium oxide channel layer on the substrate, further comprising: an undoped gallium oxide layer is grown on the substrate.
Illustratively, an undoped gallium oxide layer is disposed between the substrate and the n-type gallium oxide channel layer. Correspondingly, an undoped gallium oxide layer is grown on the substrate, and then an n-type gallium oxide channel layer is grown on the undoped gallium oxide layer.
Illustratively, the n-type gallium oxide channel layer has a thickness in the range of 10 nanometers to 1000 nanometers.
Fig. 3 is a schematic diagram of a device structure after a source-drain electrode is grown according to an embodiment of the present invention. Referring to fig. 3: the embodiment of the invention can prepare the drain electrode and the source electrode on the upper surfaces of the two opposite sides of the n-type gallium oxide channel layer.
In some embodiments, the materials of the drain and source electrodes include titanium gold or titanium aluminum nickel gold.
As a possible implementation manner, the embodiment of the invention can prepare n on the n-type gallium oxide channel layer in the region where the drain electrode and the source electrode are to be grown + A region channel layer; thereafter, a drain electrode and a source electrode are prepared by an electrode deposition process.
Illustratively, the electrodeposition process includes an electron beam evaporation process. Correspondingly, the drain electrode and the source electrode can be prepared through an electron beam evaporation process.
In step 102, a first implantation mask is prepared on the upper surface of the n-type gallium oxide channel layer and between the drain electrode and the source electrode, wherein the first implantation mask includes a fin mask region, and two sides of the fin mask region are hollowed out to form an unmasked region.
Fig. 4 is a schematic diagram of a device structure after preparing a first implantation mask according to an embodiment of the present invention. Referring to fig. 4: according to the embodiment of the invention, the first implantation mask can be prepared on the upper surface of the n-type gallium oxide channel layer. The first implantation mask is used for shielding the n-type gallium oxide channel layer for the next ion implantation.
In some embodiments, the first implantation mask may include a plurality of regions, one of which may be a fin mask region.
The first implantation mask may further include a drain side channel mask region and a source side channel mask region, for example.
For example, the drain side channel mask region covers the n-type gallium oxide channel layer to the drain electrode side. The source side channel mask region covers the n-type gallium oxide channel layer and is biased to the source electrode side. The fin-type mask region is connected with the drain-side channel mask region and the source-side channel mask region.
Illustratively, two sides of the fin mask region are hollowed out to form an unmasked region.
The fin mask region may be a stripe-shaped region disposed between the drain electrode and the source side channel mask region.
In some embodiments, the material of the first implantation mask may be photoresist. Correspondingly, preparing a photoresist mask based on a photoetching development process to obtain a first implantation mask.
In some embodiments, the material of the first implantation mask may also be metal. Correspondingly, preparing a metal mask based on a photoetching stripping process to obtain a first implantation mask.
As one possible implementation, the embodiment of the present invention prepares the first implantation mask through a contact lithography process or an electron beam lithography process.
As one possible implementation, step 102 of an embodiment of the present invention further includes preparing a mask that covers the surfaces of the source and drain electrodes.
In step 103, under the shielding of the first implantation mask, ion implantation is performed on the n-type gallium oxide channel layer of the unmasked region, so as to obtain a fin-type channel region and an ion implantation region.
Fig. 5 is a schematic view of a device structure after ion implantation according to an embodiment of the present invention. Referring to fig. 5: ion implantation is performed under the shielding of the first implantation mask, and the residual first implantation mask is removed after the ion implantation to obtain the structure shown in fig. 5.
In some embodiments, under the shielding of the fin mask region of the first implantation mask, after ion implantation, the shielded region of the fin mask region corresponds to the fin channel region.
Illustratively, the n-type gallium oxide channel layer region masked by the mask is not ion implanted.
In some embodiments, ion implantation is performed on the n-type gallium oxide channel layer corresponding to the unmasked region of the first implantation mask to obtain an ion implantation region.
According to the embodiment of the invention, the fin-type channel region and the ion implantation region are obtained by performing ion implantation under the shielding of the mask. The implanted ions act as acceptors in the gallium oxide, depleting the carriers in the channel, disrupting the lattice of the gallium oxide in the implanted region to reduce the carrier concentration.
In some embodiments, after step 103, further comprising: a high temperature annealing process is performed after ion implantation to activate the implanted ions. Wherein the injected ions can be used as acceptor depletion carriers after activation.
In some embodiments, the ion material used for ion implantation is any of the following: boron, magnesium, nitrogen, helium and hydrogen.
In step 104, a gate dielectric layer is formed over the fin channel region and the ion implantation region. And preparing a gate electrode on the gate dielectric layer, wherein the vertical projection of the gate electrode on the n-type gallium oxide channel layer is vertical to the fin-type channel region.
Fig. 6 is a schematic diagram of a device structure after a gate dielectric layer is prepared according to an embodiment of the present invention. Referring to fig. 6: the gate dielectric layer covers the upper surface of the n-type gallium oxide channel layer.
In some embodiments, the gate dielectric layer is made of one or more of the following materials: al (Al) 2 O 3 、HfO 2 And SiO 2 。
Exemplary gate dielectric layer materials may be Al 2 O 3 、HfO 2 And SiO 2 Either of them may be Al 2 O 3 And HfO 2 Is a composite dielectric material of (a).
In some embodiments, a gate dielectric layer is formed on the upper surfaces of the fin channel region and the ion implantation region by atomic layer deposition.
Fig. 7 is a schematic view of a device structure after a gate electrode is prepared according to an embodiment of the present invention. Referring to fig. 7: the gate electrode is disposed on the gate dielectric layer.
In some embodiments, the gate electrode is in the shape of a bar.
Illustratively, the vertical projection direction of the gate electrode on the n-type gallium oxide channel layer is perpendicular to the fin-type channel region with the direction along the bar-shaped length direction as the gate electrode.
In some embodiments, the material of the gate electrode is nickel gold or platinum gold.
In some embodiments, the gate electrode has a length in the range of 50 nanometers to 10 micrometers.
The embodiment of the invention provides a gallium oxide field effect transistor and a preparation method thereof. Since the maximum value of the field strength between the electrodes of the transistor is determined by the number of carriers at each electrode. According to the invention, ion implantation is performed on two sides of the fin-type channel, so that the lattice structure of the gallium oxide channel layer in the implantation region is damaged, the generation quantity of carriers is reduced, and the carrier concentration at each electrode is reduced, thereby reducing the carrier quantity at each electrode. Therefore, when voltages are applied to the two ends of the electrodes, the number of carriers for generating field intensity under the same voltage condition can be reduced, the field intensity generated under the same voltage condition is reduced, the maximum field intensity which can be born between the electrodes of each transistor is increased, and the breakdown voltage of the gallium oxide field effect transistor is further improved.
Furthermore, after the ions are injected into the n-type gallium oxide channel layer, the injected ions can be used as carriers in an acceptor depletion channel in the gallium oxide, so that the concentration of the carriers is reduced, and the breakdown voltage of the gallium oxide field effect transistor is further improved.
In addition, in step 103, a step of ion implantation is performed to obtain the fin channel and the ion implantation region. Compared with the mode of filling the P-type dielectric layers on two sides of the fin-type channel in the prior art, the method has the advantages of simplifying process steps and improving the preparation efficiency of the gallium oxide field effect transistor.
In one possible implementation, the first implantation mask further includes a source side channel mask region. The source side channel mask region covers the n-type gallium oxide channel layer and is biased to the source electrode side. The fin type mask region is arranged between the drain electrode and the source side channel mask region. The channel layer region shielded by the source side channel mask region is the source side channel region. Correspondingly, the preparation of the gate electrode on the gate dielectric layer comprises the following steps: and preparing a gate electrode in a projection area of the connection part of the fin channel region and the source side channel region to the gate dielectric layer.
In some embodiments, the source side channel mask region is rectangular.
In some embodiments, the fin mask region is connected to the drain electrode on one side and to the source side channel mask region on the other side.
Illustratively, the fin mask region is disposed between the drain electrode and the source side channel mask region.
In some embodiments, the source side channel region is obtained in the channel layer region masked by the source side channel mask region after ion implantation under the masking of the source side channel mask region.
In some embodiments, a vertical projection of the gate electrode on the n-type gallium oxide channel layer covers a connection region of the fin channel and the source-side channel region.
Illustratively, a portion of the gate electrode overlies the fin-type channel and another portion overlies the source-side channel.
Breakdown voltage is a critical parameter of MOSFET power electronics, and breakdown of gallium oxide MOSFETs tends to occur under the gate electrode because conventional right angle gate electrodes have a spike electric field under the end point near the drain where breakdown of the device tends to occur.
The embodiment provided by the invention is to arrange a gate electrode in a connection region of a fin-type channel and a source-side channel region. On the one hand, ion implantation is carried out on two sides of the fin-type channel to destroy the lattice structure of the gallium oxide channel layer in the implantation area, reduce the generation quantity of carriers of the Fang Qi-type channel under the endpoint of the gate electrode close to the drain electrode, reduce the concentration of the carriers, and reduce the peak field intensity of the Fang Qi-type channel under the endpoint of the gate electrode close to the drain electrode, so that the electric field distribution of the device is more uniform, and the breakdown voltage is improved. On the other hand, the injected ions are used as carriers in the acceptor depletion channel in gallium oxide, so that the carrier concentration is reduced, and the breakdown voltage is further improved.
In one possible implementation, the fin mask region is a plurality of fin mask regions. One end of each fin mask region is connected with the drain electrode, and the other end is connected with the source electrode. Correspondingly, under the shielding of the first implantation mask, performing ion implantation on the n-type gallium oxide channel layer of the non-shielding region to obtain a fin-type channel region and an ion implantation region, wherein the steps of: and under the shielding of the first implantation mask, performing ion implantation on the two sides of each fin type mask region and the non-shielding region between two adjacent fin type mask regions, wherein a plurality of fin type channel regions are obtained corresponding to the shielding region of each fin type mask region, and a plurality of ion implantation regions are obtained corresponding to the non-shielding region of each fin type mask region.
In some embodiments, the number of fin mask regions is greater than or equal to three.
Illustratively, the number of fin mask regions is three.
According to the embodiment of the invention, the fin type channel regions and the ion implantation regions which are alternately arranged are obtained by arranging the fin type mask regions. The fin-type channel regions and the ion implantation regions which are arranged in a dispersing mode enable electric field distribution of the device to be more uniform, so that peak field intensity of the device is reduced, and breakdown voltage of the device is improved.
In one possible implementation, the fin mask region has a cross-section in the shape of a trapezoid pointing in the direction of the source electrode, wherein the cross-section is parallel to the upper surface of the substrate.
A trapezoid is a quadrilateral with only one set of opposite sides that are parallel. The parallel sides are the bottom sides of the trapezium: the longer bottom edge is the lower bottom of the trapezoid, and the shorter bottom edge is the upper bottom of the trapezoid. The other two sides are trapezoidal waists. The vertical line section sandwiched between the two bottoms is trapezoidal in height. The trapezoid pointing in the direction of the source electrode, i.e. the direction of the bottom to the top of the trapezoid, points in the direction of the source electrode.
In some embodiments, the trapezoidal cross-section fin mask region corresponds to a trapezoidal cross-section fin channel region.
In some embodiments, the length of the bottom of the fin channel region, which is trapezoidal in cross section toward the drain electrode side, ranges from 300 nanometers to 4000 nanometers.
In some embodiments, the fin channel region has a cross-sectional trapezoid shape with a length ranging from 200 nanometers to 2000 nanometers toward the upper bottom of the source electrode side.
In some embodiments, the cross-sectional trapezoid of fin channel region 22 has a bottom and waist angle in the range of 5 degrees to 85 degrees.
The embodiment provided by the invention adopts a trapezoidal fin-type channel structure, so that the gate electrode has higher surface area, the gate control capability is improved, the threshold voltage is increased, the breakdown voltage is improved, the electric field distribution of the device is more uniform, the peak field intensity of the device is reduced, and the breakdown characteristic of the device is improved.
In one possible implementation, the ion implantation region is divided into a plurality of stripe-shaped regions from the source electrode side to the drain electrode side. Correspondingly, under the shielding of the first implantation mask, ion implantation is performed on the n-type gallium oxide channel layer of the unmasked region, so that after the fin-type channel region and the ion implantation region are obtained, the method further comprises the steps of: a second implantation mask is prepared in a first stripe-shaped region of the ion implantation region from the source electrode side to the drain electrode side. And under the shielding of the second implantation mask, performing ion implantation on the unmasked area of the ion implantation area. And repeatedly preparing a second implantation mask, shielding the plurality of strip-shaped areas one by one, and carrying out ion implantation on the unmasked areas of the second implantation mask in the ion implantation area until the plurality of strip-shaped areas of the ion implantation area are shielded by the second implantation mask.
Illustratively, the stripe-shaped regions are arranged sequentially from the source electrode side to the drain electrode side.
In some embodiments, the ion implantation region is divided into three stripe-shaped regions from the source electrode side to the drain electrode side. The first strip-shaped area, the second strip-shaped area and the third strip-shaped area are respectively arranged. Correspondingly, after step 103, the method further comprises: a mask is prepared covering the first stripe-shaped region. And implanting ions into the second strip-shaped region and the third strip-shaped region of the ion implantation region under the shielding of a mask covering the first strip-shaped region. A mask is prepared covering the second stripe-shaped region. And implanting ions into the third strip-shaped region of the ion implantation region under the shielding of the mask covering the first strip-shaped region and the mask covering the second strip-shaped region. And preparing an ion implantation region with gradient ion implantation concentration.
According to the embodiment provided by the invention, the ion implantation region is subjected to ion implantation for multiple times in the divided regions, so that the ion implantation region with the ion implantation concentration changing in a gradient manner from the source electrode side to the drain electrode side is prepared. The ion implantation region with gradient implantation concentration can further reduce the peak field intensity below the endpoint of the device gate electrode close to the drain electrode, so that the electric field distribution of the device is more uniform, and the breakdown voltage is improved.
In one possible implementation manner, under the shielding of the first implantation mask, ion implantation is performed on the n-type gallium oxide channel layer of the unmasked area, so that after the fin-type channel area and the ion implantation area are obtained, the method further includes:
and removing the first implantation mask after the ion implantation based on the photoresist removing process to obtain the fin-type channel region and the ion implantation region after the mask is removed.
The embodiment of the invention provides a gallium oxide field effect transistor, which is prepared based on the preparation method of the gallium oxide field effect transistor provided in any one of the possible implementation modes.
The above embodiments are only for illustrating the technical solution of the present invention, and are not limiting. Although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some of the technical features thereof can be replaced by equivalents. Such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A preparation method of a gallium oxide field effect transistor is characterized by comprising the following steps of
Growing an n-type gallium oxide channel layer on a substrate; preparing a drain electrode and a source electrode on the n-type gallium oxide channel layer;
preparing a first implantation mask between the drain electrode and the source electrode on the upper surface of the n-type gallium oxide channel layer, wherein the first implantation mask comprises a fin type mask region, and two sides of the fin type mask region are hollowed out to form an unshielded region;
under the shielding of the first implantation mask, carrying out ion implantation on the n-type gallium oxide channel layer of the non-shielding region to obtain a fin-type channel region and an ion implantation region;
preparing a gate dielectric layer on the upper surfaces of the fin channel region and the ion implantation region; and preparing a gate electrode on the gate dielectric layer, wherein the vertical projection of the gate electrode on the n-type gallium oxide channel layer is vertical to the fin-type channel region.
2. The method of manufacturing a gallium oxide field effect transistor of claim 1, wherein the first implantation mask further comprises a source side channel mask region; the source side channel mask region covers the n-type gallium oxide channel layer and is biased to one side of the source electrode; the fin-shaped mask region is arranged between the drain electrode and the source-side channel mask region; the channel layer area shielded by the source side channel mask area is a source side channel area;
correspondingly, the preparation of the gate electrode on the gate dielectric layer comprises the following steps:
and preparing a gate electrode in a projection area of the connection part of the fin-type channel region and the source-side channel region to the gate dielectric layer.
3. The method for manufacturing a gallium oxide field effect transistor according to claim 1 or 2, wherein the fin mask region is a plurality of fin mask regions; one end of each fin type mask region is connected with the drain electrode, and the other end is connected with the source electrode;
correspondingly, under the shielding of the first implantation mask, performing ion implantation on the n-type gallium oxide channel layer of the unmasked region to obtain a fin channel region and an ion implantation region, wherein the steps of:
and under the shielding of the first implantation mask, performing ion implantation on the two sides of each fin type mask region and the non-shielding region between two adjacent fin type mask regions, wherein a plurality of fin type channel regions are obtained corresponding to the shielding region of each fin type mask region, and a plurality of ion implantation regions are obtained corresponding to the non-shielding region of each fin type mask region.
4. The method of claim 1, wherein the fin mask region has a cross-section in a trapezoid shape pointing in a direction of the source electrode, wherein the cross-section is parallel to the upper surface of the substrate.
5. The method of manufacturing a gallium oxide field effect transistor according to claim 1, wherein the ion implantation region is divided into a plurality of stripe-shaped regions from a source electrode side to a drain electrode side;
correspondingly, under the shielding of the first implantation mask, performing ion implantation on the n-type gallium oxide channel layer of the unmasked region to obtain a fin-type channel region and an ion implantation region, and then further comprising:
preparing a second implantation mask in a first strip-shaped area from the source electrode side to the drain electrode side of the ion implantation area;
under the shielding of a second implantation mask, carrying out ion implantation on the non-shielding region of the ion implantation region;
and repeatedly preparing a second implantation mask, shielding the plurality of strip-shaped areas one by one, and carrying out ion implantation on the non-shielded areas of the second implantation mask in the ion implantation area until the plurality of strip-shaped areas of the ion implantation area are shielded by the second implantation mask.
6. The method for manufacturing a gallium oxide field effect transistor according to claim 1, wherein the ion material used for the ion implantation is any one of the following: boron, magnesium, nitrogen, helium and hydrogen.
7. The method of manufacturing a gallium oxide field effect transistor according to claim 1, wherein the n-type doping concentration of the n-type gallium oxide channel layer gradually decreases from the lower layer to the upper layer.
8. The method for manufacturing a gallium oxide field effect transistor according to claim 1, wherein the ion implantation is performed on the n-type gallium oxide channel layer of the non-shielded region under the shielding of the first implantation mask, so as to obtain a fin channel region and an ion implantation region, and further comprising:
and removing the first implantation mask after ion implantation based on a photoresist removing process to obtain a fin-type channel region and an ion implantation region after mask removal.
9. The method of manufacturing a gallium oxide field effect transistor according to claim 1, wherein the gate dielectric layer is made of one or more of the following materials: al (Al) 2 O 3 、HfO 2 And SiO 2 。
10. Gallium oxide field effect transistor, characterized in that it is produced on the basis of a method for producing a gallium oxide field effect transistor according to any one of claims 1 to 9.
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