CN117372342A

CN117372342A - Wafer defect detection method, system and storage medium

Info

Publication number: CN117372342A
Application number: CN202311245929.6A
Authority: CN
Inventors: 李成成; 王刚
Original assignee: Guangdong Anda Intelligent Equipment Co Ltd
Current assignee: Guangdong Anda Intelligent Equipment Co Ltd
Priority date: 2023-09-25
Filing date: 2023-09-25
Publication date: 2024-01-09

Abstract

The application discloses a wafer defect detection method, a system and a storage medium, which relate to the technical field of semiconductors and comprise the following steps: setting characteristic parameters; the characteristic parameters comprise a wafer gray value and a background gray value; positioning to the inner area of the wafer in the detection area through a preset coordinate system, a wafer gray value and a background gray value; performing contour screening from an inner region of the wafer to an outer region of the wafer; dividing the background area and the wafer area in the screened detection area according to the wafer gray value and the background gray value to extract the wafer area; performing coarse defect extraction on the wafer area to obtain a defect set; and carrying out defect screening on the defect areas in the defect set to obtain target defect areas. The wafer detection efficiency can be improved, and the cost can be reduced.

Description

Wafer defect detection method, system and storage medium

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a method and system for detecting wafer defects, and a storage medium.

Background

In the related art, with the development of technology, the precision of semiconductor integrated circuits is also increasing, which puts higher demands on the quality of wafers. In order to ensure the quality of the wafer, the wafer needs to be inspected. At present, there are two general ways to detect a wafer: one is to manually operate the detection equipment, but the effect is not ideal, the time is often wasted, and the labor cost is also high; the other is Artificial Intelligence (AI) detection, and in order to improve the accuracy, the detection mode often needs more complex algorithm operation, which is unfavorable for the rapid detection and affects the detection efficiency. Therefore, how to improve the wafer inspection efficiency and reduce the cost is a technical problem to be solved.

Disclosure of Invention

The present application aims to solve at least one of the technical problems existing in the prior art. Therefore, the application provides a wafer defect detection method, a system and a storage medium, which can improve the wafer detection efficiency and reduce the cost.

According to an embodiment of the first aspect of the present application, a wafer defect detection method includes:

setting characteristic parameters; the characteristic parameters comprise a wafer gray value and a background gray value;

positioning the inner region of the wafer in the detection region through a preset coordinate system, the wafer gray value and the background gray value;

performing contour screening from the inner region of the wafer to the outer region of the wafer;

dividing the background area and the wafer area in the screened detection area according to the wafer gray value and the background gray value to extract the wafer area;

performing coarse defect extraction on the wafer area to obtain a defect set;

and carrying out defect screening on the defect areas in the defect set to obtain target defect areas.

The wafer defect detection method according to the embodiment of the application has at least the following beneficial effects: firstly, setting characteristic parameters; the characteristic parameters comprise a wafer gray value and a background gray value; secondly, positioning the inner area of the wafer in the detection area through a preset coordinate system, a wafer gray value and a background gray value; thirdly, carrying out contour screening from the inner area of the wafer to the outer area of the wafer; dividing the background area and the wafer area in the screened detection area according to the wafer gray value and the background gray value to extract the wafer area; fifthly, performing coarse defect extraction on the wafer area to obtain a defect set; and sixthly, carrying out defect screening on the defect areas in the defect set to obtain target defect areas. According to the wafer defect detection method, after the wafer gray value and the background gray value are set and positioned, contour screening is carried out from inside to outside, on one hand, manual operation by a person is not required to be additionally arranged, and the operation cost can be effectively reduced; on the other hand, the calculation amount can be greatly reduced by screening the contours from inside to outside, so that the contours corresponding to the wafer areas can be rapidly extracted, and the detection efficiency of the wafer is effectively improved. Therefore, the wafer defect detection method can improve the wafer detection efficiency and reduce the cost.

According to some embodiments of the present application, the setting the characteristic parameter includes:

acquiring a first pixel corresponding to the type of the wafer, and setting the gray value of the wafer through the first pixel;

and obtaining a second pixel corresponding to the background, and setting the background gray value through the second pixel.

According to some embodiments of the application, the characteristic parameter further comprises a gray value fluctuation range of each defect;

the performing coarse defect extraction on the wafer area to obtain a defect set includes:

extracting a standard gray value of the lossless wafer as a detection gray value;

obtaining a gray value fluctuation range of bubbles, a gray value fluctuation range of scratches and a dirty gray value fluctuation range according to the detected gray values;

performing coarse defect extraction on the wafer area according to the detected gray value, the gray value fluctuation range of bubbles, the gray value fluctuation range of scratches and the gray value fluctuation range of dirt, so as to obtain a bubble area, a scratch area and a dirt area;

determining the bubble area, the scratch area and the dirt area as defect areas to obtain the defect set; wherein the defect set includes a plurality of defect areas.

According to some embodiments of the present application, the performing coarse defect extraction on the wafer area to obtain a defect set further includes:

setting a first angle threshold value and a second angle threshold value which are common to the concave pit and the convex edge;

calculating a first included angle formed by the concave region and a second included angle formed by the convex region in the edge of the wafer region;

extracting the concave region and determining the concave region as the dent when the first included angle is greater than the first angle threshold;

when the second included angle is larger than the first angle threshold, extracting the convex area and determining the convex area as the convex edge;

when the first included angle is smaller than the second angle threshold, extracting the concave area and determining the concave area as the dent;

when the second included angle is smaller than the second angle threshold, extracting the convex area and determining the convex area as the convex edge;

and determining the areas corresponding to the dents and the convex edges as defect areas to acquire the defect set.

According to some embodiments of the present application, the performing defect screening on the defect areas in the defect set to obtain a target defect area includes:

calculating characteristic parameters of the defect areas corresponding to the bubbles, the scratches, the dirt, the dents and the convex edges, and screening the characteristic parameters through preset screening parameters to obtain the bubbles, the scratches, the dirt, the dents and the convex edges after screening;

and determining the bubbles, scratches, dirt, dents and convex edges after screening as target defect areas.

According to some embodiments of the present application, the wafer defect detection method further includes:

storing the characteristic parameters of each target defect area into a database; wherein the characteristic parameters comprise brightness parameters and shape parameters;

and outputting the target defect area in a classified mode according to the defect gray value or the shape parameter.

when the distance between two adjacent defect areas is smaller than a preset distance threshold value, merging the two adjacent defect areas into one defect area; wherein two adjacent defective areas are the same type of defective area.

According to some embodiments of the application, the characteristic parameter further comprises a wafer area threshold;

the wafer defect detection method further comprises the following steps:

and selecting the wafer with a specific size through the wafer area threshold.

According to a second aspect of the present application, a wafer defect detection apparatus includes:

the parameter setting module is used for setting characteristic parameters; the characteristic parameters comprise a wafer gray value and a background gray value;

the positioning module is used for positioning the inner area of the wafer in the detection area through a preset coordinate system, the wafer gray value and the background gray value;

the profile screening module is used for carrying out profile screening from the inner area of the wafer to the outer area of the wafer;

the segmentation module is used for selecting a wafer with a specific size through the wafer area threshold value, and segmenting a background area and a wafer area in the screened detection area according to the wafer gray value and the background gray value so as to extract the wafer area;

the defect detection module is used for performing defect rough extraction on the wafer area to obtain a defect set; and the defect screening device is also used for carrying out defect screening on the defect areas in the defect set so as to obtain target defect areas.

A wafer defect detection system according to an embodiment of a third aspect of the present application, comprising:

at least one memory;

at least one processor;

at least one program;

the program is stored in the memory, and the processor executes at least one of the programs to implement the wafer defect detection method according to the embodiment of the first aspect.

A computer-readable storage medium according to an embodiment of a fourth aspect of the present application stores computer-executable instructions for causing a computer to perform the wafer defect detection method according to the embodiment of the first aspect.

Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.

Drawings

The application is further described with reference to the accompanying drawings and examples, in which:

FIG. 1 is a flowchart illustrating a method for detecting a wafer defect according to an embodiment of the present disclosure;

FIG. 2 is a schematic structural diagram of a detection area according to an embodiment of the present disclosure;

FIG. 3 is a schematic structural diagram of a defective area according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram illustrating connection of a wafer defect detecting device according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a wafer defect detection system according to an embodiment of the present application.

Reference numerals:

background area 100, wafer area 110, protection area 111, parameter setting module 120, positioning module 130, profile screening module 140, segmentation module 150, defect detection module 160, memory 200, processor 300.

Detailed Description

Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.

It should be noted that although functional block diagrams are depicted as block diagrams, and logical sequences are shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the block diagrams in the system. The terms and the like in the description and in the claims, and in the above-described drawings, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.

In the description of the present application, the meaning of a number is one or more, the meaning of a number is two or more, and greater than, less than, exceeding, etc. are understood to exclude the present number, and the meaning of a number above, below, within, etc. are understood to include the present number. The description of the first and second is for the purpose of distinguishing between technical features only and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.

In the description of the present application, unless explicitly defined otherwise, terms such as arrangement, installation, connection, etc. should be construed broadly and the specific meaning of the terms in the present application can be reasonably determined by a person skilled in the art in combination with the specific contents of the technical solution.

In the description of the present application, a description with reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Next, a wafer defect detection method according to an embodiment of the present application is described with reference to fig. 1 to 3.

It can be appreciated that as shown in fig. 1 and 2, there is provided a wafer defect detection method, including:

step S100, setting characteristic parameters; the characteristic parameters comprise a wafer gray value and a background gray value;

step S110, positioning the inner area of the wafer in the detection area through a preset coordinate system, a wafer gray value and a background gray value;

step S120, performing contour screening from the inner area of the wafer to the outer area of the wafer;

step S130, dividing the background area 100 and the wafer area 110 in the screened detection area according to the wafer gray level value and the background gray level value to extract the wafer area 110;

step S140, performing coarse defect extraction on the wafer area 110 to obtain a defect set;

step S150, defect screening is carried out on the defect areas in the defect set to obtain target defect areas.

Firstly, setting characteristic parameters; the characteristic parameters comprise a wafer gray value and a background gray value; secondly, positioning the inner area of the wafer in the detection area through a preset coordinate system, a wafer gray value and a background gray value; thirdly, carrying out contour screening from the inner area of the wafer to the outer area of the wafer; fourth, dividing the background area 100 and the wafer area 110 in the screened detection area according to the wafer gray level value and the background gray level value to extract the wafer area 110; fifth, performing coarse defect extraction on the wafer area 110 to obtain a defect set; and sixthly, carrying out defect screening on the defect areas in the defect set to obtain target defect areas. According to the wafer defect detection method, after the wafer gray value and the background gray value are set and positioned, contour screening is carried out from inside to outside, on one hand, manual operation by a person is not required to be additionally arranged, and the operation cost can be effectively reduced; on the other hand, the calculation amount can be greatly reduced by the contour screening from inside to outside, so that the contour corresponding to the wafer area 110 can be rapidly extracted, and the detection efficiency of the wafer can be effectively improved. Therefore, the wafer defect detection method can improve the wafer detection efficiency and reduce the cost.

It should be noted that, as shown in fig. 2, the wafer has a characteristic that a protection area 111 with a certain width is formed around, and the gray scale characteristic and the detection area characteristic of the protection area 111 are connected, if breakage occurs, the protection area 111 is easily put into detection, and further, the detection process is complicated, so that in order to avoid the occurrence of the situation, the contour screening from inside to outside is used in positioning, thereby obtaining the wafer area 110 actually needing to be detected.

It should be noted that, in the existing scheme, there is a scheme adopting Artificial Intelligence (AI), and the intelligent AI is adopted, so that firstly, data training is required in the early stage, the workload is large, secondly, specific data training is required for different products and environments, the adaptation cost is high, and the risk of missed detection and false detection is easy to occur. Based on the above, the wafer defect detection method only needs to set the wafer gray value and the background gray value to be fluctuation values, namely, the wafer gray value and the background gray value are allowed to fluctuate within a certain range, so that the wafer defect detection method can be rapidly adapted to different types of wafers with different backgrounds, and because the wafer gray value and the background gray value are adaptively adjusted, and the contour screening from inside to outside is not easy to occur the risk of false detection.

It will be appreciated that setting the characteristic parameters includes:

acquiring a first pixel corresponding to the type of the wafer, and setting a wafer gray value through the first pixel;

and acquiring a second pixel corresponding to the background, and setting a background gray value through the second pixel.

It should be noted that selecting a wafer of a specific size through the wafer area threshold includes:

when the area of the wafer area 110 is greater than the wafer area threshold, the wafer corresponding to the wafer area 110 is determined as a wafer of a specific size.

It can be understood that the characteristic parameters also include the gray value fluctuation range of each defect;

performing coarse defect extraction on the wafer area 110 to obtain a defect set, including:

performing defect rough extraction on the wafer area 110 according to the detected gray value, the gray value fluctuation range of bubbles, the gray value fluctuation range of scratches and the dirty gray value fluctuation range to obtain a bubble area, a scratch area and a dirty area;

determining a bubble area, a scratch area and a dirt area as defect areas to obtain a defect set; wherein the defect set comprises a plurality of defect areas.

As shown in fig. 3 a), b), and c), the bubble region, the scratch region, and the dirt region are sequentially formed.

It can be appreciated that performing coarse defect extraction on the wafer area 110 to obtain a defect set further includes:

calculating a first included angle formed by the concave region and a second included angle formed by the convex region in the edge of the wafer region 110;

when the first included angle is larger than a first angle threshold value, extracting the concave area and determining the concave area as an indent;

when the second included angle is larger than the first angle threshold, extracting the convex area and determining the convex area as a convex edge;

when the first included angle is smaller than the second angle threshold value, extracting the concave area and determining the concave area as an indent;

when the second included angle is smaller than a second angle threshold, extracting the convex area and determining the convex area as a convex edge;

and determining the area corresponding to the dent and the convex edge as a defect area to obtain a defect set.

It should be noted that, the values of the first angle threshold and the second angle threshold are generally as follows:

0 degrees < first angle threshold <10 degrees;

170 degrees < second angle threshold <180 degrees.

As shown in d) and e) in fig. 3, a first included angle formed by the concave region and a second included angle formed by the convex region in the edge of the wafer region 110 are calculated, including:

taking the end point of the concave region connected with the wafer region 110 as a vector starting point, intersecting the two vectors along the edge of the concave region, wherein the intersecting point is the point at which the midpoint perpendicular corresponding to the line segment connected with the two end points intersects with the edge, and calculating a first included angle;

the second included angle is calculated in the same way as the first included angle.

It can be appreciated that performing defect screening on defect areas in the defect set to obtain target defect areas includes:

calculating characteristic parameters of defect areas corresponding to the bubbles, scratches, dirt, dents and convex edges, and screening the characteristic parameters through preset screening parameters to obtain the screened bubbles, scratches, dirt, dents and convex edges;

and determining the screened bubbles, scratches, dirt, dents and convex edges as target defect areas.

It is understood that the wafer defect detection method further includes:

when the distance between two adjacent defect areas is smaller than a preset distance threshold value, merging the two adjacent defect areas into one defect area; wherein two adjacent defect areas are defect areas of the same type.

It should be noted that, as shown in the dashed boxes at a), b), c), d), and e) in fig. 3, the same type of distance is smaller than the distance threshold, and the same type of defect regions may be merged.

It is understood that the characteristic parameter further includes a wafer area threshold;

the wafer defect detection method further comprises the following steps:

and selecting the wafer with a specific size through the wafer area threshold.

It should be noted that, in the same inspection process, there may be different types of wafers in the inspection range, and the sizes of the different types may be inconsistent, based on this, when the wafers are screened, the wafers with a specific size may be identified through the wafer area threshold and the wafer gray value, and then positioned one by one, so as to perform defect inspection.

It should be noted that, in the wafer defect detection method, firstly, the wafer gray value and the background gray value are set, and the contours are screened from inside to outside, so that the positioning speed is high; secondly, screening of characteristic parameters is realized through screening parameters, so that the positioning accuracy is high; and thirdly, different scenes and different defects only need to set a certain fluctuation amplitude, so that the parameter setting is less, and the characteristics of the wafer can be utilized to adapt to the scenes of most situations, including wafers with different sizes and different models. Therefore, the wafer defect detection method is high in defect detection accuracy, and the detection accuracy can be improved by setting parameters.

It can be appreciated that as shown in fig. 4, the present application further provides a wafer defect detecting apparatus, including:

a parameter setting module 120, configured to set a characteristic parameter; the characteristic parameters comprise a wafer gray value and a background gray value;

the positioning module 130 is configured to position the inner area of the wafer in the detection area through a preset coordinate system, a wafer gray value and a background gray value;

a profile screening module 140, configured to perform profile screening from an inner region of the wafer to an outer region of the wafer;

the dividing module 150 is configured to select a wafer of a specific size through a wafer area threshold, and divide the background area 100 and the wafer area 110 in the screened detection area according to the wafer gray value and the background gray value to extract the wafer area 110;

a defect detection module 160, configured to perform defect rough extraction on the wafer area 110 to obtain a defect set; and the defect screening device is also used for carrying out defect screening on the defect areas in the defect set so as to obtain target defect areas.

A wafer defect detection system according to an embodiment of the present application is described below with reference to fig. 5.

It will be appreciated that as shown in fig. 5, the wafer defect detection system includes:

at least one memory 200;

at least one processor 300;

at least one program;

the program is stored in the memory 200, and the processor 300 executes at least one program to implement the wafer defect detection method described above. Fig. 5 illustrates a processor 300.

The processor 300 and the memory 200 may be connected by a bus or other means, fig. 5 being an example of a connection via a bus.

The memory 200, as a non-transitory computer readable storage medium, may be used to store non-transitory software programs, non-transitory computer executable programs, and signals, such as program instructions/signals corresponding to the wafer defect detection system in the embodiments of the present application. The processor 300 performs various functional applications and data processing by running non-transitory software programs, instructions, and signals stored in the memory 200, i.e., implements the wafer defect detection method of the above-described method embodiments.

Memory 200 may include a storage program area that may store an operating system, at least one application program required for functions, and a storage data area; the storage data area may store data related to the wafer defect detection method described above, and the like. In addition, memory 200 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, memory 200 may optionally include memory remotely located with respect to processor 300, which may be connected to the wafer defect inspection system through a network. Examples of such networks include, but are not limited to, the internet of things, software defined networks, sensor networks, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The one or more signals are stored in the memory 200, which when executed by the one or more processors 300, perform the wafer defect detection method of any of the method embodiments described above. For example, the method of fig. 1 described above is performed.

A computer-readable storage medium according to an embodiment of the present application is described below with reference to fig. 5.

As shown in fig. 5, the computer-readable storage medium stores computer-executable instructions that are executed by one or more processors 300, for example, by one of the processors 300 in fig. 5, to cause the one or more processors 300 to perform the wafer defect detection method in the method embodiment described above. For example, the method of fig. 1 described above is performed.

The system embodiments described above are merely illustrative, in which elements illustrated as separate elements may or may not be physically separate, and elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

From the description of the embodiments above, those skilled in the art will appreciate that all or some of the steps, systems, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media and communication media. The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable signals, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and may include any information delivery media.

The embodiments of the present application have been described in detail above with reference to the accompanying drawings, but the present application is not limited to the above embodiments, and various changes can be made within the knowledge of one of ordinary skill in the art without departing from the spirit of the present application. Furthermore, embodiments of the present application and features of the embodiments may be combined with each other without conflict.

Claims

1. The wafer defect detection method is characterized by comprising the following steps:

performing coarse defect extraction on the wafer area to obtain a defect set;

2. The method of claim 1, wherein the setting feature parameters comprises:

3. The method according to claim 1, wherein the characteristic parameters further include a gray value fluctuation range of each defect;

4. The method of claim 3, wherein the performing coarse defect extraction on the wafer area to obtain a defect set further comprises:

5. The method of claim 4, wherein the performing defect screening on the defect regions in the defect set to obtain the target defect region comprises:

6. The method of claim 5, further comprising:

7. The method of claim 5, further comprising:

8. The method of claim 1, wherein the characteristic parameters further comprise a wafer area threshold;

the wafer defect detection method further comprises the following steps:

and selecting the wafer with a specific size through the wafer area threshold.

9. A wafer defect inspection system, comprising:

at least one memory;

at least one processor;

at least one program;

the program is stored in the memory, and the processor executes at least one of the programs to implement the wafer defect detection method according to any one of claims 1 to 7.

10. A computer-readable storage medium storing computer-executable instructions for causing a computer to perform the wafer defect detection method according to any one of claims 1 to 7.