CN117370261A - Method for data transmission and multi-core chip - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 58
- 230000005540 biological transmission Effects 0.000 title claims abstract description 33
- 230000006835 compression Effects 0.000 claims abstract description 197
- 238000007906 compression Methods 0.000 claims abstract description 197
- 230000004044 response Effects 0.000 claims abstract description 9
- 238000012545 processing Methods 0.000 description 25
- 230000006837 decompression Effects 0.000 description 17
- 238000010586 diagram Methods 0.000 description 6
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
Abstract
The present disclosure provides a method for data transmission, which is used for a sending core in a multi-core chip, wherein the multi-core chip comprises a plurality of cores connected with a bus, at least one core is the sending core, and the method comprises: determining a compression scheme of target data according to the target data to be written into the bus; compression schemes include non-compression or target compression schemes; uncompressed means that the target data is not compressed; in response to the compression scheme being uncompressed, writing the target data as online data to the bus; and in response to the compression scheme being a target compression scheme, compressing target data by using a target compression algorithm to obtain online data, writing the online data into a bus, and at least transmitting the identification and the compression scheme of the online data to a core receiving the online data, wherein the target compression algorithm is a lossless compression algorithm. The disclosure also provides a method for receiving data transmission of the core and a multi-core chip.
Description
Technical Field
The present disclosure relates to the technical field of multi-core chips, and in particular, to a data transmission method and a multi-core chip.
Background
Data transmission between cores of a multi-Core chip can be performed by connecting Double Data Rate synchronous dynamic random access memories (DDR) through a bus, so that Data transmission between cores consumes a large amount of DDR bandwidth, and thus bus throughput becomes one of important factors limiting chip processing speed.
Disclosure of Invention
The disclosure provides a data transmission method and a multi-core chip, which can reduce the data quantity transmitted in a bus and improve the processing speed and other performances of the multi-core chip.
In a first aspect, an embodiment of the present disclosure provides a method for transmitting data, where the method is used for a transmitting core in a multi-core chip, and the multi-core chip includes a plurality of cores connected to a bus, and at least one of the cores is the transmitting core, and the method includes:
determining a compression scheme of target data according to the target data to be written into a bus; the compression scheme includes an uncompressed or target compression scheme; the uncompressed means that the target data is not compressed;
writing the target data as online data to the bus in response to the compression scheme being uncompressed;
and responding to the compression scheme as a target compression scheme, compressing the target data by using a target compression algorithm to obtain online data, writing the online data into the bus, and at least transmitting the identification and the compression scheme of the online data to a core receiving the online data, wherein the target compression algorithm is a lossless compression algorithm.
In some embodiments, the identifying and compressing scheme for sending the online data at least to the core receiving the online data comprises:
and broadcasting the identification and compression scheme of the online data.
In some embodiments, the determining the compression scheme of the target data according to the target data to be written to the bus includes:
determining redundancy of the target data; the redundancy represents the duty ratio of repeated information in the target data;
if the redundancy of the target data is larger than a preset threshold value, selecting a target compression algorithm of the target compression scheme from a plurality of preset candidate compression algorithms;
and if the redundancy of the target data is smaller than or equal to a preset threshold value, determining that the compression scheme is not compression.
In some embodiments, the target compression algorithm is selected from one of:
dictionary compression algorithm and run-length encoding compression algorithm.
In some embodiments, the compression scheme further comprises:
and obtaining the compression level of the target compression algorithm.
In a second aspect, embodiments of the present disclosure provide a method for data transmission, for a receiving core in a multi-core chip, the multi-core chip including a plurality of cores connected to a bus, wherein at least a portion of the cores are the receiving cores, the method comprising:
receiving on-line data from a bus;
in response to determining that the online data is not compressed, using the online data as target data;
and responding to the received identification and compression scheme of the online data, wherein the compression scheme is a target compression scheme, and decompressing the online data by using a target compression algorithm to obtain target data, and the target compression algorithm is a lossless compression algorithm.
In some embodiments, the target compression algorithm is selected from one of:
dictionary compression algorithm and run-length encoding compression algorithm.
In some embodiments, the compression scheme further comprises: and obtaining the compression level of the target compression algorithm.
In a third aspect, embodiments of the present disclosure provide a multi-core chip, including a plurality of cores connected to a bus, where at least a portion of the cores are transmitting cores and at least a portion of the cores are receiving cores;
the sending core is configured to any one of the methods of data transmission of the embodiments of the present disclosure;
the receiving core is configured as a method of any of the data transmission of the embodiments of the present disclosure.
In some embodiments, the bus connects double rate synchronous dynamic random access memory DDR.
In the embodiment of the disclosure, a sending core in the multi-core chip can detect whether target data to be sent should be compressed or not, and select a proper target compression algorithm to compress the data and then send the data to the bus when required, and a receiving core which needs to receive the data decompresses the data from the bus and then uses the data, so that the online data entering the bus is compressed, the data quantity transmitted in the bus is greatly reduced, the throughput of the bus is saved, and the processing speed and other performances of the multi-core chip are further improved; moreover, the mode of the embodiment of the disclosure is easy to realize without changing the bus architecture of the multi-core chip.
Drawings
In the drawings of the embodiments of the present disclosure:
FIG. 1 is a schematic diagram of a multi-core chip according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a multi-core chip according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of the core structure of another multi-core chip according to an embodiment of the present disclosure;
FIG. 4 is a flow chart of a method for data transmission of a sending core provided by an embodiment of the present disclosure;
fig. 5 is a flow chart of core processing data in a method for data transmission according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram illustrating the division of target data in a data transmission method according to an embodiment of the present disclosure;
fig. 7 is a flowchart of a method for receiving a data transmission of a core provided by an embodiment of the present disclosure;
fig. 8 is a block diagram of a multi-core chip according to an embodiment of the present disclosure.
Detailed Description
In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the method for data transmission and the multi-core chip provided by the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
The present disclosure will be described more fully hereinafter with reference to the accompanying drawings, but the embodiments shown may be embodied in different forms and should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The accompanying drawings, which are included to provide a further understanding of embodiments of the disclosure and are incorporated in and constitute a part of this specification, illustrate the disclosure and together with the detailed embodiment, do not limit the disclosure. The above and other features and advantages will become more readily apparent to those skilled in the art from the description of the detailed embodiments with reference to the accompanying drawings.
The present disclosure may be described with reference to plan and/or cross-sectional views with the aid of idealized schematic diagrams of the present disclosure. Accordingly, the example illustrations may be modified in accordance with manufacturing techniques and/or tolerances.
Embodiments of the disclosure and features of embodiments may be combined with each other without conflict.
The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The term "and/or" as used in this disclosure includes any and all combinations of one or more of the associated listed items. As used in this disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," "including," "includes," "including," "having," "including," "made of … …" and/or "comprising," when used in this disclosure, specify the presence of stated features, integers, steps, operations, elements, and/or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.
Unless defined otherwise, all terms used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The present disclosure is not limited to the embodiments shown in the drawings, but includes modifications of the configuration formed based on the manufacturing process. Thus, the regions illustrated in the figures have schematic properties and the shapes of the regions illustrated in the figures illustrate the particular shapes of the regions of the elements, but are not intended to be limiting.
In some embodiments, the portable consumer electronics applications processor and MODEM (AP & MODEM, application Processor & MODEM), the terminal chip may employ a multi-core chip, also referred to as a many-core chip, i.e., a chip including a plurality of cores with data processing capability, and the buses of the cores may be connected to DDR, so as to mutually transmit data to cooperatively implement data processing.
With the development of 5G technology, the demands of users show a diversified trend, such as watching high-definition sports live broadcast by using a terminal, guiding different-place operations by medical professionals through real-time video connection, etc., and these application scenes all require that the AP & MODEM terminal chip has high capacity and low-delay ultra-fast data processing capability, so the data transmission quantity between cores is also increasing. However, the large amount of data transfer between cores consumes a large amount of DDR bandwidth, and thus bus throughput is one of the important factors limiting chip processing speed.
In a first aspect, an embodiment of the present disclosure provides a method for data transmission, where the method is used for a sending core in a multi-core chip, and the multi-core chip includes a plurality of cores connected to a bus, where at least a portion of the cores are sending cores.
The method of data transmission of the disclosed embodiments is performed by a sending core in a multi-core chip.
Referring to fig. 1, a multi-core chip includes a plurality of cores each having a certain data processing capability; and each core is connected with the bus, so that each core can mutually transmit data through the bus to cooperatively complete data processing.
It should be understood that in the embodiments of the present disclosure, the "sending core" and the "receiving core" are both determined by the operations performed by the cores during each data transmission, that is, if a certain core sends data according to the method of the embodiments of the present disclosure, it is the sending core, and if a certain core receives data according to the method of the embodiments of the present disclosure, it is the receiving core.
Thus, each core in a multi-core chip of an embodiment of the present disclosure may actually have "capability" to both transmit and receive cores according to the methods of embodiments of the present disclosure, so that each core is either a transmit core or a receive core, or is a transmit core at some times and a receive core at some times.
In some embodiments, the bus connects DDR.
As one way of an embodiment of the present disclosure, referring to fig. 2, each core is connected to the DDR through a Bus, such that the core sending data to the Bus is equivalent to writing data to the DDR through the Bus, and the core receiving data from the Bus is equivalent to reading data from the DDR through the Bus; thus, the bus throughput is equivalent to the data read/write capability of DDR, namely DDR bandwidth.
As a way of an embodiment of the present disclosure, the Core in an embodiment of the present disclosure may be an IP Core, i.e., intellectual Property Core, intellectual property Core.
As a way of an embodiment of the present disclosure, referring to fig. 3 and 5, a core may include a processing core that actually performs data processing, and a method of an embodiment of the present disclosure may be performed by a "policy decision+compression/decompression module" that is hooked at an interface between the processing core and a bus, that is, target data sent from the processing core to the bus, and on-line data to be received by the processing core from the bus, all need to go through the above "policy decision+compression/decompression module" to implement the method of an embodiment of the present disclosure.
Further, referring to fig. 3 and 5, the "policy decision+compression/decompression module" may be divided into a "policy decision sub-module" and a "compression/decompression sub-module", the specific roles of which will be described later.
It should be understood that it is also possible to implement the method of the embodiments of the present disclosure by the core itself, if there is no policy decision + compression/decompression module in the core.
It should be understood that the multi-core chip, core, bus forms of embodiments of the present disclosure are not limited to the above examples.
Referring to fig. 4, a method of data transmission of an embodiment of the present disclosure includes:
s101, determining a compression scheme of target data according to the target data to be written into the bus.
Wherein the compression scheme includes an uncompressed or target compression scheme; uncompressed means that the target data is not compressed.
Referring to fig. 5, when there is target data in a certain transmitting core that needs to be written into a bus to be sent to other receiving cores for processing, the processing core sends the generated target data to a policy decision sub-module, and the policy decision sub-module can analyze characteristics of the target data to determine how the target data should be compressed, that is, determine a compression scheme thereof, and send the target data and the compression scheme to a compression/decompression sub-module for the compression/decompression sub-module to execute subsequent operations according to the compression scheme.
The compression scheme represents a manner of processing the target data, specifically, an uncompressed or selected target compression scheme, the uncompressed representing that the target data does not need to be compressed, and the target compression scheme representing that the target data is compressed with a target compression algorithm selected by the target compression scheme according to the target compression scheme.
That is, the policy decision submodule needs to determine whether to compress the target data and what compression algorithm to use to compress it.
S102, in response to the compression scheme being not compressed, the target data is written into the bus as online data.
When the compression scheme indicates that the target data does not need to be compressed, the compression/decompression sub-module allows the target data to pass through, i.e. bypass, and directly write into the bus as online data.
And S103, responding to the compression scheme as a target compression scheme, compressing target data by using a target compression algorithm to obtain online data, writing the online data into a bus, and transmitting at least the identification of the online data and the compression scheme to a core receiving the online data.
The target compression algorithm is a lossless compression algorithm.
And when the compression scheme is a target compression scheme, the compression/decompression sub-module compresses target data by using a target compression algorithm in the target compression scheme, takes the compressed data as online data, and writes the online data into a bus.
In order to ensure that the receiving core can completely restore the target data, the target compression algorithm must be a lossless compression algorithm, i.e. no information is lost after compression.
Meanwhile, in order to "tell" how the receiving core that receives the online data should decompress, the policy decision+compression sub-module needs to send at least the identifier and the compression scheme of the online data to the receiving core, such as the policy decision+compression sub-module sent to the receiving core.
The identification of the online data refers to any information capable of "distinguishing" the online data, and may specifically include feature information, number information, source core information, destination core information, module information, and the like of the online data.
The "core for receiving the online data" refers to a core that is to receive and process the online data finally, i.e., a corresponding receiving core. For each online data, there may be only one receiving core, i.e., the online data is only processed by one other core, or there may be multiple receiving cores, i.e., the online data needs to be processed by multiple other cores; the receiving core may be determined before the sending of the online data, such as selected by the sending core, or may be determined after the sending of the online data, such as automatically extracted by the currently idle core, or may be temporarily calculated by an upper layer routing algorithm.
In summary, regardless of the number of receiving cores and when selected, the cores that ultimately receive and process the incoming data are enabled to acquire an identification and compression scheme for the incoming data; the receiving core can determine the received online data according to the identification and determine the compression mode adopted by the receiving core.
It should be understood that the above steps S102 and S103 are based on two steps executed separately in different cases, and thus the numbering order and description order thereof do not represent the necessary execution order of both.
In the embodiment of the disclosure, a sending core in the multi-core chip can detect whether target data to be sent should be compressed or not, and select a proper target compression algorithm to compress the data and then send the data to the bus when required, and a receiving core which needs to receive the data decompresses the data from the bus and then uses the data, so that the online data entering the bus is compressed, the data quantity transmitted in the bus is greatly reduced, the throughput of the bus is saved, and the processing speed and other performances of the multi-core chip are further improved; moreover, the mode of the embodiment of the disclosure is easy to realize without changing the bus architecture of the multi-core chip.
In some embodiments, in response to the compression scheme being uncompressed, the method further comprises:
s1021, at least the identification and compression scheme of the online data is sent to the core receiving the online data.
When the target data does not need to be compressed, the identification and the representation of the online data can also be sent to the corresponding receiving core through the compression scheme which does not need to be compressed.
It will be appreciated that it is also possible that the corresponding identification and compression scheme is not sent if no data is compressed, i.e. all cores may default to some data with the corresponding identification and compression scheme being uncompressed.
In some embodiments, the identification and compression scheme for transmitting the online data to at least the core receiving the online data includes:
s104, broadcasting the identification and compression scheme of the online data.
As a way of an embodiment of the present disclosure, the sending core may specifically "broadcast" the identification and compression scheme of the online data to all other cores in the multi-core chip.
For example, referring to fig. 5, an information synchronization system connected to each "policy decision sub-module" may also be provided in the multi-core chip for transmitting the above identification and compression schemes.
In many cases, the cores receiving the online data are not predetermined and often are plural, so that when the online data are written into the bus, the identification and compression scheme can be directly sent to all other cores, so as to ensure that any core has obtained the compressed related information when it is to receive the online data.
It should be appreciated that the identification and compression scheme of the on-line data may also be sent to the receiving core by other means. For example, the identification and compression scheme may also be issued directly by the sending core to the corresponding receiving core; alternatively, the identification and compression scheme may be directly attached to the online data, so that the core that receives the online data is equivalent to receiving the identification and compression scheme thereof.
In some embodiments, determining a compression scheme for target data based on target data to be written to a bus includes:
s1011, determining redundancy of the target data.
Wherein the redundancy characterizes the duty cycle of the repeated information in the target data.
S1012, if the redundancy of the target data is larger than a preset threshold, selecting a target compression algorithm of the target compression scheme from a plurality of preset candidate compression algorithms.
S1013, if the redundancy of the target data is smaller than or equal to a preset threshold value, determining that the compression scheme is not compression.
As a way of the embodiment of the present disclosure, the policy decision submodule may determine redundancy of target data to be written into the bus, where the greater the amount of repeated information in the target data, the greater the corresponding redundancy, and the greater the compression ratio that can be achieved after compressing the target data.
Therefore, the target compression algorithm can be selected to compress the target data only when the redundancy, namely the compression ratio, is large, and when the redundancy is small, no obvious effect can be obtained after compression, and certain calculation force and time are consumed for compression and decompression, so that the target data can be determined not to be compressed.
It should be understood that the above steps S1012 and S1013 are based on two steps executed separately in different cases, and thus the numbering order and description order thereof do not represent the necessary execution order of both.
Wherein the target data may be one of all the data to be written to the bus. For example, referring to fig. 6, all data to be written into the bus may be "segmented", and each segment of data may be the same or different in size, specifically 1-2K, and each segment of data is further used as a target data, and the above processes are respectively determined and performed.
In the compression/decompression sub-module, there may be multiple processing engines, which process compression and decompression operations of multiple segments of data, i.e., multiple target data, in "parallel" to improve efficiency.
In some embodiments, the target compression algorithm is selected from one of: dictionary compression algorithm and run-length encoding compression algorithm.
The target compression algorithm in the embodiment of the disclosure must be lossless, should be adaptable to different scenes, should be calculated in parallel, and should have the characteristics of high execution efficiency and high robustness; for the above requirements, specifically, dictionary compression algorithm and run-length encoding compression algorithm can be selected.
It should be appreciated that the compression algorithms that are actually available are not limited to the above examples.
In some embodiments, the compression scheme further comprises: the compression level of the target compression algorithm is obtained.
As a way of an embodiment of the present disclosure, when a target compression algorithm is determined to be employed, the level of compression required thereof may also be determined to further accommodate the needs of different data.
It should be appreciated that the above compression level may also be selected concurrently with the selection of the target compression algorithm based on the characteristics of the target data.
In a second aspect, an embodiment of the present disclosure provides a method for data transmission, for a receiving core in a multi-core chip, where the multi-core chip includes a plurality of cores connected to a bus, and at least a portion of the cores are receiving cores.
The method of data transmission of the disclosed embodiments is performed by a sending core in a multi-core chip.
Referring to fig. 7, a method of data transmission according to an embodiment of the present disclosure includes:
s201, receiving the online data from the bus.
S202, in response to determining that the online data is not compressed, using the online data as target data.
S203, responding to the received identification and compression scheme of the online data, wherein the compression scheme is a target compression scheme, and the online data is decompressed by a target compression algorithm to obtain target data.
The target compression algorithm is a lossless compression algorithm.
Correspondingly, for the receiving core, the policy decision sub-module receives the identification and the compression scheme of the online data from the information synchronization system and sends the identification and the compression scheme to the compression/decompression sub-module, so after the compression/decompression sub-module receives the online data from the sending core from the bus, if the compression of the online data through the target compression algorithm is determined according to the identification and the compression scheme, the compression/decompression sub-module can decompress the online data according to the target compression algorithm to restore the target data, and then the target data is sent to the processing core for actual processing through the policy decision sub-module.
If the compression/decompression sub-module receives the online data, it is determined that the online data is not compressed, the online data can be directly passed through, and the online data is used as target data, so that the target data is actually processed in the policy decision sub-module transmission processing core.
In some embodiments, determining that the online data is not compressed comprises: the identification of the online data and the compression scheme are received, and the compression scheme is not compressed.
As a way of an embodiment of the present disclosure, if the sending core also sends the identifier and the compression scheme to the uncompressed online data, it may be determined that the online data is not compressed when the identifier and the compression scheme of the online data are received and the compression scheme is uncompressed.
It should be appreciated that the online data may also be determined to be uncompressed by other means. For example, if the sending core does not send the identifier and the compression scheme when the online data is not compressed, it may determine that the online data corresponding to the identifier and the compression scheme is not received.
In some embodiments, the target compression algorithm is selected from one of: dictionary compression algorithm and run-length encoding compression algorithm.
In some embodiments, the compression scheme further comprises: the compression level of the target compression algorithm is obtained.
In a third aspect, referring to fig. 8, an embodiment of the present disclosure provides a multi-core chip, including a plurality of cores connected to a bus, where at least a portion of the cores are transmitting cores and at least a portion of the cores are receiving cores; the sending core is configured as a method of any one of the data transmission embodiments of the present disclosure; the receiving core is configured as a method of any of the data transmission of the embodiments of the present disclosure.
The multi-core chip of the disclosed embodiments includes a plurality of cores, each connected to a bus, wherein at least some of the cores are capable of performing the above data transmission method, and thus are transmitting cores or receiving cores.
It should be understood that a core in the embodiments of the present disclosure is a transmitting core or a receiving core determined by the work it performs during each data transmission, that is, if a certain core transmits data according to the method of the embodiments of the present disclosure at a certain time, it is a transmitting core, and if a certain core receives data according to the method of the embodiments of the present disclosure at a certain time, it is a receiving core.
Thus, each core in a multi-core chip of an embodiment of the present disclosure may actually have "capability" to both transmit and receive cores according to the methods of embodiments of the present disclosure, so that each core is either a transmit core or a receive core, or is a transmit core at some times and a receive core at some times.
In some embodiments, the bus connects DDR.
It should be understood that it is also possible if the bus in the multi-core chip is of other forms.
It should be understood that the multi-core chip in the embodiments of the present disclosure may be a mobile AP & MODEM terminal chip, and may also be a chip used in other fields.
It should be understood that cores in the multi-Core chip in the embodiments of the present disclosure may be IP cores, but may also be other forms of cores; the structure for executing the method can be the core itself or a part of the core is hung at the interface of the processing core and the bus to form a strategy decision+compression/decompression module.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof.
In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components.
Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media or non-transitory medium and communication media or transitory medium. The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information, as known to those skilled in the art. Computer storage media includes, but is not limited to, random access memory, read only memory, charged erasable programmable read only memory, flash memory, or other disk storage; read-only optical discs, digital versatile discs, or other optical disc storage; magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage; any other medium that can be used to store the desired information and that can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.
The present disclosure has disclosed example embodiments, and although specific terms are employed, they are used and should be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, it will be apparent to one skilled in the art that features, characteristics, and/or elements described in connection with a particular embodiment may be used alone or in combination with other embodiments unless explicitly stated otherwise. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the disclosure as set forth in the appended claims.
Claims (10)
1. A method of data transmission for a transmit core in a multi-core chip, the multi-core chip comprising a plurality of cores connected to a bus, wherein at least one of the cores is the transmit core, the method comprising:
determining a compression scheme of target data according to the target data to be written into a bus; the compression scheme includes an uncompressed or target compression scheme; the uncompressed means that the target data is not compressed;
writing the target data as online data to the bus in response to the compression scheme being uncompressed;
and responding to the compression scheme as a target compression scheme, compressing the target data by using a target compression algorithm to obtain online data, writing the online data into the bus, and at least transmitting the identification and the compression scheme of the online data to a core receiving the online data, wherein the target compression algorithm is a lossless compression algorithm.
2. The method of claim 1, wherein the transmitting the identification and compression scheme of the online data at least to a core receiving the online data comprises:
and broadcasting the identification and compression scheme of the online data.
3. The method of claim 1, wherein the determining the compression scheme of the target data from the target data to be written to the bus comprises:
determining redundancy of the target data; the redundancy represents the duty ratio of repeated information in the target data;
if the redundancy of the target data is larger than a preset threshold value, selecting a target compression algorithm of the target compression scheme from a plurality of preset candidate compression algorithms;
and if the redundancy of the target data is smaller than or equal to a preset threshold value, determining that the compression scheme is not compression.
4. The method of claim 1, wherein the target compression algorithm is selected from one of:
dictionary compression algorithm and run-length encoding compression algorithm.
5. The method of claim 1, wherein the compression scheme further comprises:
and obtaining the compression level of the target compression algorithm.
6. A method of data transmission for a receiving core in a multi-core chip, the multi-core chip comprising a plurality of cores connected to a bus, wherein at least a portion of the cores are the receiving cores, the method comprising:
receiving on-line data from a bus;
in response to determining that the online data is not compressed, using the online data as target data;
and responding to the received identification and compression scheme of the online data, wherein the compression scheme is a target compression scheme, and decompressing the online data by using a target compression algorithm to obtain target data, and the target compression algorithm is a lossless compression algorithm.
7. The method of claim 6, wherein the target compression algorithm is selected from one of:
dictionary compression algorithm and run-length encoding compression algorithm.
8. The method of claim 6, wherein the compression scheme further comprises:
and obtaining the compression level of the target compression algorithm.
9. A multi-core chip comprising a plurality of cores connected to a bus, wherein at least one of the cores is a transmitting core and at least one of the cores is a receiving core;
the sending core being configured to perform the method of data transmission of any one of claims 1 to 5;
the receiving core is configured to perform the method of data transmission of any of claims 6 to 8.
10. The multi-core chip of claim 9, wherein,
the bus is connected with the DDR.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210764103.XA CN117370261A (en) | 2022-06-30 | 2022-06-30 | Method for data transmission and multi-core chip |
| PCT/CN2023/102776 WO2024002077A1 (en) | 2022-06-30 | 2023-06-27 | Data transmission method and multi-core chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210764103.XA CN117370261A (en) | 2022-06-30 | 2022-06-30 | Method for data transmission and multi-core chip |
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| CN109074669A (en) * | 2018-07-06 | 2018-12-21 | 深圳市汇顶科技股份有限公司 | data compression method and device |
| CN112559434B (en) * | 2019-09-25 | 2023-12-08 | 阿里巴巴集团控股有限公司 | Multi-core processor and inter-core data forwarding method |
| US11132326B1 (en) * | 2020-03-11 | 2021-09-28 | Nvidia Corporation | Techniques to transfer data among hardware devices |
| CN114077568A (en) * | 2020-08-18 | 2022-02-22 | Oppo广东移动通信有限公司 | Inter-core communication method and device, electronic assembly and electronic equipment |
| US20220179720A1 (en) * | 2020-12-09 | 2022-06-09 | The Boeing Company | Message Synchronization System |
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