CN117370107A

CN117370107A - BIOS log collection method and computing device

Info

Publication number: CN117370107A
Application number: CN202311232136.0A
Authority: CN
Inventors: 方英杰
Original assignee: XFusion Digital Technologies Co Ltd
Current assignee: XFusion Digital Technologies Co Ltd
Priority date: 2023-09-21
Filing date: 2023-09-21
Publication date: 2024-01-09

Abstract

The embodiment of the application discloses a BIOS log collection method and computing equipment, wherein the method comprises the following steps: after the initialization of the eSPI is completed in the BIOS starting process, mapping a first storage space of the out-of-band controller to a memory address space of a processor through an MMBI protocol; and then, the BIOS log is written into the first storage space through the memory address space. According to the embodiment of the invention, the MMBI protocol is applied in the BIOS starting process, and the first storage space of the out-of-band controller is used as the shared space of the out-of-band controller and the processor, so that the processor can rapidly output the detailed BIOS log to the first storage space through the ePI interface, the starting time of the system is not influenced, and when the BIOS is started to have a problem, maintenance personnel can more accurately position the BIOS problem through the detailed BIOS log.

Description

BIOS log collection method and computing device

Technical Field

The application relates to the technical field of computers, in particular to a BIOS log collection method and computing equipment.

Background

During the booting process of a computing device, a basic input/output system (BIOS) performs scan detection, device initialization, resource allocation and adaptation on hardware devices in the computing device. If a boot failure, a system downtime or other failure phenomena occur in the boot process, the BIOS log recorded in the BIOS startup process is often required to analyze and locate the BIOS problem.

The output of the BIOS log through the serial port is a common method in the industry, and because the serial port is a low-speed data transmission interface, the BIOS needs to consume a great deal of time when outputting log data through the serial port, thereby prolonging the system starting time and affecting the use experience of users on products. Therefore, in the general method, the BIOS log is not output or a small number of abbreviated BIOS logs are output at the time of BIOS startup, in consideration of system security and startup speed.

However, when the BIOS start-up is problematic, it is difficult to accurately locate the BIOS problem without or with only a brief BIOS log.

Disclosure of Invention

The embodiment of the application provides a BIOS log collecting method and computing equipment, which can quickly output detailed BIOS logs, reduce the influence of a BIOS starting process on the system starting time, and enable maintenance personnel to more accurately position BIOS problems through the detailed BIOS logs when the BIOS starting is problematic.

A first aspect of an embodiment of the present application provides a BIOS log collection method, applied to a processor of a computing device, the method including:

after the initialization of the enhanced serial peripheral interface (enhanced serial peripheral interface, eSPI) is completed in the BIOS startup process, mapping the first storage space of the out-of-band controller into the memory address space of the processor through a memory-mapped baseboard management controller interface (memory-mapped BMC interface, MMBI) protocol, wherein the MMBI protocol is a data transmission protocol based on the eSPI interface; and writing the BIOS log into the first storage space through the memory address space.

The transmission rate of the serial port is about 11KB/s, the transmission rate theory of the eISPI interface can reach 23MB/s, and the data transmission rate of the eISPI interface is far faster than that of the serial port.

In the embodiment of the application, since the MMBI protocol is a data transmission protocol based on the eSPI interface, after the initialization of the eSPI interface is completed in the BIOS startup process, the processor may map the first storage space of the out-of-band controller to the memory address space of the processor through the MMBI protocol; the processor may then write a BIOS log to the first memory space via the memory address space. According to the embodiment of the invention, the MMBI protocol is applied in the BIOS starting process, and the first storage space of the out-of-band controller is used as the shared space of the out-of-band controller and the processor, so that the processor can rapidly output the detailed BIOS log to the first storage space through the ePI interface, the starting time of the system is not influenced, and when the BIOS is started to have a problem, maintenance personnel can more accurately position the BIOS problem through the detailed BIOS log.

In one possible implementation, after the mapping the first storage space of the out-of-band controller into the memory address space of the processor, the method further comprises: and initializing a serial port.

In this embodiment of the present application, after the processor completes initialization of the eSPI interface and maps the first storage space to the memory address space of the processor, the processor may output the corresponding BIOS log to the first storage space when initializing the serial port. Thus, the embodiment of the application can at least collect the serial port initialization and the BIOS log after the serial port initialization is completed.

In one possible implementation, after the mapping the first storage space of the out-of-band controller into the memory address space of the processor, the method further comprises: and initializing the memory.

In this embodiment of the present application, after the processor completes initialization of the eSPI interface and maps the first storage space to the memory address space of the processor, the processor may output the corresponding BIOS log to the first storage space before initializing the memory; thus, compared to the scheme of outputting the BIOS log to the memory, the embodiments of the present application may at least collect the BIOS log initialized by the memory.

In one possible implementation, the first storage space includes a first buffer region and a second buffer region; the BIOS log comprises a plurality of log records; the writing the BIOS log into the first storage space includes: when the available space of the first buffer area is enough to buffer the log record to be written, writing the log record to be written into the first buffer area; when the available space of the first buffer area is insufficient to buffer the log record to be written, writing the log record to be written into the second buffer area; and sending a first instruction to the out-of-band controller so that the out-of-band controller can migrate the log record in the first buffer area to a second storage space of the out-of-band controller according to the first instruction.

In this embodiment of the present application, by dividing the first storage space into a first buffer area and a second buffer area, the processor may output the log record to one of the buffer areas, replace the buffer area when the buffer area is full, write the log record, and instruct the out-of-band controller to migrate the log record in the full buffer area; under such an asynchronous transmission scheme, the out-of-band controller does not need real-time synchronous data, and only needs to perform data migration when receiving the instruction, so that the processing resources of the out-of-band controller are saved, and the working stability of the out-of-band controller is ensured.

In one possible implementation, the first storage space further includes a header space including a write identification; before the writing of the BIOS log to the first storage space, the method further comprises: when the writing identification indicates that the writing object of the BIOS log is the first cache area, judging whether the available space of the first cache area is enough to cache the log record to be written; when the available space of the first buffer area is insufficient to buffer the log record to be written, modifying the writing identification, wherein the modified writing identification indicates that the writing object is the second buffer area; the writing the log record to be written into the second buffer area includes: and writing the log record to be written into the second buffer area according to the modified writing identification.

In the embodiment of the application, the head space and the writing identifier are arranged in the first storage space, so that the writing identifier controls the processor to output the output object of the log record, and the output object is switched after the current output object is fully written, so that the interval between two times of log record migration of the out-of-band controller is more balanced, and the working stability is higher.

In one possible implementation, the first storage space is a storage space of a volatile memory, and the second storage space is a storage space of a non-volatile memory.

In the embodiment of the application, the storage space of the nonvolatile memory of the out-of-band controller is used as the second storage space, so that the out-of-band controller can store the BIOS log in the nonvolatile memory, and the BIOS log loss caused by accidents such as faults of the out-of-band controller can be avoided.

In one possible implementation, after the writing of the BIOS log to the first storage space, the method further comprises: and sending a second instruction to the out-of-band controller, so that the out-of-band controller migrates the log record in the first storage space to a second storage space of the out-of-band controller according to the second instruction, and releases the first storage space.

In this embodiment of the present application, after the output of the BIOS log is completed, the processor may instruct the out-of-band controller to migrate all log records to the second storage space, and release the first storage space; therefore, the memory resource of the out-of-band controller can be recovered while the BIOS log is prevented from being lost due to unexpected situations.

In one possible implementation, before the writing of the BIOS log to the first storage space, the method further comprises: the first storage space is formatted, and the formatted first storage space comprises a head space, a first cache region and a second cache region.

In the embodiment of the application, the first storage space is formatted to include the head space, the first buffer area and the second buffer area, so that the processor can write the BIOS log to the out-of-band controller in an asynchronous transmission mode.

In one possible implementation, the first memory space is 64KB in size.

In the embodiment of the application, the first storage space is set to be the maximum value of the memory space of the single out-of-band controller which supports mapping by the MMBI protocol at present, so that the data volume of log records which can be cached in the first storage space can be increased as much as possible, the number of times of data migration of the out-of-band controller is reduced, and the working stability of the out-of-band controller is improved.

In one possible implementation, the first storage space includes a first subspace and a second subspace, each of the first subspace and the second subspace being 64KB in size; the first subspace comprises a first cache region and a head space, and the second subspace comprises a second cache region.

In the embodiment of the application, the sizes of the first buffer area and the second buffer area are set to be the maximum value 64KB of the memory space of the single out-of-band controller which is mapped by the MMBI protocol at present, so that the number of times of data migration operation of the out-of-band controller can be reduced, the occupation of computing resources of the out-of-band controller is reduced, and the working stability of the out-of-band controller is improved.

A second aspect of an embodiment of the present application provides a computing device comprising a processor, an enhanced serial peripheral interface, eSPI, and an out-of-band controller, the processor and the out-of-band controller being connected by the eSPI interface; the processor is used for mapping the first storage space of the out-of-band controller into the memory address space of the processor through a memory mapping baseboard management controller interface MMBI protocol after the initialization of the eSPI is completed in the process of executing the BIOS starting program, wherein the MMBI protocol is a data transmission protocol based on the eSPI; the processor is further configured to write a BIOS log into the first storage space through the memory address space.

In one possible implementation, the first storage space includes a first buffer region and a second buffer region; the BIOS log comprises a plurality of log records; when the available space of the first buffer area is enough to buffer the log record to be written, the processor is specifically configured to write the log record to be written into the first buffer area; when the available space of the first buffer area is insufficient to buffer the log record to be written, the processor is specifically configured to write the log record to be written into the second buffer area; and sending a first instruction to the out-of-band controller, so that the out-of-band controller migrates the log record in the first buffer to a second storage space of the out-of-band controller according to the first instruction.

In one possible implementation, before the writing of the BIOS log to the first memory space and after the initializing of the eSPI interface is completed, the method further comprises: and initializing a serial port.

In one possible implementation, before the writing of the BIOS log to the first memory space and after the initializing of the eSPI interface is completed, the method further comprises: and initializing the memory.

In one possible implementation, the first memory space is 64KB in size.

In a third aspect of the embodiments of the present application, there is also provided a computer-readable storage medium having stored therein computer-executable instructions which, when executed by at least one processor of a computing device, perform the method of the first aspect described above.

There is also provided in a fourth aspect of embodiments of the present application a computer program product comprising computer-executable instructions stored in a computer-readable storage medium; the at least one processor of the computing device may read the computer-executable instructions from the computer-readable storage medium, the at least one processor executing the computer-executable instructions causing the computing device to perform the method of the first aspect described above.

It should be appreciated that the benefits of the various aspects described above may be referenced to one another.

Drawings

FIG. 1 is a schematic diagram of a computing device according to an embodiment of the present application;

FIG. 2 is a data flow diagram of a computing device collecting BIOS logs according to an embodiment of the present application;

fig. 3 is a flowchart of a method for collecting BIOS logs according to an embodiment of the present application;

fig. 4 is a flowchart illustrating another BIOS log collection method according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will now be described with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some, but not all embodiments of the present application. As a person of ordinary skill in the art can know, with the development of technology and the appearance of new scenes, the technical solutions provided in the embodiments of the present application are applicable to similar technical problems.

The terms first, second and the like in the description and in the claims of the present application and in the above-described figures, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments described herein may be implemented in other sequences than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

First, technical terms related to the present application will be described:

an enhanced serial peripheral interface (enhanced serial peripheral interface, eSPI) bus, which is an input/output (IO) bus in a computing device, is erected on a south bridge chip of the computing device, and is used for connecting various IO devices with a processor of the computing device; note that, the eSPI bus is mainly used to connect the low-speed IO device with a processor, such as a mouse, a keyboard, and a voice input/output device.

The ePI bus also comprises an ePI interface, which is a serial peripheral interface and belongs to a physical interface for connecting various IO devices.

The memory-mapped baseboard management controller interface (MMBI) protocol is a data transfer protocol based on the eSPI interface.

The workflow agreed by MMBI protocol is: under the condition that the processor and the out-of-band controller are connected through an eSPI bus, the out-of-band controller reserves a part of memory of the out-of-band controller according to an MMBI protocol; the processor maps a partial address in the memory address space of the processor with the partial memory according to the MMBI protocol. Thus, the processor can read and write the partial memory in a memory access mode, namely, the processor can directly read and write the partial memory of the out-of-band controller.

Basic input/output system (BIOS) logs refer to the work logs that the BIOS generates during startup. The BIOS log is the data material necessary to locate BIOS problems, and includes detection records and initialization records of various hardware devices in the computing device, as well as records of BIOS boot loading Operating Systems (OS) during BIOS startup. When a fault occurs in the BIOS starting process, maintenance personnel can locate the BIOS problem by reading and analyzing the BIOS log corresponding to the starting process.

In the related scheme, a BIOS log is output outwards in real time in the BIOS starting process in a serial port output mode, so that a user, maintainer or corresponding software tool can analyze the BIOS log to position BIOS problems. However, in most application scenarios except for the test scenario, the BIOS will not output log data or output a small amount of log data at startup due to system security and startup speed considerations.

Under the condition of adopting the scheme, if the BIOS fails in the starting process, the BIOS problem is difficult to accurately position due to the lack of log data or a small amount of log data; at this time, the BIOS problem needs to be located by changing the starting parameters of the BIOS, restarting the BIOS to reproduce the fault and collect the related log data, for example, turning on the control switch of the serial printing function or changing the printing grade of the serial printing function, and restarting the BIOS. However, upon restarting the BIOS, the environmental or other contingent factors in the computing device that caused the failure may change or be destroyed, making it difficult to fully reproduce the failure, affecting the accuracy of the BIOS problem location.

Therefore, in most application scenarios, when a fault occurs in the BIOS startup process, a BIOS log that can accurately locate the BIOS problem cannot be obtained. Based on this, how to automatically collect and store BIOS logs is an urgent issue to be resolved.

In some implementations, the BIOS log storage process includes: by setting a function with a tracking or mapping function, when the BIOS is started, BIOS log data generated by the BIOS are written into a memory of the computing device for storage.

In this way, the memory is available only after the initialization is completed, so that the finally obtained BIOS log will lack the BIOS log data before the initialization of the memory is completed.

In order to solve the above-mentioned problems, embodiments of the present application provide a method for collecting BIOS logs, which can obtain more complete BIOS log data during the process of starting the BIOS, so as to more accurately locate the BIOS problem.

The BIOS log collection method provided in the embodiment of the present application may be applied to the computing device 100 shown in fig. 1, where the computing device 100 may be a server, a storage controller, a switch, a router, a base station controller, a computing offload card, a computing accelerator card, a computer, a notebook computer, or the like, and the embodiment of the present application is not limited to the specific form of the computing device shown in fig. 1. As shown in fig. 1, the computing device 100 includes a processor 110, a BIOS chip 120, and an out-of-band controller 130, the out-of-band controller 130 including a volatile memory 1301 and a non-volatile memory 1302.

Wherein the processor 110 is coupled to the out-of-band controller 130 via an enhanced serial peripheral interface (enhanced serial peripheral interface, eSPI) bus. Specifically, computing device 100 also includes an eSPI interface (not shown) disposed on the eSPI bus; the processor 110 is coupled to the out-of-band controller 130 through the eSPI interface.

The processor 110 may be a central processing unit (central processing unit, CPU) of the computing device 100 for executing BIOS programs in the BIOS chip 120 to implement BIOS startup.

Specifically, after the computing device 100 is powered up, a main control chipset (not shown in the figure) of the computing device 100 may send a reset signal to the processor 110; the processor 110 restores an initial state according to the reset signal; after the main control chipset detects that the power supply of the processor 110 is stable, the reset signal is removed, and then the processor 110 executes the BIOS program to start the BIOS.

The host chipset may be a north-south bridge of the computing device 100.

The BIOS chip 120 is a read-only memory (ROM) chip in which a BIOS program is stored.

The out-of-band controller 130 may be a management unit for non-business modules, e.g., the out-of-band controller 130 may remotely maintain and manage the computing device 100 via a dedicated data channel; the out-of-band controller 130 is completely independent of the operating system of the computing device 100, and the out-of-band controller 130 can communicate with the processor 110 via the eSPI interface of the computing device 100.

Specifically, the out-of-band controller 130 may be a combination of one or more of a management unit of the operating state of the computing device 100, a management unit built into the processor 110, a management system in a management chip outside the processor, a baseboard management controller (baseboard management controller, BMC), a system management module (system management module, SMM), a management unit built into a business unit, or a device management system in an operating system. The embodiments of the present application are not limited to the specific form of the out-of-band controller 130, but are merely illustrative.

It should be noted that different computing devices may be referred to as BMCs differently, for example, some companies may be referred to as BMCs, some companies may be referred to as integrated lights-out (iLO), and other companies may be referred to as Integrated Dell Remote Access Controller (iDRAC). Either called BMC or iLO or iracc may be understood as BMC in embodiments of the present invention.

The out-of-band controller 130 may be used to store the BIOS log as a file that is convenient for a user or maintenance personnel to view without the need to employ other tools for data conversion.

The processor 110 is further configured to map, during the BIOS startup process, the first storage space of the out-of-band controller 130 into the memory address space of the processor 110 through a memory-mapped baseboard management controller interface (MMBI) protocol after the eSPI interface is initialized; and writing the BIOS log into the first storage space through the memory address space.

Where processor 110 needs to communicate and data interact with the IO devices connected to computing device 100 via the eSPI bus, it will be appreciated that during the startup of the BIOS, the time to initialize the eSPI interface is prior. Similarly, at an early stage in the BIOS boot process, the processor 110 also needs to initialize the serial port to communicate and interact data with the serial device.

Alternatively, during BIOS boot, the processor 110 may initialize the ePI interface first, and then initialize the serial port after mapping the first memory space of the out-of-band controller 130 to the memory address space of the processor 110.

In this embodiment of the present application, the processor completes initialization of the eSPI interface first, and after preparing to output the BIOS log, performs serial port initialization, and at least may collect the serial port initialized BIOS log and the BIOS log after serial port initialization is completed.

It can be understood that the initialization of the serial port and the initialization of the eSPI interface are both early in the BIOS startup process, and the integrity of the BIOS logs that can be collected by the schemes corresponding to different initialization sequences of the serial port and the eSPI interface is similar.

Alternatively, the processor 110 may initialize the eSPI interface first during BIOS startup, and then initialize the memory of the computing device after mapping the first memory space of the out-of-band controller 130 into the memory address space of the processor 110. Therefore, compared with the scheme of outputting the BIOS log to the memory, the embodiment of the invention can collect the BIOS log initialized by the memory, and the integrity is higher.

Wherein the processor 110 may enable the register (not shown in the figures) of the computing device 100 for address mapping by writing an enable flag in the register; after the processor 110 maps the first memory space to the memory address space of the processor 110 according to the MMBI protocol, the processor 110 may write the address of the first memory space corresponding to the memory address space into the register; the processor 110 may then read from and write to the first memory space based on the address in the register.

In particular, the register may be located in a different component of computing device 100, such as in some possible implementations may be located in a south bridge chip of computing device 100, and in other possible implementations may be located in processor 110.

Specifically, there is an enable bit in the register, which processor 110 may write to enable the register for address mapping by writing a code corresponding to the "enable address mapping" action. For example, the code corresponding to the "enable address mapping" action is "1", and the processor 110 may write a "1" in the enable bit.

The processor 110 is specifically configured to obtain the number of storage units that constitute the first storage space according to MMBI protocol; these memory locations are mapped to a segment of contiguous addresses in the memory address space of the processor 110, and the segment of contiguous addresses is written to the register. Specifically, these storage units have a number or serial number identification in the out-of-band controller 130; the processor 110 may obtain the numbers or serial number identifiers of the storage units, and sequentially allocate the addresses of the segment of continuous addresses to the storage units one by one according to the numbers or serial numbers.

It is appreciated that the implementation of the MMBI protocol is based on the physical interface eSPI interface; after the eSPI interface initialization is complete, the processor 110 may map the first memory space to a memory address space of the processor 110 through an MMBI protocol; the related service using the first storage space starts to acquire the data to be transmitted after the BIOS and the OS are started, and then the data to be transmitted is transmitted to the out-of-band controller 130 through the first storage space, so that the first storage space is not occupied by other service functions of the processor 110 or the out-of-band controller 130 in the BIOS starting process. Thus, after the eSPI interface initialization is completed during the BIOS startup process, the processor 110 may write the BIOS log to the out-of-band controller 130 through the first memory space.

It should be noted that, the transmission rate of the serial port is about 11KB/s, and the transmission rate theory of the eSPI interface can reach 23MB/s, so that the transmission speed is faster by adopting the way that the eSPI interface outputs the BIOS log, the influence of the BIOS log collection process on the system starting time is smaller, and the user experience can be improved.

In addition, the output of the BIOS log is carried out through the eSPI interface, and no additional hardware equipment support is needed when the computing equipment collects the BIOS log, so that the computing equipment does not need to wait for the interface supporting the hardware equipment or the controller to collect the BIOS log after the initialization is finished, and the more complete BIOS log can be collected.

The out-of-band controller 130 is further configured to reserve a portion of the memory space from the memory of the out-of-band controller 130 as a first memory space according to the MMBI protocol, so that the processor 110 maps the first memory space to a memory address space of the processor 110 itself.

Optionally, the first storage space is a storage space of the volatile memory 1301. It is understood that the processor 110 does not perceive that the first storage space provided by the out-of-band controller 130 corresponds to the volatile memory 1301 or the nonvolatile memory 1302, and that the first storage space may also be a storage space of the nonvolatile memory 1302 as technology advances.

It should be noted that, the operation of the out-of-band controller 130 is not dependent on hardware or software in the computing device 100, and the out-of-band controller 130 can perform normal operation after power-up and voltage stabilization; if the out-of-band controller 130 and the processor 110 are powered on at the same time, the processor 110 is in a voltage stable operating state when the voltage is stable and the instructions in the BIOS program are started to be executed. In addition, in the current industrial, intelligent operating scenario, a worker typically issues instructions to the out-of-band controller 130 remotely to control the powering on and off of the computing device 100, so that in this scenario, the out-of-band controller 130 is already in operation prior to the BIOS start-up of the computing device 100. That is, during BIOS startup of computing device 100, out-of-band controller 130 is capable of supporting the memory mapping operations and BIOS log write operations of processor 110 described above.

Referring specifically to fig. 2, fig. 2 is a data flow diagram of a computing device collecting BIOS logs according to an embodiment of the present application. As shown in fig. 2, the out-of-band controller 130 further includes a control unit 1303, and the control unit 1303 may be a processing chip or a control chip of the out-of-band controller 130.

The first storage space is a storage space of the volatile memory 1301, and the second storage space is a storage space of the nonvolatile memory 1302. It will be appreciated that in some other possible implementations, the second memory space may also be the memory space of a volatile memory.

After the mapping of the first storage space and the memory address space of the processor 110 itself is completed, when generating the BIOS log, the processor 110 may write the BIOS log into the first storage space; then, after the buffer area in the first storage space is fully written or the output of the BIOS log is completed, an instruction is sent to the control unit 1303; the control unit 1303 migrates the BIOS log in the first storage space to the second storage space according to the instruction.

Alternatively, after the mapping of the first memory space and the memory address space of the processor 110 itself is completed, the processor 110 may format the first memory space first and then write the BIOS log into the first memory space.

Wherein the processor 110 may write specific data in the first storage space, so that the first storage space is changed to a specific format.

Optionally, the processor 110 may write an area identifier in the first storage space, and divide the first storage space into a header space, a first buffer area and a second buffer area; and writing table data into the head space, and tabulating the head space, wherein part of the head space is used for storing fixed data as a table head, and the other space is used for storing variable data as variable table items.

Optionally, the formatted first storage space includes a header space, a first buffer area, and a second buffer area; the head space is used for storing parameters for controlling log caching, and the first cache area and the second cache area are used for caching the BIOS log.

Illustratively, the format of this head space may be as shown in Table 1 below:

table 1 head space table

Wherein the Signature parameter in the header space is a globally unique identifier (globally unique identifier, GUID) of the first storage space for identifying the first storage space.

Wherein the Version parameter is used to indicate the Version of the format of the current first storage space. It will be appreciated that as technology improves and functionality increases, parameters in the header space of the first storage space may increase or decrease, the region division of the first storage space may change, and the Version of the format of the first storage space may be identified by the Version parameter.

The writing identifier (current bank parameter) is used for indicating that the object written into the BIOS log by the current processor 110 is the first cache area or the second cache area; the offset parameter related to the buffer is used for indicating the offset of the starting address of the buffer in the first storage space, and the length parameter is used for indicating the size of the used space of the buffer, and the two parameters can be combined to determine the writing address of the current BIOS log. It will be appreciated that the number of bytes of the header space occupied by the length parameter may vary depending on the accuracy of the writing.

In this example, the header space further includes a buffer threshold parameter, that is, a buffer threshold parameter, for indicating the processor 110 to change the writing identifier when the space occupation of the buffer is greater than or equal to the buffer threshold parameter.

Wherein the reserved space is used to indicate other spaces in the head space than the space occupied by the existing parameters, which free spaces can be used to implement more functions in the future.

The header space also records the offset of the start addresses of the first buffer (Bank 1 buffer) and the second buffer (Bank 2 buffer) in the first storage space, and the space sizes of the first buffer and the second buffer.

The BIOS log includes a plurality of log records, and the processor 110 is configured to write the log records into the first storage space one by one according to a generation time of the log records.

In one possible implementation, after generating the BIOS log, the processor 110 may first access the header space in the first storage space, and determine, according to the writing identifier therein, whether the writing object of the current BIOS log is the first cache area or the second cache area; judging whether the available space of the writing object is enough to cache the log record to be written; if so, writing the log record to be written into the writing object; if the number of the write objects is insufficient, replacing the write objects, and writing the log records to be written into the replaced write objects.

The writing object of the BIOS log refers to a buffer object of the processor 110 writing the BIOS log.

The following two ways are used to determine whether the available space of the writing object is sufficient:

in a first possible implementation, the head space includes a dump threshold parameter; the processor 110 may obtain the dump threshold parameter, and calculate the used space percentage of the writing object according to the total space size and the used space size indicated by the length parameter of the writing object; when the percentage of used space is greater than or equal to the dump threshold parameter, the processor 110 may determine that the available space of the write object is insufficient to cache the log record to be written; when the percentage of used space is less than the dump threshold parameter, the processor 110 may determine that the available space of the write object is sufficient to cache the log record to be written.

When the percentage of the used space is smaller than or equal to the dump threshold parameter, the remaining minimum available space of the corresponding buffer area is larger than a preset value, and the preset value is the size of a preset log record. It can be appreciated that the average size of the log records is tens to hundreds of bytes, and the preset value can be set according to the upper limit of the existing log record size; after the preset value is determined, the dump threshold parameter may be set according to the preset value.

In a second possible implementation, the processor 110 may directly calculate the remaining available space of the current writing object according to the size of the used space indicated by the length parameter and the total size of the writing object; and comparing the available space with the size of the log record to be written to determine whether the available space of the writing object is enough to cache the log record to be written.

The processor 110 may determine the start address of the writing object in the first storage space according to the offset parameter of the current writing object, determine the writing address according to the space length of the writing object currently occupied indicated by the length parameter of the writing object, and finally perform writing of log records according to the writing address.

Optionally, when the processor 110 determines that the current writing object is insufficient to cache the log record to be written, the writing identifier in the head space of the first storage space may be changed to replace the writing object; and writing the log record to the replaced writing object according to the changed writing identifier.

Alternatively, when the processor 110 determines that the current writing object is insufficient to cache the log record to be written, the processor may directly use the cache area except for the writing object in the first storage space as the replaced writing object to write the log record.

Optionally, the out-of-band controller 130 may monitor occupancy of the first buffer and the second buffer; when it is determined that the first buffer or the second buffer is full, the out-of-band controller 130 may migrate the data in the full buffer to the second storage space.

Alternatively, when the processor 110 determines that the current writing object is insufficient to cache the log record to be written, a first instruction may be sent to the control unit 1303; the control unit 1303 migrates the log record in the writing object to the second storage space according to the first instruction, and combines the above schemes of changing the writing object, so that the first buffer area and the second buffer area can alternately buffer the log record.

It will be appreciated that in some possible implementations, the first memory space may be formatted as a buffer; when the buffer is full, the processor 110 instructs the out-of-band controller 130 to migrate the data in the buffer; after waiting for the out-of-band controller 130 to complete the data migration process, the processor 110 continues writing the BIOS log to the cache. In this implementation, the control unit 1303 in the out-of-band controller 130 is required to respond to the request of the processor 110 in time, so as to quickly complete the data migration process, avoid the accumulation of the BIOS log in the cache of the processor 110, and prevent the occurrence of the loss of the BIOS log caused by insufficient cache of the processor 110. Thus, such an implementation requires more computing resources of the out-of-band controller 130, as well as cache resources of the processor 110.

Compared with the implementation mode that the first storage space is a buffer zone, by setting the first buffer zone and the second buffer zone in the first storage space to perform asynchronous transmission of the BIOS log, the interactive real-time requirement of the processor 110 and the out-of-band controller 130 can be reduced, the computing resources of the out-of-band controller 130 are not occupied at any time, the out-of-band controller 130 can perform processing of other services when the first instruction is not received, and the working stability of the out-of-band controller 130 is improved; meanwhile, the situation that the BIOS logs are accumulated in the cache of the processor 110 and the BIOS logs are lost due to insufficient cache is avoided, and the waste of cache resources of the processor 110 is avoided.

The processor 110 is specifically configured to write a BIOS log into the first storage space according to an address corresponding to the first storage space in the memory address space of the processor.

As described above, the memory locations comprising the first memory space correspond to consecutive addresses in the memory address space of the processor 110. The process of writing the BIOS log to the first storage space by the processor 110 may be: the processor 110 determines the write address and then determines the offset of the write address relative to the start address in the segment of consecutive addresses; the offset and log record to be written are then sent to the out-of-band controller 130 over the eSPI bus; the out-of-band controller 130 determines a corresponding storage unit to be written according to the offset and the number or the serial number identifier of the storage unit constituting the first storage space, and stores the log record in the storage unit to be written.

For example, the start address in the segment of consecutive addresses is 601 (in decimal), the write address is 611, and the offset is 10; the numbers of the memory cells constituting the first memory space are 1 to 20, the out-of-band controller 130 may determine that the memory cell to be written is the memory cell of the number 11 according to the offset.

Alternatively, as shown in table 1, the first memory space has a size of 64KB, and is divided into a header space having a size of 4KB, and a first buffer region and a second buffer region having a size of 30KB, respectively.

In one possible implementation, the first storage space includes a first subspace and a second subspace, each of the first subspace and the second subspace being 64KB in size; the first subspace comprises a head space and a first buffer zone, and the second subspace comprises a second buffer zone.

In another possible implementation, the first storage space includes a third subspace, a fourth subspace, and a fifth subspace; wherein the third subspace comprises a head space, the fourth subspace comprises a first buffer zone, and the fifth subspace comprises a second buffer zone.

Illustratively, the fourth subspace and the fifth subspace are each 64KB in size.

It can be appreciated that the current MMBI protocol supports mapping between not more than 3 memory spaces in the out-of-band controller 130 and memory address spaces of the processor 110, and each memory space has a size not greater than 64KB, and in this embodiment of the present application, the head space, the first buffer region, and the second buffer region may be set within the supporting range according to actual needs.

In this embodiment of the present application, the sizes of the first buffer area and the second buffer area are set to the maximum value of 64KB supported by the MMBI protocol, so that the number of times of performing data migration operations by the out-of-band controller 130 can be reduced, the occupation of computing resources of the out-of-band controller 130 is reduced, and the working stability of the out-of-band controller 130 is improved.

Optionally, after the completion of the BIOS startup, the processor 110 writes the last log record of the BIOS log into the first storage space, a second instruction may be sent to the control unit 1303, to instruct the control unit 1303 to migrate all data in the first storage space into the second storage space.

In this embodiment of the present application, by continuously migrating the log record to the second storage space of the nonvolatile memory 1302 during the BIOS startup process, the computing device 100 can obtain the corresponding BIOS log even in the scene of the system startup failure, which is more convenient for the maintainer to locate the BIOS problem according to the BIOS log.

Optionally, after migrating the data in the first storage space to the second storage space according to the second instruction, the control unit 1303 may obtain the BIOS log file according to all log records collected by stitching.

Alternatively, the control unit 1303 may release the first storage space after migrating the data of the first storage space to the second storage space according to the second instruction.

After the processor 110 completes detection and initialization of the various hardware devices of the computing device 100, the processor 110 is further configured to read an OS boot program or an OS boot code in a hard disk or a magnetic disk, and execute an instruction for booting the OS to start.

After the processor 110 starts executing the instruction for initiating the OS start, at which time the BIOS has started to complete, the out-of-band controller 130 stores a BIOS log file generated during the BIOS start process, and the processor 110 is further configured to obtain the BIOS log file from the out-of-band controller 130.

It should be noted that in a specific implementation, the computing device 100 may be any device including a similar structure as in fig. 1. Embodiments of the present application are not limited to a particular constituent structure of computing device 100. Moreover, the constituent structures shown in FIG. 1 do not constitute limitations of computing device 100, and computing system 100 may include more or fewer components than shown in FIG. 1, or may combine certain components, or a different arrangement of components.

Referring to fig. 3, referring to the computing device shown in fig. 1, fig. 3 is a flowchart illustrating a BIOS log collection method according to an embodiment of the present application, where the method is executed by a processor of the computing device shown in fig. 1, and the method includes steps 301 to 302.

In step 301, after initializing the eSPI interface in the BIOS startup process, the processor maps the first storage space of the out-of-band controller to the memory address space of the processor through the MMBI protocol.

Wherein, MMBI protocol is based on the data transmission protocol of eISPI interface.

Wherein the first memory space is a memory space of a memory in the out-of-band controller. Alternatively, the first storage space may be a discontinuous storage space.

Optionally, the first storage space is a storage space of a volatile memory of the out-of-band controller.

The memory address space of the processor refers to a set of memory units that the processor can seek to through a bus. Specifically, for each type of memory (including the memory of the computing device and the memory of the peripheral connected to the computing device) that is physically independent of each other and that is connected to the processor by a bus, the processor may send read and write instructions to operate the memories by the bus; when the processor controls the memories, the memories can be used as a whole logic memory which consists of a plurality of memory units, and the logic memory is a memory address space of the processor, wherein each memory unit corresponds to one address in the memory address space.

By way of example, the peripheral devices may include peripheral device interconnect express (peripheral component interconnect express, PCIe) devices and IO devices.

The processor is connected with the memory of the computing device through a memory bus, connected with the PCIe device through a PCIe bus and connected with the IO device through an IO bus.

In particular, different memories occupy different address ranges in the memory address space. Thus, the processor may map the first memory space of the out-of-band controller as a memory into a segment of contiguous addresses in the memory address space via MMBI protocol; alternatively, the processor may assign segment sequential addresses to the first memory space.

Specifically, after the out-of-band controller is powered on, the out-of-band controller can reserve the first storage space according to the MMBI protocol, and a program or service running in the out-of-band controller does not occupy the first storage space; after initializing the eSP interface, the processor can acquire a first storage space provided by the out-of-band controller according to the MMBI protocol, and can specifically acquire the number of storage units forming the first storage space; then the processor allocates addresses in its own memory address space for each of the memory cells comprising the first memory space, respectively, to establish a mapping.

Optionally, the out-of-band controller is a BMC.

Step 302, the processor writes the BIOS log into the first storage space through the memory address space.

The processor may write the BIOS log into the first storage space through the eSPI interface according to an address corresponding to the first storage space in the memory address space.

The BIOS program comprises a plurality of program instructions; when the BIOS is started, each time the processor executes a program instruction, a log record is generated, and the log record is written into the first storage space.

It will be appreciated that the first storage space supported by the MMBI protocol may not be able to receive the complete BIOS log, and thus when the first storage space is full or is close to full, the out-of-band controller may migrate the log record in the first storage space to the second storage space to complete the collection of the BIOS log.

Optionally, the second storage space is a storage space of a nonvolatile memory of the out-of-band controller.

In this embodiment of the present application, after the processor completes initialization of the eSPI interface and maps the first storage space to the memory address space of the processor, the processor may output the corresponding BIOS log to the first storage space when initializing the serial port. Thus, the embodiment of the application can at least collect the BIOS log after the serial port initialization is completed.

In this embodiment of the present application, after the processor completes initialization of the eSPI interface and maps the first storage space to the memory address space of the processor, the BIOS log of the initialized memory may be output to the first storage space; thus, compared to the scheme of outputting the BIOS log to the memory, the embodiments of the present application can collect the BIOS log initialized by the memory.

In one possible implementation, the out-of-band controller may monitor the remaining available space of the first storage space during the writing of the log record to the first storage space by the processor; when the available space is smaller than or equal to a preset threshold value, the out-of-band controller can migrate the log record in the first storage device to the second storage space.

In one possible implementation, the processor may obtain the size of the first storage space according to MMBI protocol, or according to consecutive addresses corresponding to the first storage space; the processor may calculate an available space of the first storage space when writing a log record to the first storage space; when the available space is insufficient to buffer the log record to be written, sending a collection instruction to the out-of-band controller; the out-of-band controller may migrate the log records in the first storage space to the second storage space in accordance with the gather instruction.

In the implementation, the out-of-band controller is required to timely respond to the request of the processor, the data migration process is completed rapidly, the phenomenon that the BIOS logs are accumulated in the cache of the processor and the BIOS logs are lost due to insufficient cache of the processor is avoided. Thus, such an implementation requires more computing resources of the out-of-band controller, as well as cache resources of the processor.

In one possible implementation, the first storage space includes a first buffer region and a second buffer region; when the available space of the first buffer area is enough to buffer the log record to be written, the processor writes the log record to be written into the first buffer area; when the available space of the first buffer area is insufficient to buffer the log record to be written, the processor writes the log record to be written into the second buffer area and sends a first instruction to the out-of-band controller, so that the out-of-band controller migrates the log record in the first buffer area to a second storage space of the out-of-band controller according to the first instruction.

Optionally, the first buffer area may be an initial writing object, and when the available space of the first buffer area is insufficient to cache the log record to be written, the processor may use the second buffer area as the writing object, and write the subsequent log record into the second buffer area; when the available space of the second buffer area is insufficient to buffer the log records to be written, the log records in the first buffer area are migrated to the second storage space by the out-of-band controller, and the processor can write the subsequent log records into the first buffer area by taking the first buffer area as a writing object, and send a first instruction to the out-of-band controller to instruct the out-of-band controller to migrate the log records in the second buffer area to the second storage space. Thus, the first buffer area and the second buffer area can be alternately used for log record buffering.

Optionally, the first instruction includes an identification of a cache region in which the available space is insufficient.

Optionally, the first storage space may be divided into a first buffer area and a second buffer area, and the sizes of the first buffer area and the second buffer area may be the same. It can be understood that the speed of processing data by the out-of-band controller is slower, and the first buffer area and the second buffer area with the same size can enable the time interval between two times of data migration of the out-of-band controller to be more average, so that the pressure of processing data by the out-of-band controller can be reduced, and the situation that log record is lost due to untimely processing of the out-of-band controller or the processor cannot write the log record to influence the starting time of the computing device is avoided.

Compared with the implementation mode that the first storage space is used as a buffer zone, in the embodiment of the invention, the asynchronous transmission of the BIOS log is carried out by setting the first buffer zone and the second buffer zone in the first storage space, so that the interactive real-time requirement of the processor and the out-of-band controller can be reduced, the computing resource of the out-of-band controller is not occupied at any time, and the out-of-band controller can process other services when the first instruction is not received, thereby being beneficial to improving the working stability of the out-of-band controller; meanwhile, the situation that the BIOS logs are accumulated in the cache of the processor 110 and the BIOS logs are lost due to insufficient cache is avoided, and the waste of cache resources of the processor 110 is avoided.

After the processor writes the last log record of the BIOS log into the first memory space, a second instruction may be sent to the out-of-band controller. Informing the BIOS that the log is completely output; the out-of-band controller may migrate the log record in the first storage space to the second storage space according to the second instruction and then release the first storage space so that the first storage space may perform other services.

Optionally, after migrating the log records in the first storage space to the second storage space according to the second instruction, the out-of-band controller may splice the log records in the second storage space to obtain a BIOS log file, so as to complete collection of the BIOS log; the processor may obtain the BIOS log file from the out-of-band controller.

Optionally, the processor may obtain all log records from the second storage space, and then splice to obtain the BIOS log file.

It will be appreciated that after the completion of the BIOS startup, the processor may obtain the BIOS log file or log record in the second storage space through a network port or other out-of-band interface.

It will be appreciated that with the development of MMBI protocol and related technology, if the future first memory space is sufficient to cache the entire BIOS log, the processor may directly write the BIOS into the first memory space without the out-of-band controller participating in the process.

In the embodiment of the application, since the MMBI protocol is a data transmission protocol based on the eSPI interface, after the initialization of the eSPI interface is completed in the BIOS startup process, the processor may map the first storage space of the out-of-band controller to the memory address space of the CPU through the MMBI protocol; the processor may then write a BIOS log to the first memory space via the memory address space. According to the embodiment of the invention, the MMBI protocol is applied in the BIOS starting process, and the first storage space of the out-of-band controller is used as the shared space of the out-of-band controller and the processor, so that the processor can rapidly output the detailed BIOS log to the first storage space through the ePI interface, the starting time of the system is not influenced, and when the BIOS is started to have a problem, maintenance personnel can more accurately position the BIOS problem through the detailed BIOS log.

With the foregoing in mind, the method for collecting BIOS logs provided in the embodiments of the present application will be further described in detail below by way of one embodiment.

Referring to fig. 4, fig. 4 is a flowchart of another BIOS log collection method according to an embodiment of the present application, where the method is applied to a processor of a computing device, and the processor of the computing device is taken as a CPU, and an out-of-band controller is taken as a BMC for illustration. The specific flow of the method includes steps 401 to 413.

Step 401, the CPU executes a BIOS startup program.

After the CPU is powered on, a BIOS program in the BIOS chip may be executed to implement BIOS startup.

Step 402, the CPU maps the first storage space of the out-of-band controller to the memory address space of the CPU through MMBI protocol.

After the eSPI interface of the computing device is initialized, the CPU may map the first storage space of the out-of-band controller to the memory address space of the CPU through the MMBI protocol.

Step 402 in this embodiment is similar to the technical content of step 301 in the embodiment shown in fig. 3, and specific reference may be made to the related description, which is not repeated here.

Step 403, the CPU formats the first storage space.

After mapping the first storage space to the memory address space, the CPU may format the first storage space into a preset format, where the formatted first storage space includes a header space, a first buffer area, and a second buffer area.

In some embodiments, the head space includes a writing identifier, where the writing identifier is an identifier of a buffer area, and is used to identify that a writing object of the current CPU writing the BIOS log is a first buffer area or a second buffer area; other parameters in the head space may be as shown in table 1 in the computing device embodiment described above. In practical applications, other parameters than the written identifier in the head space may be more or less parameters based on table 1 according to the requirements of the function setting.

Step 404, the CPU determines the writing object according to the writing identification.

Wherein, after the formatting is completed, the first storage space may be used to cache log records of the BIOS log. At this time, the CPU may write log records that have been generated and have not been lost to the first storage space.

Specifically, the CPU may first cache the generated log records in a CPU cache (CPU cache) before the first memory space formatting is completed, and write the log records to the first memory space after the first memory space formatting is completed.

The CPU can access the writing identification in the head space of the first storage space, and determine that the writing object is the first cache area or the second cache area. The writing mark is the mark of the first buffer area or the mark of the second buffer area; it will be appreciated that the written identification defaults to the identification of the first buffer after formatting is complete.

Further, after determining the writing object, the CPU may further determine a storage unit to be written in the storage units forming the first storage space according to an offset parameter and a length parameter of the writing object in the header space; and determining the writing address according to the storage unit to be written.

Specifically, the CPU may obtain the start address of the writing object in the first storage space according to the offset parameter of the writing object, and then obtain the length of the space currently occupied by the writing object according to the length parameter; then determining the minimum offset of the available space of the writing object in the first storage space according to the starting address and the occupied space length, and determining the storage unit to be written according to the minimum offset; and finally, the CPU determines the writing address according to the serial number or the serial number identification of the storage unit to be written.

For example, the first memory space has a size of 64KB, the first buffer is a writing object, and the first buffer has a size of 30KB; the 1 st to 4 th KB of the first storage space is the head space, and the initial address of the first buffer area is 0x1000, namely 4096 th byte; if the first buffer currently occupies 1KB, the minimum offset of the available space of the first buffer in the first storage space is 5120 bytes.

Then, the first storage space consists of 16 storage units with the number of 1-16 and the number of 4KB, wherein the address offset range in the storage unit with the number of 2 corresponds to the first storage space is 4096 bytes-8192 bytes; the CPU can determine that the storage unit to be written is the storage unit with the number of 2 according to the minimum offset; finally, the CPU may determine the write address by determining, according to the storage unit numbered 2, that the offset of the write address in the consecutive addresses corresponding to the first storage space is 1. The continuous addresses corresponding to the first storage space refer to continuous addresses in the memory address space of the processor mapped by the first storage space.

The writing object is an object for writing the BIOS log by the CPU and points to the first cache area or the second cache area; the write address is the address corresponding to the memory unit to be written in the memory address space of the CPU.

Step 405, the CPU determines whether the available space of the writing object is enough to cache the log record to be written.

The CPU may determine the available space of the writing object according to the length parameter of the writing object, determine the available space in combination with the total space size of the writing object, and finally compare the available space with the size of the log record to be written to determine whether the available space is enough to cache the log record to be written.

If so, execute step 406; if not, step 409 is performed.

Step 406, the CPU writes the log record to be written into the writing object.

The above-mentioned determination of the write address is performed after step 404 and before step 406, and may be performed before step 405 or after step 405, which is not specifically limited herein.

Step 406 in this embodiment is similar to the technical content of step 302 in the embodiment shown in fig. 3, and specific reference may be made to the related description, which is not repeated here.

After completing writing of one log record at a time, the CPU may update the length parameter of the writing object in the head space to update the used space information of the writing object, and then execute step 407.

Step 407, the CPU determines whether the BIOS log is output.

After writing a log record, the CPU may determine whether the output of the BIOS log is completed, and if so, execute step 408; if not, go back to execute step 404.

When the BIOS is started, the CPU reads an OS boot program or an OS boot code in the hard disk or the magnetic disk, and executes an instruction for booting the OS. Alternatively, the CPU may determine whether the BIOS startup is complete based on whether the boot OS startup instruction is currently started or whether the startup OS is started.

Optionally, after completing writing of a log record, if it is determined that the current BIOS is started, the CPU may determine that the BIOS log is output, and then execute step 408.

Optionally, after completing writing of one log record, if it is determined that the current BIOS is started, the CPU may further determine whether the log record to be written exists in the cache of the CPU; if not, it may be determined that the output of the BIOS log is completed, and step 408 is performed; if so, execution returns to step 404.

If it is determined that the current BIOS does not complete the boot, then execution returns to step 404.

In step 408, the CPU sends a second instruction to the BMC.

After the output of the BIOS log is completed, the CPU may send a second instruction to the BMC to inform that the output of the BIOS log is completed, and instruct the BMC to execute step 411.

Step 409, the CPU modifies the write flag.

In the case where it is determined that the available space of the writing object is insufficient, the CPU may change the writing identification in the head space to the identification of another buffer. For example, the original writing identifier is the identifier of the first buffer area, when the available space of the first buffer area is insufficient, the CPU can change the writing identifier into the identifier of the second buffer area, and then perform log writing according to the identifier of the second buffer area.

After modifying the write flag, the CPU may return to execute step 404 and execute step 410. It will be appreciated that the CPU may execute step 404 first or may execute step 410 first, which is not limited in this embodiment of the present application.

Step 410, the CPU sends a first instruction to the BMC.

The first instruction includes an identifier of a buffer area with insufficient available space, and is used for informing the BMC that the available space of the buffer area is insufficient, and the buffer area needs to be emptied by data migration for subsequent log record writing.

Specifically, the CPU may send the first instruction to the BMC through an intelligent platform management interface (intelligent platform management interface, IPMI).

Step 411, the BMC migrates a log record in the first storage space.

After receiving the related instruction of the CPU, the BMC migrates the log record in the first storage space according to the instruction. The instruction comprises a first instruction and a second instruction, wherein the first instruction is an instruction for instructing the BMC to migrate log records in a full cache region when the cache region in a first storage space is full; and when the output of the BIOS log is finished, the second instruction indicates the BMC to migrate the last log record in the first storage space.

If the first instruction is received, the BMC can migrate the log record in the corresponding cache region to the second storage space according to the cache region identifier in the first instruction; if the second instruction is received, the BMC may directly migrate the log record in the first storage space to the second storage space according to the second instruction.

After completing the data migration according to the second instruction, the BMC may execute step 412 according to the second instruction.

Step 412, the BMC releases the first memory space according to the second instruction.

After the log records of the first storage space are migrated to the second storage space, the mission of the first storage space is completed, no log records need to be cached before the computing device is restarted, and at this time, the BMC can release the first storage space according to the second instruction so as to avoid wasting storage resources.

Optionally, the BMC may initialize the first memory space and restore the first memory space to an initial state, so that various functional services of the BMC or the CPU may use the first memory space.

Step 413, the CPU obtains a BIOS log.

The CPU can acquire the spliced BIOS log from the BMC, or can acquire the log record from the BMC and then splice the BIOS log by itself.

In the embodiment of the application, the writing identification is set in the head space of the first storage space to indicate the writing object, the CPU writes the log record into the buffer area in the first storage space according to the writing identification, and rewrites the writing identification when one buffer area is full, and simultaneously instructs the BMC to migrate the log record full in the buffer area, so that the asynchronous transmission effect is achieved. Therefore, compared with a synchronous transmission scheme, the method can reduce the interactive real-time requirement of the CPU and the BMC, does not need to occupy the computing resource of the BMC at any time, can process other services when the migration instruction is not received, and is beneficial to improving the working stability of the BMC; meanwhile, the situation that the BIOS logs are accumulated in the cache of the CPU and the BIOS logs are lost due to insufficient cache is avoided, and the waste of cache resources of the CPU is avoided.

In another embodiment of the present application, there is further provided a computer-readable storage medium having stored therein computer-executable instructions that, when executed by at least one processor of a computing device, perform the BIOS log collection method described in the above-described embodiments of fig. 3-4.

In another embodiment of the present application, there is also provided a computer program product comprising computer-executable instructions stored in a computer-readable storage medium; the at least one processor of the computing device may read the computer-executable instructions from the computer-readable storage medium, the at least one processor executing the computer-executable instructions causing the computing device to perform the BIOS log collection method described in the above-described embodiments of fig. 3-4.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the embodiments of the present application.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.

In the several embodiments provided in the embodiments of the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the embodiments of the present application may be essentially or, what contributes to the prior art, or part of the technical solution may be embodied in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

Claims

1. A method for collecting BIOS logs, the method comprising:

after the initialization of an enhanced serial peripheral interface eSPI is completed in the BIOS starting process, mapping a first storage space of an out-of-band controller into a memory address space of a processor through a memory mapping baseboard management controller interface MMBI protocol, wherein the MMBI protocol is a data transmission protocol based on the eSPI interface;

and writing the BIOS log into the first storage space through the memory address space.

2. The method of claim 1, wherein after said mapping the first memory space of the out-of-band controller into the memory address space of the processor, the method further comprises:

and initializing a serial port.

3. The method according to claim 1 or 2, wherein the first storage space comprises a first buffer and a second buffer; the BIOS log comprises a plurality of log records; the writing the BIOS log into the first storage space includes:

when the available space of the first buffer area is enough to buffer the log record to be written, writing the log record to be written into the first buffer area;

When the available space of the first buffer area is insufficient for buffering the log record to be written, writing the log record to be written into the second buffer area; and sending a first instruction to the out-of-band controller so that the out-of-band controller migrates the log record in the first buffer zone to a second storage space of the out-of-band controller according to the first instruction.

4. The method of claim 3, wherein the first storage space further comprises a head space, the head space comprising a written identification; before the writing of the BIOS log to the first storage space, the method further comprises:

when the writing identification indicates that the writing object of the BIOS log is the first cache area, judging whether the available space of the first cache area is enough to cache the log record to be written;

when the available space of the first cache region is insufficient for caching the log record to be written, modifying the writing identification, wherein the writing identification after modification indicates that the writing object is the second cache region;

the writing the log record to be written into the second buffer area includes:

And writing the log record to be written into the second cache region according to the modified writing identification.

5. A method according to claim 3, wherein the first memory space is a memory space of a volatile memory and the second memory space is a memory space of a non-volatile memory.

6. The method of any of claims 1-5, wherein after the writing of the BIOS log to the first storage space, the method further comprises:

and sending a second instruction to the out-of-band controller, so that the out-of-band controller migrates the log record in the first storage space to a second storage space of the out-of-band controller according to the second instruction, and releases the first storage space.

7. The method of any of claims 1-6, wherein prior to the writing of the BIOS log to the first storage space, the method further comprises:

and formatting the first storage space, wherein the formatted first storage space comprises a head space, a first cache region and a second cache region.

8. The method of any of claims 1-7, wherein the first storage space is 64KB in size.

9. The method of any of claims 1-7, wherein the first storage space comprises a first subspace and a second subspace, the first subspace and the second subspace each being 64KB in size; the first subspace comprises a first cache region and a head space, and the second subspace comprises a second cache region.

10. A computing device, the device comprising a processor, an enhanced serial peripheral interface, eSPI, and an out-of-band controller, the processor and the out-of-band controller being connected by the eSPI interface;

the processor is configured to map, after the initialization of the eSPI interface is completed in the process of executing the BIOS startup procedure, the first storage space of the out-of-band controller into the memory address space of the processor through a memory mapping baseboard management controller interface MMBI protocol, where the MMBI protocol is a data transmission protocol based on the eSPI interface;

the processor is further configured to write a BIOS log into the first storage space through the memory address space.