CN117370092A - Random test program, chip detection method and device - Google Patents
Random test program, chip detection method and device Download PDFInfo
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- CN117370092A CN117370092A CN202311529443.5A CN202311529443A CN117370092A CN 117370092 A CN117370092 A CN 117370092A CN 202311529443 A CN202311529443 A CN 202311529443A CN 117370092 A CN117370092 A CN 117370092A
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- 238000012360 testing method Methods 0.000 claims abstract description 141
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- 230000015654 memory Effects 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 19
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- 238000010998 test method Methods 0.000 claims description 3
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
Abstract
The invention relates to the technical field of computers and discloses a random test program, a chip detection method and a device, wherein the random test program comprises a random context, a head control code, a test instruction sequence and a tail control code, and the random context comprises a plurality of random values; the header control code is used for storing the random value into a register of the target chip; the test instruction sequence comprises a plurality of test instructions, the test instructions are randomly generated according to a target instruction set, a callback function and ARM instruction set codes, and the test instruction sequence is used for operating random values in a register to obtain a test result; the tail control code is used for returning the target address of the target chip after executing the test instruction sequence, and the invention can meet the test requirement of special instructions and improve the effectiveness of functional test of the test program.
Description
Technical Field
The invention relates to the technical field of processors, in particular to a random test program, a chip detection method and a device.
Background
In designing a processor chip, verification of the designed processor chip is required to determine whether the designed processor chip functions normally, whether there is a design defect or a production defect, or the like.
In the prior art, an instruction sequence in a test program is generated through a template definition framework and an instruction set, the configurable constraint types of a predefined template are limited, special test requirements of partial instructions cannot be met, and the effectiveness of random test is reduced.
Disclosure of Invention
In view of the above, the present invention provides a random test program, a chip test method and a device for solving the problem of validity of the test program.
In a first aspect, the present invention provides a random test program comprising a random context, a header control code, a sequence of test instructions, a trailer control code, the random context comprising a plurality of random values; the header control code is used for storing the random context into a register of a target chip; the test instruction sequence comprises a plurality of test instructions, the test instructions are randomly generated according to a target instruction set, a callback function and ARM instruction set codes, and the test instruction sequence is used for operating random values in a register to obtain a test result; and the tail control code is used for returning to the target address of the target chip after executing the test instruction sequence.
The random test program of the invention stores the random context into the register of the target chip, and calculates the random value of the generated test instruction sequence to obtain a test result, and judges the functional correctness of the target chip according to the test result; according to the target instruction set, the callback function and the ARM instruction set, the test instruction which is randomly generated can meet the test requirement of the special instruction, and the effectiveness of the functional test of the test program is improved.
In an alternative embodiment, the test program further includes a file header, including:
when the storage space storing the random test program stores a reference result, the file header contains a result comparison mark, and the reference result is the result of executing the random test program on the reference platform.
The result comparison mark is used for recording whether the storage space storing the random test program stores the reference result or not, and if the result comparison mark is stored, the random test program is called in the target chip to obtain the test result.
In an alternative embodiment, the file header further includes a random seed and an instruction number, including:
the random value in the random context is generated from a random seed; the instruction number is used for specifying the number of test instructions in the test instruction sequence.
The random seed generates the random value, so that the generated random test program has more randomness, the random seed is used for generating the random value in the random context, the random context initializes the register of the target chip when being called, the instruction number is used for designating the number of test instructions in the test instruction sequence, the test instruction sequence is flexibly formulated, and different test requirements can be met.
In an alternative embodiment, the test instructions are obtained by:
randomly generating an instruction according to a target instruction set; judging whether the instruction is in a legal interval according to the coding mode in ARM instruction set coding; if the instruction is in the legal interval, calling an instruction constraint callback function so that the instruction constraint callback function judges whether the instruction meets the constraint or not; and if the instruction meets the constraint condition, adding the instruction as a test instruction into a test instruction sequence.
In the invention, whether the instruction belongs to an illegal instruction interval in the coding mode in ARM instruction set coding is judged, if the instruction is in the legal interval, the instruction is called to restrict the callback function, the random restriction capability of the callback function is strong, and the restriction is carried out by defining a callback function for each instruction, so that the problem of insufficient restriction capability caused by limited configuration templates is avoided, and the efficiency is higher.
In an alternative embodiment, if the instruction is not within the legal interval or the instruction does not meet the constraint condition, judging whether the instruction performs an exception test; if the abnormal test is carried out, adding the instruction as a test instruction into a test instruction sequence; if the exception test is not performed, the instruction is discarded.
If the instruction is not in the legal interval or the instruction does not meet the constraint condition, and when the abnormal test is carried out, the instruction is added into the test instruction sequence as the test instruction, so that the stability and fault tolerance of the random test program are improved, the abnormal test can find out the performance bottleneck caused by system abnormality, dependence server, application abnormality and other reasons, and the abnormal test can ensure the stability of the random test program.
In a second aspect, the present invention provides a chip detection method, the method comprising:
calling the random test program of the first aspect or any implementation mode corresponding to the first aspect in a target chip to obtain a test result; if the storage space storing the random test program is determined to store the reference result according to the random test program; obtaining a reference result; and determining an abnormal detection result of the target chip according to the comparison result of the reference result and the test result.
According to the method, the random test program is called to obtain the test result, and the method for determining the abnormal detection result of the target chip according to the comparison result of the reference result and the test result is more accurate for detecting the abnormal of the target chip.
In an alternative embodiment, if the random test program includes a header and the header includes a result comparison flag, it is determined that the reference result is stored in the storage space in which the random test program is stored.
In the invention, if the file header contains the result comparison mark, the reference result is stored in the storage space storing the random test program, the random test program is not required to be called in the reference platform, and if the file header does not contain the result comparison mark, the reference result is not stored in the storage space storing the random test program.
In a third aspect, the present invention provides a chip testing apparatus, comprising:
the calling module is used for calling the random test program of the first aspect or any implementation mode corresponding to the first aspect in the target chip to obtain a test result;
the first judging module is used for determining that a reference result is stored in a storage space in which the random test program is stored according to the random test program;
the reference result acquisition module is used for acquiring a reference result;
and the result comparison module is used for determining an abnormal detection result of the target chip according to the comparison result of the reference result and the test result.
According to the invention, the abnormal detection result of the target chip is determined by calling the test result of the random test program, and the abnormal detection result has accuracy.
In a fourth aspect, the present invention provides a computer device comprising: the random test program of the first aspect or any implementation manner corresponding to the first aspect or the chip detection method of any implementation manner corresponding to the second aspect is executed by the processor.
In a fifth aspect, the present invention provides a computer readable storage medium, where the random test program of the first aspect or any embodiment corresponding thereto, or computer instructions, where the computer instructions are configured to cause a computer to execute the chip detection method of the second aspect or any embodiment corresponding thereto, are stored.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method of chip detection according to some embodiments of the invention;
FIG. 2 is a block diagram of a chip inspection apparatus according to an embodiment of the present invention;
fig. 3 is a schematic hardware structure of a computer device according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The embodiment of the invention provides a random test program, which achieves the effect of improving the effectiveness of the random test program by testing an instruction sequence.
In accordance with an embodiment of the present invention, a random test program embodiment is provided, it being noted that the steps shown in the flowcharts of the figures may be performed in a computer system, such as a set of computer executable instructions, and, although a logical order is shown in the flowcharts, in some cases, the steps shown or described may be performed in an order other than that shown or described herein.
In this embodiment, a random test program is provided, which can be used in a mobile terminal, and the program includes:
a random context, the random context comprising a plurality of random values.
In some alternative embodiments, the random value in the random context is generated by a random seed.
And the header control code is used for storing the random context into a register of the target chip.
In some alternative embodiments, the random context is stored in a register of the target chip, such that the test instruction sequence computes random values in the random context in the register.
And the test instruction sequence is used for operating the random value in the register to obtain a test result, and comprises a plurality of test instructions which are randomly generated according to the target instruction set, the callback function and the ARM instruction set codes.
In some optional embodiments, a plurality of test instructions in a test instruction sequence are randomly generated according to a target instruction set, a callback function and ARM instruction set codes, wherein the target instruction set comprises a plurality of instructions, different instructions are applicable to different test objects, in the embodiment of the invention, when the test instructions are generated, instructions applicable to a target chip are selected from the target instruction set according to a target chip to be tested, and then the instructions are screened through the callback function and the ARM instruction set codes; the constraint mode of the callback function is to define a method for constraining the callback function through each instruction to conduct instruction constraint; the ARM instruction set codes indicate the coding modes belonging to illegal instruction intervals; the test instruction sequence calculates the random value in the register to obtain a test result, and determines an abnormal detection result of the target chip according to the test result.
And the tail control code is used for returning to the target address of the target chip after the test instruction sequence is executed.
In some alternative embodiments, after the test instruction sequence is executed, the test instruction sequence is returned to the target address of the target chip, so that the target chip can perform field collection and result comparison, or the random test program can be re-called to continue target chip detection.
According to the random test program provided by the embodiment, a head control code stores a random value in a random context into a register of a target chip, a generated test instruction sequence carries out operation on the random value in the register to obtain a test result, and the functional correctness of the target chip is judged according to the test result; the target instruction set indicates a target chip applicable to the random test program generated at present, the ARM instruction set codes indicate coding modes belonging to illegal instruction intervals, the instructions which are not in legal instruction intervals are judged, the constraint mode of the callback function is to conduct instruction constraint by a method of defining a constraint callback function for each instruction, the constraint method of the callback function can conduct instruction constraint for all instructions, and the test requirement of special instructions is met; according to the target instruction set, the callback function and the ARM instruction set, the test instruction which is randomly generated can meet the test requirement of the special instruction, and the effectiveness of the function test of the random test program is improved.
In this embodiment, a random test program is provided, which may be used in the above mobile terminal, where the random test program further includes:
and when the storage space storing the random test program stores a reference result, the file header contains a result comparison mark, and the reference result is the result of executing the random test program on the reference platform.
In some alternative embodiments, the file header further comprises:
a random seed for generating a random value in a random context.
In some alternative embodiments, the random values are generated from a random seed, and the random values are used to operate with the test instruction sequence stored in a register.
The instruction number is used for specifying the number of the test instructions in the test instruction sequence.
In some alternative embodiments, when generating the test instruction sequence, generating the test instruction in a loop until the number of generated test instructions in the generated test instruction sequence is equal to the number of test instructions in the test instruction sequence, so as to obtain the test instruction sequence.
In some alternative embodiments, the test instructions are obtained by:
step a1, randomly generating instructions according to a target instruction set.
In some alternative embodiments, the instructions are randomly generated according to a target instruction set that indicates the test chip for which the random test program is currently being generated.
And a2, judging whether the instruction is in a legal interval according to the coding mode in ARM instruction set coding.
In some alternative embodiments, the ARM instruction set code indicates a coding mode belonging to an illegal instruction section, the coding mode of the instruction is compared with the coding mode of the illegal instruction section in the ARM instruction set code, if the coding mode of the instruction belongs to the coding mode of the illegal instruction section in the ARM instruction set code, the instruction is determined to be in the illegal instruction section, and if the coding mode of the instruction does not belong to the coding mode of the illegal instruction section in the ARM instruction set code, the instruction is determined to be in the legal section.
And a3, if the instruction is in the legal interval, calling an instruction constraint callback function so that the instruction constraint callback function judges whether the instruction meets constraint conditions or not.
In some alternative embodiments, the callback function is constrained by calling the instruction constraint callback function, the callback function has strong random constraint capability, and the problem of insufficient constraint capability caused by limited configuration templates is avoided by defining a callback function for each instruction to conduct constraint.
For example, for one mov instruction, the destination register, source register range, or immediate range may be constrained separately or simultaneously as test requirements code. However, the template constraint needs more complex configuration and even can not realize the constraint, so that the constraint mode in the embodiment of the invention is more flexible.
And a4, adding the instruction as a test instruction into a test instruction sequence if the instruction meets the constraint condition.
In some alternative embodiments, instructions that belong to legal intervals and satisfy constraints are added to the test instruction sequence.
In some alternative embodiments, if the instruction is not within a legal interval or the instruction does not satisfy the constraint, it is determined whether the instruction is performing an exception test.
In an alternative embodiment, the random test program is randomly generated by another generation program, and the generation program can be configured by a command option, and after the flag bit is configured based on the configuration option, the flag bit is referred to determine whether to perform the abnormal test.
If the abnormal test is carried out, the instruction is added into a test instruction sequence as a test instruction.
In some alternative embodiments, if an exception test is performed, the instruction that does not satisfy the constraint and is not in the legal interval is added to the test instruction sequence, so that stability and fault tolerance of the random test program are improved.
If the exception test is not performed, the instruction is discarded.
In some alternative embodiments, if the exception test is not performed, the instructions that do not satisfy the constraint and are not within the legal interval are discarded, and the randomly generated instructions are continued.
The plurality of test instructions in the test instruction sequence in the random test program provided by the embodiment are randomly generated according to the target instruction set, the callback function and the ARM instruction set codes, the constraint mode of the callback function is to carry out instruction constraint by a method that each instruction defines a constraint callback function, the constraint method of the callback function can carry out instruction constraint on all instructions, the test requirement of special instructions is met, and the problem that constraint capacity is insufficient due to the fact that a configuration template is limited when the configuration template is adopted to generate the test instruction sequence is avoided by adopting the mode that the callback function is adopted to generate the test instruction sequence; the method for determining the abnormal detection result of the target chip by comparing the reference result of the reference platform with the test result avoids the problems that a plurality of test results obtained by calling the random test program for many times on the target platform occupy more registers and have lower accuracy, and the problem that the error of the plurality of test results leads to lower accuracy of the abnormal detection result of the target chip. In this embodiment, a chip detection method is provided, which may be used in the mobile terminal described above, and fig. 1 is a flowchart of a chip detection method according to an embodiment of the present invention, as shown in fig. 1, where the flowchart includes the following steps:
step S201, calling a random test program in the specific embodiment mode in the target chip to obtain a test result.
In some alternative embodiments, a random test program is loaded in a designated memory space in a target chip, the target chip parses out a file header of the random test program, fetches a random context, calls a header control code, loads the random context into a register of the target chip, calls a test instruction sequence, operates on a random value in the register to obtain a test result, executes a tail control code, and returns a target address of the target chip.
Step S202, if it is determined that the reference result is stored in the storage space storing the random test program according to the random test program.
In some alternative embodiments, when the reference result is stored in the memory space in which the random test program is stored, it indicates that the random test program has been executed on the reference platform; when the reference result is not stored in the storage space storing the random test program, the random test program is indicated not to be executed in the reference platform.
Step S203, a reference result is obtained.
In some alternative embodiments, the reference result is a result obtained when the random test program is executed in the reference platform, and in the embodiments of the present invention, the default reference platform is not abnormal, so that the reference result obtained by the reference platform may be compared with the test result obtained by the target chip, so as to determine whether the target chip is abnormal.
Step S204, determining the abnormal detection result of the target chip according to the comparison result of the reference result and the test result.
In some alternative embodiments, if the reference result is the same as the test result, determining that the target chip is not abnormal; if the reference result is different from the test result, determining that the target chip is abnormal.
In some alternative embodiments, if the random test program includes a header and the header includes a result comparison flag, it is determined that the reference result is stored in the storage space in which the random test program is stored.
In some alternative embodiments, if the header in the random test program does not include a result comparison flag, the random test program may be called multiple times in the target chip, the test results of the multiple calls may be compared, if the test results of the multiple calls are the same, it is determined that the target chip is not abnormal, and if the test results of the multiple calls are different, it is determined that the target chip is abnormal.
According to the chip detection method provided by the embodiment, whether the target chip is abnormal or not is detected by calling the random test program, the test result is compared with the reference result of the reference platform, and the comparison result is high in accuracy and efficiency.
In this embodiment, a chip detection device is further provided, and the device is used to implement the foregoing embodiments and preferred embodiments, and is not described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.
The present embodiment provides a chip detection apparatus, as shown in fig. 2, including:
a calling module 301, configured to call a random test program in a specific embodiment in a target chip, so as to obtain a test result;
the first determining module 302 is configured to determine, according to the random test program, that the reference result is stored in the storage space in which the random test program is stored.
The reference result obtaining module 303 is configured to obtain a reference result.
The result comparison module 304 is configured to determine an abnormal detection result of the target chip according to a comparison result of the reference result and the test result.
In some alternative embodiments, the method comprises:
and the second judging module judges that the storage space storing the random test program stores the reference result if the random test program comprises a file header and the file header comprises a result comparison mark.
The chip scale test device in this embodiment is in the form of a functional unit, where the unit refers to an ASIC circuit, a processor and a memory executing one or more software or firmware programs, and/or other devices that may provide the above functions.
Further functional descriptions of the above respective modules are the same as those of the above corresponding embodiments, and are not repeated here.
The embodiment of the invention also provides computer equipment, which is provided with the chip detection device shown in the figure 2.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a computer device according to an alternative embodiment of the present invention, and as shown in fig. 3, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components are communicatively coupled to each other using different buses and may be mounted on a common motherboard or in other manners as desired. The processor 10 may process instructions executing within the computer device, including instructions stored in or on the memory 20 to display graphical information of a GUI on an external input/output device, such as a display device coupled to an interface. In some alternative embodiments, multiple processors and/or multiple buses may be used, if desired, along with multiple memories and multiple memories. Also, multiple computer devices may be connected, each providing a portion of the necessary operations (e.g., as a server array, a set of blade servers, or a multiprocessor system). One processor 10 is illustrated in fig. 3.
The processor 10 may be a central processor, a network processor, or a combination thereof. The processor 10 may further include a hardware chip, among others. The hardware chip may be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general-purpose array logic, or any combination thereof.
Wherein the memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform the methods shown in implementing the above embodiments.
The memory 20 may include a storage program area that may store an operating system, at least one application program required for functions, and a storage data area; the storage data area may store data created from the use of the computer device of the presentation of a sort of applet landing page, and the like. In addition, the memory 20 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, memory 20 may optionally include memory located remotely from processor 10, which may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
Memory 20 may include volatile memory, such as random access memory; memory 20 may also include non-volatile memory, such as flash memory, a hard disk, or a solid state disk; the memory 20 may also comprise a combination of the above types of memories.
The computer device further comprises input means 30 and output means 40. The processor 10, memory 20, input device 30, and output device 40 may be connected by a bus or other means, for example in fig. 3.
The input device 30 may receive input numeric or character information and generate key signal inputs related to user settings and function control of the computer apparatus, such as a touch screen, a keypad, a mouse, a trackpad, a touchpad, a pointer stick, one or more mouse buttons, a trackball, a joystick, and the like. The output means 40 may include a display device, auxiliary lighting means (e.g., LEDs), tactile feedback means (e.g., vibration motors), and the like. Such display devices include, but are not limited to, liquid crystal displays, light emitting diodes, displays and plasma displays. In some alternative implementations, the display device may be a touch screen.
The embodiments of the present invention also provide a computer readable storage medium, and the method according to the embodiments of the present invention described above may be implemented in hardware, firmware, or as a computer code which may be recorded on a storage medium, or as original stored in a remote storage medium or a non-transitory machine readable storage medium downloaded through a network and to be stored in a local storage medium, so that the method described herein may be stored on such software process on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, a solid state disk or the like; further, the storage medium may also comprise a combination of memories of the kind described above. It will be appreciated that a computer, processor, microprocessor controller or programmable hardware includes a storage element that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the methods illustrated by the above embodiments.
Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.
Claims (10)
1. A random test program is characterized by comprising a random context, a head control code, a test instruction sequence and a tail control code,
the random context contains a plurality of random values;
the header control code is used for storing the random context into a register of a target chip;
the test instruction sequence comprises a plurality of test instructions, the test instructions are randomly generated according to a target instruction set, a callback function and ARM instruction set codes, and the test instruction sequence is used for operating random values in the register to obtain a test result;
and the tail control code is used for returning to the target address of the target chip after the test instruction sequence is executed.
2. The program according to claim 1, wherein the random test program further includes a header, and the method comprises:
when the storage space storing the random test program stores a reference result, the file header contains a result comparison mark, and the reference result is the result of executing the random test program on a reference platform.
3. The program of claim 2, wherein the header further includes a random seed and a number of instructions, and the method comprises:
the random value in the random context is generated from the random seed;
the instruction number is used for specifying the number of test instructions in the test instruction sequence.
4. The program of claim 1, wherein the test instruction is obtained by:
randomly generating an instruction according to the target instruction set;
judging whether the instruction is in a legal interval or not according to the coding mode in the ARM instruction set coding;
if the instruction is in the legal interval, calling an instruction constraint callback function so that the instruction constraint callback function judges whether the instruction meets constraint conditions or not;
and if the instruction meets the constraint condition, adding the instruction as a test instruction into the test instruction sequence.
5. The program according to claim 4, comprising:
if the instruction is not in the legal interval or the instruction does not meet the constraint condition, judging whether the instruction carries out an abnormal test or not;
if an abnormal test is carried out, the instruction is added into the test instruction sequence as a test instruction;
if no exception test is performed, discarding the instruction.
6. A chip detection method, comprising:
invoking the random test program according to any one of claims 1-5 in a target chip to obtain a test result;
if the random test program is determined to be stored with the reference result in the storage space stored with the random test program;
acquiring the reference result;
and determining an abnormality detection result of the target chip according to the comparison result of the reference result and the test result.
7. The method according to claim 6, comprising:
if the random test program comprises a file header and the file header comprises a result comparison mark, judging that a reference result is stored in a storage space in which the random test program is stored.
8. A chip testing device, the device comprising:
a calling module, configured to call the random test program according to any one of claims 1 to 5 in a target chip, so as to obtain a test result;
the first judging module is used for determining that a reference result is stored in the storage space storing the random test program according to the random test program;
the reference result acquisition module is used for acquiring the reference result;
and the result comparison module is used for determining an abnormal detection result of the target chip according to the comparison result of the reference result and the test result.
9. A computer device, comprising:
a memory and a processor, the memory and the processor being communicatively connected to each other, the memory having stored therein computer instructions, the processor executing the random test program of any one of claims 1-5 or performing the chip test method of claim 6 or 7 by executing the computer instructions.
10. A computer-readable storage medium, wherein the computer-readable storage medium has stored thereon the random test program according to any one of claims 1 to 5, or computer instructions for causing a computer to execute the chip test method according to claim 6 or 7.
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