CN117369878A - Instruction processing method and device of double-emission pipeline, electronic equipment and medium - Google Patents
Instruction processing method and device of double-emission pipeline, electronic equipment and medium Download PDFInfo
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- CN117369878A CN117369878A CN202210772559.0A CN202210772559A CN117369878A CN 117369878 A CN117369878 A CN 117369878A CN 202210772559 A CN202210772559 A CN 202210772559A CN 117369878 A CN117369878 A CN 117369878A
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- 238000003672 processing method Methods 0.000 title claims abstract description 14
- 230000005540 biological transmission Effects 0.000 claims abstract description 15
- 238000012545 processing Methods 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims description 18
- 230000009977 dual effect Effects 0.000 claims description 15
- 238000004590 computer program Methods 0.000 claims description 5
- 238000004364 calculation method Methods 0.000 claims description 2
- 230000007246 mechanism Effects 0.000 claims description 2
- 238000013461 design Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
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- 238000004422 calculation algorithm Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 230000002093 peripheral effect Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The embodiment of the application relates to the field of processors and discloses an instruction processing method, an instruction processing device, electronic equipment and a medium of a double-emission pipeline. In the application, the instruction is transmitted according to a preset sequence by utilizing a double-in double-out queue; when the instructions are transmitted, sequentially distributing marks representing the transmission sequence for each instruction according to a preset sequence; and acquiring the marks of the instructions during the submission, and submitting the instructions in turn according to the sequence of the instructions recorded by the marks. Therefore, the sequential double-emission pipeline scheme of instruction level parallelism is realized, the performance of the processor is improved relative to single emission, and compared with an out-of-order pipeline, the scheme does not need to additionally increase hardware and optimizes the occupied area of the processor.
Description
Technical Field
The embodiment of the application relates to the field of processors, in particular to an instruction processing method, an instruction processing device, electronic equipment and a medium of a double-emission pipeline.
Background
In order to improve the efficiency of the CPU, most of modern processors have widely adopted pipeline designs, and pipeline structures are respectively: fetch (Ifetch), decode (Dec), execute (Exec), memory operation (Mem), and write back register (WB).
The emission design of instructions under the traditional pipeline structure is usually sequential single-shot, and only one instruction can be realized in a single period, so that the requirements of high data volume communication and big data operation under the present condition are difficult to be met. In order to meet the requirement of big data operation, an out-of-order multiple-shot processor is generally adopted, and a single cycle of the processor can emit multiple instructions, so that the performance of the processor is improved, but the mode has the same problems: the out-of-order pipeline needs to additionally add hardware units to solve the problem of pipeline conflict, and the newly added hardware units cause a large size of the processor and occupy a large area.
Disclosure of Invention
The embodiment of the application aims to provide an instruction processing method, an instruction processing device, electronic equipment and a medium of a double-emission pipeline, which improve the performance of a processor, and simultaneously, do not need to additionally increase hardware, so that the occupied area of the processor is controlled.
In order to solve the above technical problems, an embodiment of the present application provides an instruction processing method of a dual-issue pipeline, including: transmitting instructions according to a preset sequence by utilizing a double-in double-out queue; when the instructions are transmitted, sequentially distributing marks representing the transmission sequence for each instruction according to a preset sequence; and acquiring the marks of the instructions during the submission, and submitting the instructions in turn according to the sequence of the instructions recorded by the marks.
The embodiment of the application also provides an instruction processing device of the dual-emission pipeline, which comprises: the transmitting module is used for transmitting the instructions according to a preset sequence; the transmitting module includes: a double-input double-output queue, and a transmitting groove connected with an output interface of the double-input double-output queue; the marking module is used for sequentially distributing marks representing the transmission sequence for each instruction according to a preset sequence when the instructions are transmitted; and the submitting module is used for acquiring the marks of the instructions during the submitting, and sequentially submitting the instructions according to the sequence of the instructions recorded by the marks.
The embodiment of the application also provides electronic equipment, which comprises: at least one processor; and a memory communicatively coupled to the at least one processor; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor, so that the at least one processor can execute the instruction processing method of the dual-emission pipeline.
Embodiments of the present application also provide a computer readable storage medium storing a computer program which, when executed by a processor, implements the instruction processing method of the dual issue pipeline described above.
Compared with the prior art, the embodiment of the application utilizes the double-in and double-out queues to transmit the instructions according to the preset sequence; when the instructions are transmitted, identity tokens are sequentially distributed to the instructions according to a preset sequence; wherein the identity token is used for recording the order of the instructions; and acquiring identity tokens of all the instructions during submitting, and submitting all the instructions in sequence according to the sequence of the instructions recorded by the identity tokens. Therefore, the sequential double-emission pipeline scheme of instruction level parallelism is realized, the performance of the processor is improved relative to single emission, and compared with an out-of-order pipeline, the scheme does not need to additionally increase hardware and optimizes the occupied area of the processor.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings.
FIG. 1 is a flow chart of a method of instruction processing for a dual issue pipeline in accordance with an embodiment of the present application;
FIG. 2 is a schematic diagram of a dual-in dual-out queue according to an embodiment of the present application;
FIG. 3 is a schematic diagram of an instruction processing apparatus according to an embodiment of the present application with a dual issue pipeline;
fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, as will be appreciated by those of ordinary skill in the art, in the various embodiments of the present application, numerous technical details have been set forth in order to provide a better understanding of the present application. However, the technical solutions claimed in the present application can be implemented without these technical details and with various changes and modifications based on the following embodiments.
The following embodiments are divided for convenience of description, and should not be construed as limiting the specific implementation of the present application, and the embodiments may be mutually combined and referred to without contradiction.
The embodiment of the application relates to an instruction processing method of a double-emission pipeline, which comprises the following steps: transmitting instructions according to a preset sequence by utilizing a double-in double-out queue; when the instructions are transmitted, sequentially distributing marks representing the transmission sequence for each instruction according to a preset sequence; and acquiring the marks of the instructions during the submission, and submitting the instructions in turn according to the sequence of the instructions recorded by the marks. The performance of the processor is improved, and meanwhile, the area occupied by the processor is controlled without adding additional hardware.
The implementation details of the instruction processing method of the dual issue pipeline of this embodiment are specifically described below, and the following details are provided only for understanding, and are not necessary to implement this embodiment.
The instruction processing method of the dual issue pipeline in some embodiments is shown in FIG. 1, and includes:
step 101, transmitting instructions according to a preset sequence by utilizing a double-in double-out queue;
102, when instructions are transmitted, sequentially distributing marks representing the transmission sequence for each instruction according to a preset sequence;
step 103, obtaining the marks of the instructions during the submitting, and submitting the instructions in turn according to the order of the instructions recorded by the marks.
Specifically, when marks representing the transmitting sequence are sequentially allocated to each instruction according to a preset sequence, identity tokens can be sequentially allocated to each instruction according to the preset sequence, the identity tokens of each instruction are obtained during submission, and the submission is performed according to the sequence of the instructions recorded in the identity tokens; or sequentially distributing corresponding emission priorities for the instructions on the scoreboard according to a preset sequence, emitting the instructions according to the priorities when emitting, acquiring the instruction emission priority sequence on the scoreboard when submitting, and sequentially submitting the instructions.
The following describes the manner of transmitting instructions in a dual-input dual-output queue by taking the order of instruction transmission by means of an identity token as an example, and as shown in fig. 2, the dual-input dual-output queue includes two writing sides, namely writing sides enq0 and enq1 respectively; also included are two readout sides, readout sides deq0 and deq1, respectively; the instruction is distributed with identity tokens token on the reading side, the tokens with preset sequences are distributed for each instruction in turn according to the transmission sequence of the instruction on the reading side, for example, token0 is distributed for the first instruction, token1 is distributed for the second instruction, and so on. In assigning an identity token to an instruction, a token of a fixed bit width may be assigned, e.g., the number of bits of the identity token may be configured as 5 bits, etc. The identity token is recorded in the micro-operation instruction and is used for recording the instruction sequence. As shown in fig. 2, a register Token is maintained inside the transmitting module, and can be increased by 0, 1 or 2. When the pipeline flush signal arrives, all instructions in the issue module are flushed and the register Token is reset to a value of 1. Meanwhile, the Bypass with optional functions is configured, namely when the transmitting module is empty, the enqueued micro-operation can be directly sent to the dequeue interface, and one pipeline period is saved. When an instruction just enters the issue slot logic, it needs to be determined whether it is an atomic instruction. If an instruction is found to be an atomic instruction, it is necessary to wait until the pipeline is flushed before sending it to the issue slot.
The two write sides and the two read sides contained in the dual-in and dual-out queues can be regarded as two issue slots, and if there is no structural conflict, the two issue slots can issue two micro-operation instructions at the same time theoretically. To ensure the instruction issue sequence of the dual in and dual out queues, different priorities may be set for the two issue slots, for example, the priority of issue slot 1 is set higher than issue slot 2, if issue slot 1 successfully handshakes with the register file interface, but issue slot 2 does not successfully handshake with the register file interface, only one micro-operation instruction in issue slot 1 is transferred; if issue slot 2 successfully handshakes with the register file interface but issue slot 1 does not, then it is necessary to wait for the interface in issue slot 1 to handshake successfully. If the micro-operation in the launching tank 1 can be launched, the micro-operation in the launching tank 2 cannot be launched, and the micro-operation in the launching tank 2 is transferred to the launching tank 1 and launched through the launching tank 1. In particular, for the instruction CSR instruction of the control register, the issue is allowed only after all instructions of its predecessor have been committed (written back), i.e., the CSR instruction is not allowed to speculatively execute.
In some embodiments, the dual-in dual-out queue may be implemented by a first-in first-out chip (FIFO, first Input First Output).
In some embodiments, it is also necessary to ensure that the operands of the instruction are ready and there are no related structural conflicts before the instruction is issued in the preset order using the double-in double-out queue. Before the double-input double-output queue is used for transmitting instructions according to a preset sequence, whether the transmitting slot of the double-input double-output queue can normally transmit instructions or not is judged according to the record table, and the transmitting slot transmits instructions after the transmitting slot is determined to normally transmit the instructions. For example, whether the source register fed back by the Busy table of the record table reads information or not is judged, the register file and the transmitting slot are in a handshake state, the unit Busy information fed back by the execution unit and whether a flushing flow signal exists or not all affect the success or failure of the transmitting slot to transmit the instruction. Therefore, the above conditions need to be determined before an instruction is issued to ensure that the issued instruction can be received by a register or by an execution unit. The manner of recording whether the source register fed back by the BusyTable reads information may be: upon receipt of the query instruction, if the queried register 1 is busy state, then result 0 is returned, otherwise result 1 is returned.
Regarding the data update in the record table busy table, the update may be completed according to the information interaction with the transmitting slot and the Write Back unit Write Back, for example, the content information of the logical destination register (Rdst) of the instruction uop that has been transmitted in the present processing period is filled, and the register content update is performed by the information written Back by the Write Back unit Write Back. The content of the BusyTable storage can be refreshed by a refresh stream signal transmitted Back from the Write Back unit.
In some embodiments, the transmission slot is mainly free, the transmission slot is effective and stores a non-Load/Store instruction and the transmission slot is effective and stores a Load/Store instruction, wherein the transmission slot free state does not need to transmit an instruction, and does not need to make a judgment whether normal transmission can be performed before transmitting the instruction; and judging in the other two states.
In some embodiments, before instructions are issued in a preset order using the dual-in dual-out queue, if no VALID instructions are stored in the issue slot of the dual-in dual-out queue, the instructions are transferred to the issue slot through a VALID/READY handshake mechanism.
In some embodiments, the computing unit module may further set a bypass for caching a computation result obtained by a computation operation performed according to the instruction, where the bypass may be a multi-stage bypass, for example, two stages of bypass are added on a conventional basis, so that the result of the computing unit may be reserved for two periods, and the instruction dependent on the result of the computing unit may take a feedforward result in a wider period range, thereby effectively improving the working efficiency of the pipeline.
The above steps of the methods are divided, for clarity of description, and may be combined into one step or split into multiple steps when implemented, so long as they include the same logic relationship, and they are all within the protection scope of this patent; it is within the scope of this patent to add insignificant modifications to the algorithm or flow or introduce insignificant designs, but not to alter the core design of its algorithm and flow.
The embodiment of the application relates to an instruction processing device of a double-emission pipeline, which comprises the following components: the transmitting module is used for transmitting the instructions according to a preset sequence; the transmitting module includes: a double-input double-output queue, and a transmitting groove connected with an output interface of the double-input double-output queue; the marking module is used for sequentially distributing identity tokens to the instructions according to a preset sequence when the instructions are transmitted; wherein the identity token is used for recording the order of the instructions; and the submitting module is used for acquiring the identity tokens of the instructions during the submitting, and sequentially submitting the instructions according to the sequence of the instructions recorded by the identity tokens. The processor performance is improved, and meanwhile, the area occupied by the processor is controlled without adding additional hardware.
The specific structure of the instruction processing apparatus of the dual-issue pipeline is shown in fig. 3, and the front-end performs branch prediction and instruction pre-decoding, and the front-end structure may be replaced by other branch prediction structures and pre-decoding structures as appropriate. The front end enters the transmitting module of the transmitting stage after finishing the operation through the decoding unit 0 or the decoding unit 1, the transmitting module is used for delivering corresponding instructions to the executing unit, recording the sequence of the instructions, playing a role in instruction scheduling, managing the life cycle of the instructions, and performing write-back stage and instruction retirement after finishing the execution.
The instruction is launched before entering the execution unit. The execution Unit is responsible for executing the instruction, executes the valid instruction emitted by the emission Unit and gives a corresponding result, wherein the calculation Unit of the execution Unit comprises an operation Unit such as a floating point operation Unit (FPU, float-point Process Unit), a floating point Division Unit (Fdiv, float-point Divsiong Unit), a floating point Integer operation Unit (Fpiu, float-point to IntegerU nit), an arithmetic logic Unit (ALU, arithmetic Logical Unit), a Jump Unit (JMP, jump Unit), a multiplication Unit (Mul, multiple Unit), a Division Unit (Div, division Unit), an Integer-to-floating point operation Unit (Ifpu, inter-to-Float-point Unit), a memory access operation Unit (LSU, load Store Unit) and the like.
After execution ends, the write-back stage is entered, at which normally ending instructions are retired and abnormally ending instructions trigger an exception. Exception handling is controlled by the CSR. Retired instructions tell the issue stage to know that the issue stage needs to use when scheduling instructions.
It is to be noted that this embodiment is an apparatus embodiment corresponding to the above-described method embodiment, and this embodiment may be implemented in cooperation with the method embodiment. The related technical details mentioned in the method embodiment are still valid in this embodiment, and in order to reduce repetition, they are not described here again. Accordingly, the related technical details mentioned in the present embodiment may also be applied in the method embodiment.
It should be noted that, each module involved in this embodiment is a logic module, and in practical application, one logic unit may be one physical unit, or may be a part of one physical unit, or may be implemented by a combination of multiple physical units. In addition, in order to highlight the innovative part of the present application, elements that are not so close to solving the technical problem presented in the present application are not introduced in the present embodiment, but it does not indicate that other elements are not present in the present embodiment.
Embodiments of the present application relate to an electronic device, as shown in fig. 4, at least one processor 401; and a memory 402 communicatively coupled to the at least one processor 401; the memory 402 stores instructions executable by the at least one processor 401, and the instructions are executed by the at least one processor 401, so that the at least one processor 401 can execute the instruction processing method of the dual-issue pipeline.
Where memory 402 and processor 401 are connected by a bus, the bus may comprise any number of interconnected buses and bridges, the buses connecting the various circuits of the one or more processors and memory together. The bus may also connect various other circuits such as peripherals, voltage regulators, and power management circuits, which are well known in the art, and therefore, will not be described any further herein. The bus interface provides an interface between the bus and the transceiver. The transceiver may be one element or may be a plurality of elements, such as a plurality of receivers and transmitters, providing a means for communicating with various other apparatus over a transmission medium. The data processed by the processor is transmitted over the wireless medium via the antenna, which further receives the data and transmits the data to the processor.
The processor 401 is responsible for managing the bus and general processing and may also provide various functions including timing, peripheral interfaces, voltage regulation, power management, and other control functions. And memory 402 may be used to store data used by the processor in performing operations.
Embodiments of the present application relate to a computer-readable storage medium storing a computer program. The computer program implements the above-described method embodiments when executed by a processor.
That is, it will be understood by those skilled in the art that all or part of the steps in implementing the methods of the embodiments described above may be implemented by a program stored in a storage medium, where the program includes several instructions for causing a device (which may be a single-chip microcomputer, a chip or the like) or a processor (processor) to perform all or part of the steps in the methods of the embodiments described herein. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific embodiments in which the present application is implemented and that various changes in form and details may be made therein without departing from the spirit and scope of the present application.
Claims (10)
1. A method for processing instructions for a dual issue pipeline, comprising:
transmitting instructions according to a preset sequence by utilizing a double-in double-out queue;
when the instructions are transmitted, sequentially distributing marks representing the transmission sequence for each instruction according to the preset sequence;
and acquiring the marks of the instructions during the submission, and submitting the instructions in turn according to the sequence of the instructions recorded by the marks.
2. The method of claim 1, further comprising, prior to said issuing instructions in a predetermined order using a dual-in dual-out queue:
judging whether the transmitting slot of the double-in and double-out queue can normally transmit instructions according to a record table, and transmitting the instructions by the transmitting slot after determining that the transmitting slot can normally transmit the instructions;
the data recorded by the recording table is adjusted according to preset conditions, wherein the preset conditions comprise: whether the source register can read information, whether the register file and the transmitting slot are in a handshake state.
3. The method of claim 1, further comprising, prior to said issuing instructions in a predetermined order using a dual-in dual-out queue:
and if no VALID instruction is stored in the transmitting slot of the double-in double-out queue, transmitting the instruction to the transmitting slot through a VALID/READY handshake mechanism.
4. The method according to claim 2, further comprising, after the sequential commit of the instructions according to the order of the instructions recorded by the identity token:
generating a refreshing flow signal;
and responding to the refreshing flow signal, and refreshing the data recorded by the recording table.
5. The method according to claim 2, wherein the number of the issue slots is two, and priorities of the two issue slots are different;
the transmitting slot transmits the instruction, including:
under the condition that a high-priority transmitting slot and a register file interface successfully handshake, a low-priority transmitting slot and the register file do not successfully handshake, an instruction in the high-priority transmitting slot normally transmits, and the instruction in the low-priority transmitting slot is transferred to the high-priority transmitting slot to transmit;
and waiting for the instruction to be normally transmitted after the high-priority transmitting slot successfully handshakes under the condition that the high-priority transmitting slot and the register file interface do not successfully handshake and the low-priority transmitting slot and the register file successfully handshake.
6. The method for processing instructions in a dual issue pipeline according to claim 1, further comprising, after said issuing instructions in a predetermined order using a dual in and dual out queue:
and executing calculation operation according to the instruction, and sending the calculated result to a multi-stage bypass so as to cache the calculated result through the multi-stage bypass, wherein the caching time is at least two processing cycles.
7. The method for processing instructions in a dual issue pipeline according to claim 1, wherein sequentially allocating a flag indicating an issue order to each instruction according to the preset order comprises:
sequentially distributing identity tokens to the instructions according to the preset sequence;
or sequentially distributing corresponding emission priorities for the instructions on the scoreboard according to the preset sequence.
8. An instruction processing apparatus of a dual issue pipeline, comprising:
the transmitting module is used for transmitting the instructions according to a preset sequence; the transmitting module includes: a double-input double-output queue, and a transmitting groove connected with an output interface of the double-input double-output queue;
the marking module is used for sequentially distributing marks representing the transmission sequence for each instruction according to the preset sequence when the instructions are transmitted;
and the submitting module is used for acquiring the marks of the instructions during the submitting, and sequentially submitting the instructions according to the sequence of the instructions recorded by the marks.
9. An electronic device, comprising:
at least one processor; the method comprises the steps of,
a memory communicatively coupled to the at least one processor; wherein,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the dual issue pipelined instruction processing method of any one of claims 1 to 7.
10. A computer readable storage medium storing a computer program, wherein the computer program when executed by a processor implements the dual issue pipeline instruction processing method of any of claims 1 to 7.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210772559.0A CN117369878A (en) | 2022-06-30 | 2022-06-30 | Instruction processing method and device of double-emission pipeline, electronic equipment and medium |
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| CN202210772559.0A CN117369878A (en) | 2022-06-30 | 2022-06-30 | Instruction processing method and device of double-emission pipeline, electronic equipment and medium |
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