CN117369711A - Method for controlling a component and related product - Google Patents
Method for controlling a component and related product Download PDFInfo
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- CN117369711A CN117369711A CN202210772225.3A CN202210772225A CN117369711A CN 117369711 A CN117369711 A CN 117369711A CN 202210772225 A CN202210772225 A CN 202210772225A CN 117369711 A CN117369711 A CN 117369711A
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- 238000000034 method Methods 0.000 title claims abstract description 104
- 238000012545 processing Methods 0.000 claims abstract description 90
- 230000004044 response Effects 0.000 claims abstract description 57
- 230000008569 process Effects 0.000 claims abstract description 45
- 238000001514 detection method Methods 0.000 claims description 37
- 230000000977 initiatory effect Effects 0.000 claims description 19
- 238000012546 transfer Methods 0.000 abstract description 15
- 238000010586 diagram Methods 0.000 description 11
- 238000007726 management method Methods 0.000 description 9
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 239000007787 solid Substances 0.000 description 5
- 239000003999 initiator Substances 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000013507 mapping Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- CXOXHMZGEKVPMT-UHFFFAOYSA-N clobazam Chemical compound O=C1CC(=O)N(C)C2=CC=C(Cl)C=C2N1C1=CC=CC=C1 CXOXHMZGEKVPMT-UHFFFAOYSA-N 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229940044442 onfi Drugs 0.000 description 1
- 238000004148 unit process Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0611—Improving I/O performance in relation to response time
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0658—Controller construction arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0688—Non-volatile semiconductor memory arrays
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Abstract
The present application relates to methods for controlling components and related products. Wherein the method for controlling the component comprises: and processing the data movement command and generating indication information according to the configured time in response to the received data movement command, wherein the indication information is used for indicating that the data movement command processing is completed. According to the scheme, corresponding indication information can be generated by utilizing different configured computers in the process of processing the data transfer command, so that specific execution conditions of the command can be reflected through the indication information, and different requirements of users can be met.
Description
Technical Field
The present application relates generally to the field of storage technology. More particularly, the present application relates to a method for controlling a component, and a control component and a storage device performing the aforementioned method.
Background
FIG. 1A illustrates a block diagram of a solid state storage device. The solid state storage device 102 is coupled to a host for providing storage capability for the host. The host and solid state storage device 102 may be coupled by a variety of means including, but not limited to, connecting the host to the solid state storage device 102 via, for example, SATA (Serial Advanced Technology Attachment ), SCSI (Small Computer System Interface, small computer system interface), SAS (Serial Attached SCSI ), IDE (Integrated Drive Electronics, integrated drive electronics), USB (Universal Serial Bus ), PCIE (Peripheral Component Interconnect Express, PCIE, peripheral component interconnect Express), NVMe (NVM Express), ethernet, fibre channel, wireless communications network, and the like. The host may be an information processing device capable of communicating with the storage device in the manner described above, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, or the like. The storage device 102 (hereinafter, solid-state storage device will be simply referred to as storage device) includes an interface 103, a control section 104, one or more NVM chips 105, and a DRAM (Dynamic Random Access Memory ) 110.
The NVM chip 105 includes common storage media such as NAND flash memory, phase change memory, feRAM (Ferroelectric RAM, ferroelectric memory), MRAM (Magnetic Random Access Memory, magnetoresistive memory), RRAM (Resistive Random Access Memory, resistive memory), and the like.
The control unit 104 is used for controlling data transmission among the interface 103, the NVM chip 105 and the DRAM110, and also for memory management, host logical address to flash physical address mapping, erase balancing, bad block management, etc. The control component 104 can be implemented in a variety of ways, such as software, hardware, firmware, or a combination thereof, for example, the control component 104 can be in the form of an FPGA (Field-programmable gate array, field programmable gate array), an ASIC (Application Specific Integrated Circuit, application-specific integrated circuit), or a combination thereof. The control component 104 may also include a processor or controller in which software is executed to manipulate the hardware of the control component 104 to process IO (Input/Output) commands. Control unit 104 may also be coupled to DRAM110 and may access data of DRAM 110. FTL tables and/or cached data of IO commands may be stored in the DRAM.
The control section 104 includes a flash interface controller (or referred to as a media interface controller, a flash channel controller) coupled to the NVM chip 105, which issues commands to the NVM chip 105 in a manner conforming to an interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives a command execution result output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", and the like.
Referring to fig. 1B, the control part includes a host interface 1041, a host command processing unit 1042, a storage command processing unit 1043, a medium interface controller 1044, and a storage medium management unit 1045. The host interface 1041 acquires an IO command provided by the host. The host command processing unit 1042 generates a storage command from the IO command and supplies the storage command to the storage command processing unit 1043. The store commands may access the same size of memory space, e.g., 4KB. The data unit of the data accessed by the corresponding one of the storage commands recorded in the NVM chip is referred to as a data frame. The physical page records one or more frames of data. For example, a physical page is 17664 bytes in size and a data frame is 4KB in size, and one physical page can store 4 data frames.
The storage medium management unit 1045 maintains a logical address to physical address conversion for each storage command. For example, the storage medium management unit 1045 includes FTL tables. For a read command, the storage medium management unit 1045 outputs a physical address corresponding to a logical address (LBA) accessed by the storage command. For a write command, the storage medium management unit 1045 allocates an available physical address thereto, and records a mapping relationship of a logical address (LBA) to which it accesses and the allocated physical address. The storage medium management unit 1045 also maintains functions required to manage NVM chips, such as garbage collection, wear leveling, and the like.
The storage command processing unit 1043 operates the medium interface controller 1044 to issue a storage medium access command to the NVM chip 105 according to the physical address supplied from the storage medium management unit 1045.
For the sake of clarity, the command sent by the host to the storage device 102 is referred to as an IO command, the command sent by the host command processing unit 1042 to the storage command processing unit 1043 is referred to as a storage command, the command sent by the storage command processing unit 1043 to the media interface controller 1044 is referred to as a media interface command, and the command sent by the media interface controller 1044 to the NVM chip 105 is referred to as a storage media access command. The storage medium access command follows the interface protocol of the NVM chip.
Fig. 1C shows a circuit structure of a control unit for processing NVMe commands in the prior art. As shown in fig. 1C, the host command processing unit 1042 in the control section includes a shared memory and a DMA unit; the store command processing unit 1043 includes an SGL/PRP cache unit, an SGL/PRP unit, and a read initiation circuit. The host transmits NVMe commands conforming to the NVMe protocol to the storage device through the host interface, and the host interface transmits the NVMe commands to the shared memory for storage. Since the NVMe protocol definition indicates access information through a scatter gather table (Scatter Gather List, abbreviated SGL) or a memory area page ((Physical Region Page, abbreviated PRP) field, the in-storage-device storage command processing unit 1043 parses the NVMe command to obtain SGL/PRP after receiving the NVMe command, and provides the NVMe command to the SGL/PRP unit.
Taking the processing procedure of the SGL unit as an example (the processing procedure of the PRP unit is the same and the processing procedure of the PRP unit is not described any more), if the read command carries the SGL, the SGL is cached in the cache unit, and if the read command carries the SGL pointer, the SGL is obtained from the host through the host interface and cached in the cache unit; next, one or more data movement command groups (DMA command groups) are generated from the information described by the one or more SGL descriptors in the SGL, and the DMA command groups are stored in the shared memory. Wherein a DMA command set includes one or more DMA commands. Then, the read initiating circuit triggers the DMA unit to process the DMA command and move the data indicated by the DMA command. After the DMA unit completes processing all DMA commands corresponding to the NVMe command, a message (NVMe CPL) of the completion of the processing of the NVMe command may be provided to the host through the read initiation circuit. Wherein, the NVMe CPL is a message that indicates that the processing of the NVMe command is completed and is specified by the NVMe protocol, and generally the host calculates the processing delay of the NVMe command according to the time interval from when the NVMe command is issued to when the CPL (Compleat Message) corresponding to the NVMe command is received.
Disclosure of Invention
Typically, each time a DMA command is processed by a DMA unit, the DMA unit sends a message that the DMA command is processed to a read initiator circuit, and the read initiator circuit recognizes that NVMe CPL is provided to the host after receiving all the messages that the DMA command corresponding to the NVMe command is processed. That is, the processing delay time of the NVMe command is related to the processing completion time of each DMA command corresponding to the NVMe command, and each DMA command processing completion time is related to the processing delay of each circuit in the DMA unit. For example, when the data to be moved indicated by the DMA command is also encrypted and/or integrity checked during processing thereof, for example, when the data is encrypted using a AES (Advanced Encryption Standard) encryption algorithm and/or integrity checked using a PI (Protect Information) signature, it takes a long time to perform the PI/AES process, which may result in a longer time for each DMA command to be processed, thereby resulting in a significantly delayed time for the read initiator circuit to provide NVMe CPL to the host. However, when the DMA unit processes each DMA command, it is only necessary to send a message of the completion of the DMA command processing to the read initiator circuit, and the time consuming condition of each operation of the DMA unit when processing the DMA command is not known. In view of this, it is desirable to be able to know how much time the DMA unit takes for each operation when processing a DMA command in order to optimize the performance of the storage device and to meet different demands depending on the time taken for each operation.
According to the scheme provided by the embodiment of the application, corresponding indication information can be generated by utilizing different configured computers in the process of processing the data movement command, so that specific execution conditions of the command can be reflected through the indication information, and different requirements of users can be met.
According to a first aspect of the present application, there is provided a first method for controlling a component according to the first aspect of the present application, comprising: and processing the data movement command and generating indication information according to the configured time in response to the received data movement command, wherein the indication information is used for indicating that the data movement command processing is completed.
According to a first method for controlling a component of the first aspect of the present application, there is provided a second method for controlling a component according to the first aspect of the present application, further comprising: generating one or more data movement commands in response to receiving the NVMe commands; and generating completion information in response to receiving indication information of one, more or all data movement commands corresponding to the NVMe command, wherein the completion information indicates that the NVMe command processing is completed.
According to the first or second method for controlling a component of the first aspect of the present application, there is provided a third method for controlling a component according to the first aspect of the present application, processing the data move command and generating indication information according to configured timing, comprising: generating the indication information in the process of executing the data moving command to move the indicated data to be moved; and/or generating the indication information in response to the encryption processing of the data to be moved.
According to a method for controlling a component according to a first aspect of the present application, there is provided a method for controlling a component according to a fourth aspect of the present application, wherein processing the data movement command includes acquiring data to be moved indicated by the data movement command from a source end, calculating the data to be moved, and moving the data to be moved to a destination end; the configured time includes before the data to be moved is acquired from the source end, after the data to be moved is calculated, and/or after the data to be moved is moved to the destination end; the processing of the data movement command is not completed before the data to be moved is acquired from the source end, after the data to be moved is acquired from the source end and after the data to be moved is calculated, and the processing of the data movement command is completed at the timing after the data to be moved is moved to the destination end.
According to one of the first to fourth methods for controlling a component of the first aspect of the present application, there is provided a fifth method for controlling a component of the first aspect of the present application, wherein the control component is a DMA unit including a first data moving circuit, a second data moving circuit, and a data protection and detection circuit, the method comprising: the second data moving circuit generates first indication information in the process of responding to the execution of the data moving command to move the indicated data to be moved; and/or the data protection and detection circuit responds to the second indication information generated in the data processing process to be moved; and/or the first data moving circuit generates third indication information and/or fourth indication information in the process of responding to the execution of the data moving command to move the indicated data to be moved.
According to a fifth method for controlling a component of the first aspect of the present application, there is provided a sixth method for controlling a component of the first aspect of the present application, the second data movement circuit generating first indication information in response to executing the data movement command to move the data to be moved indicated by the second data movement circuit comprising: the second data moving circuit responds to the completion of moving the data to be moved to generate the first indication information.
According to a fifth method for controlling a component according to the first aspect of the present application, there is provided a seventh method for controlling a component according to the first aspect of the present application, the data protection and detection circuit generating second indication information in response to the data processing procedure to be moved includes: and when the data protection and detection circuit finishes the data processing to be moved, generating the second indication information.
According to a fifth method for controlling a component according to the first aspect of the present application, there is provided the eighth method for controlling a component according to the first aspect of the present application, the first data movement circuit generating third indication information and/or fourth indication information in response to executing the data movement command to move the data to be moved indicated by the first data movement circuit comprising: the first data moving circuit responds to the completion of moving the data to be moved to generate the third indication information; and/or the first data moving circuit responds to the start of moving the data to be moved to generate the fourth indication information.
According to one of the fifth to eighth methods for controlling a component of the first aspect of the present application, there is provided the ninth method for controlling a component of the first aspect of the present application, the DMA unit receiving a pair of data move commands, the pair of data move commands comprising a first type of data move command and a second type of data move command; the first data moving circuit generates the third indication information and/or the fourth indication information in response to the process of executing the first type data moving command to move the indicated data to be moved; and/or the second data moving circuit generates the first indication information in response to the second class data moving command being executed to move the indicated data to be moved.
According to a ninth method for controlling a component of the first aspect of the present application, there is provided the method for controlling a component according to the tenth aspect of the present application, the first data movement circuit generating the fourth indication information in response to starting execution of the first type data movement command; and/or the first data moving circuit generates the third indication information in response to the execution of the first type data moving command.
According to a ninth method for controlling a component according to the first aspect of the present application, there is provided the eleventh method for controlling a component according to the first aspect of the present application, wherein the second data movement circuit generates the first indication information in response to executing a complete second type data movement command.
According to one of a fifth method for controlling a component to an eleventh method for controlling a component of the first aspect of the present application, there is provided a twelfth method for controlling a component according to the first aspect of the present application, wherein the first data movement circuit executes a first data movement command and generates the third indication information in response to receiving the first data movement command; the first data movement circuit is used for responding to the received second data movement command, executing the second data movement command and generating the fourth indication information.
According to a fifth to eleventh methods for controlling a component according to the first aspect of the present application, there is provided a thirteenth method for controlling a component according to the first aspect of the present application, wherein the first data movement circuit is responsive to executing the second data movement command and generating the fourth indication information; the data protection and detection circuit responds to encryption processing of the data to be moved indicated by the first data movement command, and generates second indication information.
According to one of a fifth method for controlling a component to an eleventh method for controlling a component of the first aspect of the present application, there is provided the fourteenth method for controlling a component of the first aspect of the present application, wherein the data protection and detection circuit generates second instruction information in response to encryption processing of data to be moved indicated by the first data movement command; the second data movement circuit is used for responding to the received first data movement command, executing the first data movement command and generating the first indication information.
A fifth method for controlling a component according to the first aspect of the present application to a fourteenth method for controlling a component, there is provided a fifteenth method for controlling a component according to the first aspect of the present application, the method further comprising: and measuring the time required by each part of circuit of the DMA unit to process corresponding operation according to the indication information.
According to a fifteenth method for controlling a component of the first aspect of the present application, there is provided a method for controlling a component according to the sixteenth aspect of the present application, wherein the control component further comprises a read initiate circuit; measuring the time required by the first data moving circuit to process the data moving command according to the time when the third indication information and the fourth indication information are received by the reading initiating circuit; measuring the time required by the data protection and detection circuit to process the to-be-moved data according to the time when the reading initiating circuit receives the second indication information and the fourth indication information; and measuring the time required by the second data moving circuit to process the data moving command according to the time when the first indication information and the second indication information are received by the reading initiating circuit.
According to a second aspect of the present application, there is provided a first control component according to the second aspect of the present application, comprising: and the DMA unit is used for responding to the received data movement command, processing the data movement command and generating indication information according to the configured time, wherein the indication information is used for indicating the completion of the data movement command processing.
According to a first control component of a second aspect of the present application, there is provided a second control component of the second aspect of the present application, further comprising a command parsing circuit and a read initiation circuit, the command parsing circuit generating one or more data movement commands in response to receiving the NVMe command; the DMA unit sends the indication information to a reading initiating circuit; and the reading initiating circuit responds to the received indication information of all the data moving commands corresponding to the NVMe command to generate the completion information, wherein the completion information indicates that the NVMe command processing is completed.
According to a first control part of a second aspect of the present application, a third control part according to the second aspect of the present application is provided, wherein the DMA unit generates the indication information in response to processing the data to be moved indicated by the data movement command in the process of moving the data; and/or generating the indication information in response to the processing of the data to be moved.
According to a first control unit of a second aspect of the present application, there is provided a fourth control unit according to the second aspect of the present application, the DMA unit comprising a first data movement circuit, a second data movement circuit, a data protection and detection circuit and a buffer; the first data moving circuit is used for moving the data to be moved indicated by the data moving command from the source end to the cache; the second data moving circuit is used for moving the data to be moved indicated by the data moving command from the cache to the destination end; the data protection and detection circuit is used for calculating the data to be moved indicated by the data movement command.
According to a fourth control part of the second aspect of the present application, there is provided a fifth control part according to the second aspect of the present application, the second data movement circuit generating first indication information in response to executing the data movement command to move the data to be moved indicated by the second data movement circuit; the data protection and detection circuit responds to the second indication information generated in the data processing process to be moved; the first data moving circuit generates third indication information and/or fourth indication information in the process of responding to the data moving command to move the indicated data to be moved.
According to one of the first control means through the fourth control means of the second aspect of the present application, there is provided a sixth control means according to the second aspect of the present application, and the timing of the instruction information generation of any one or more of the DMA units may be set.
According to a third aspect of the present application there is provided a storage device according to the third aspect of the present application comprising a storage medium and a control unit as described in the second aspect of the present application.
Drawings
For a clearer description of embodiments of the present application or of the solutions of the prior art, reference will be made below to the accompanying drawings, which are used in the description of embodiments or of the prior art, it being obvious that the drawings in the description below are only some embodiments described in the present application, from which other drawings can also be obtained for a person skilled in the art;
FIG. 1A illustrates a block diagram of a solid state storage device;
FIG. 1B shows a schematic diagram of a prior art control unit;
FIG. 1C illustrates a prior art circuit configuration of a control component for processing NVMe commands;
FIG. 2 illustrates a schematic diagram of a method for controlling a component provided by an embodiment of the present application;
FIG. 3A is a schematic diagram illustrating an indication information generating process according to an embodiment of the present application;
FIG. 3B is a schematic diagram illustrating another process for generating indication information according to an embodiment of the present application; and
fig. 4 shows a schematic structural diagram of a control unit according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application, taken in conjunction with the accompanying drawings, clearly and completely describes the technical solutions of the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
Fig. 2 shows a schematic diagram of a method for controlling a component provided by an embodiment of the present application. As described above in connection with fig. 1A and 1B, the general storage device includes the control unit, and detailed descriptions of basic functions of the control unit and relationships between other components in the storage device may be referred to the foregoing related descriptions, which are not repeated herein. Meanwhile, the function of the control component is further expanded by using the method in fig. 2.
As shown in fig. 2, at step S201, the data move command may be processed in response to receipt of the data move command, and at step S202, the instruction information may be generated according to the configured timing. It should be noted that the number of data movement commands (DMA commands) is not limited herein, for example, the number of DMA commands is related to SGL descriptors in SGLs carried by NVMe commands. Each data movement command may configure a corresponding occasion to generate the indication information. In the process of executing the data movement command, if the execution condition accords with the corresponding time, the instruction information for indicating the completion of the data movement command processing can be generated. The timing can be set and adjusted as needed.
As an example, the aforementioned data move command may be generated according to the NVMe command. For example, one or more data movement commands may be generated in response to receiving the NVMe command. Specifically, after receiving the NVMe command, the NVMe command may be parsed to obtain an SGL field, and then one or more data movement commands may be generated according to information described by one or more SGL descriptors in the SGL.
Further, in some embodiments, the processing of the foregoing data movement command may specifically involve operations such as acquiring the data 1 from the source end, calculating the data 1, and moving the data 1 to the destination end, where the data 1 is the data to be moved indicated by the data movement command. Based on the several operations of the foregoing data movement command processing, the timing for generating the indication information indicating that the data movement command is completed may specifically include various timings capable of embodying the specific execution situation of the command, such as before the data 1 is acquired from the source, after the data 1 is calculated, and/or after the data 1 is moved to the destination. The timing before the data 1 is acquired from the source, after the data 1 is acquired from the source, and after the data 1 is calculated indicates that the processing of the data transfer command is not completed, and the timing after the data 1 is transferred to the destination indicates that the processing of the data transfer command is completed. For example, if the NVMe command corresponding to the data move command is a read command, the source end is the host, and the destination end is the DRAM in the storage device (as shown in fig. 1A); the data 1 is acquired from the source end, namely the instruction control part acquires the data to be moved indicated by the data movement command from the memory of the host, and the data 1 is moved to the destination end, namely the instruction control part moves the data to be moved to the DRAM. For the write command, the source terminal is a DRAM, the destination terminal is a host, and the process is similar to the read command processing process, and will not be described here. Therefore, the time for generating the indication information of the completion of the data transfer command can be configured at different operation stages of the processing process of the data transfer command according to specific application requirements, so that the time consumption of different operations in the processing process of the data transfer command can be known, and the NVMe command processing can be optimized according to the time consumption of each operation. In addition, the time for generating the indication information of the completion of the data transfer command can be configured according to different requirements, so that different requirements are met; for example, when the performance is greatly affected by the NVMe command delay, the timing of generating the indication information of the completion of the data movement command may be configured to generate the indication information before the data is acquired from the source.
As another example, the foregoing operations for acquiring data from the source terminal and transferring the data to the destination terminal are essentially two operations in the process of the control section executing the data transfer command to transfer the data to be transferred indicated by the command. The foregoing calculation of the data includes, but is not limited to, encryption of the data to be moved. Based on the above, the processing of the data movement command may further include executing the data movement operation indicated by the data movement command to move the data to be moved, and performing the encryption processing operation on the data to be moved. Based on this, the generation timing of the indication information may include: and generating the indication information in the process of executing the data moving command to move the indicated data to be moved. Or generating the indication information in response to the encryption processing process of the data to be moved. Or the instruction information is generated in the process of executing the data moving command to move the indicated data to be moved and in the process of encrypting the data to be moved. For example, the timing of the data transfer command corresponding to the NVMe command may be configured to control the DMA unit in the component before encrypting/decrypting (PI/AES) the data to be transferred indicated by the data transfer command. Therefore, the processing delay of the NVMe command received by the host is not changed obviously due to the encryption/decryption (PI/AES) of the data to be moved, so that the influence of the encryption/decryption on the processing delay of the NVMe command perceived by the host is reduced, and the influence of the NVMe command delay on the performance is further reduced.
Based on the above (as in fig. 1C), the DMA unit in the control section feeds back the instruction information of the DMA command processing completion to the read initiation circuit at the time of processing each DMA command, and based on this, the timing configuration of the DMA unit for generating the instruction information during the processing of each DMA command is further described below in conjunction with the specific structure of the DMA unit in the control section.
Fig. 3A illustrates a schematic diagram of an indication information generating process according to an embodiment of the present application. It should be noted that, the process of generating the one or more data movement commands from the NVMe command in fig. 3A may refer to the foregoing description related to fig. 1C, and will not be described herein. On this basis, the generation process of the instruction information is described in conjunction with the specific structure of the DMA unit in fig. 3A.
As shown in fig. 3A, the storage device includes a host interface, a DMA unit, a shared memory, a read generation circuit, and a memory (DRAM in fig. 3A). The DMA unit may include a data moving circuit 1, a data protection and detection circuit, and a data moving circuit 2. The host interface may receive an NVMe command, which is parsed to generate one or more data movement commands, and which is present in the shared memory. As an example, when the DMA command to be processed by the DMA unit is a DMA command corresponding to an NVMe read command, the data move circuit 1 responds to receiving the data move command, and acquires the data to be moved indicated by the data move command (indicated as "(1)" in fig. 3A), and supplies the acquired data to the data detection circuit (indicated as "(2)" in fig. 3A). The data protection and detection circuit may calculate (e.g., encrypt and/or perform integrity check, etc.) the data to be moved and record the detection result (indicated as "(3.1)" in fig. 3A) in the shared memory, for example, the detection result includes the detection result of data encryption and/or integrity check, etc. The data protection and detection circuit supplies the calculated data to be moved to the data moving circuit 2 (indicated as "(3.2)" in fig. 3A). The data moving circuit 2 moves the data to be moved acquired from the data protection and detection circuit into the DRAM (indicated as "(4)" in fig. 3A).
As another example, when the DMA command to be processed by the DMA unit is a DMA command corresponding to an NVMe write command, the data moving circuit 2 is configured to acquire, in response to receiving the DMA command, data to be moved indicated by the DMA command (indicated as "(5)" in fig. 3A) from the DMA command, and supply the acquired data to be moved to the data detecting circuit (indicated as "(3.3)" in fig. 3A); the data protection and detection circuit is used for encrypting and/or checking the integrity of the data to be moved to obtain a data encryption and/or integrity checking result, and recording the detection result (shown as "(3.1)" in fig. 3A) in the shared memory; the data moving circuit 1 moves the result data acquired from the data protection and detection circuit to the host (indicated as "(7)" in fig. 3A). In addition, the DMA unit acquires data to be moved from the host through the host interface or transmits the data to be moved to the host through the host interface (indicated as "(8)" in fig. 3A).
Since the DMA unit includes three circuit structures of the data moving circuit 1, the data moving circuit 2, and the data protection and detection circuit, each circuit structure performs a different operation in the DMA command processing. The foregoing has taught that the timing of generating the instruction information for the completion of the DMA command processing may be configured according to different operations, i.e., the timing of generating the instruction information per part of the circuits in the DMA unit may be configured.
For example, the data movement circuit 2 generates the indication information 1 in response to executing the data movement command to move the indicated data to be moved. For example, the data movement circuit 2 may generate the indication information 1 in response to completion of movement of the data to be moved.
By way of example, the data protection and detection circuit generates the indication information 2 in response to processing the data to be moved. Specifically, the data protection and detection circuit may generate the instruction information 2 when the processing of the data to be moved is completed. The data protection and detection circuit can encrypt data by adopting an AES encryption algorithm and can carry out integrity check on the data by adopting a PI signature. PI (Protect Information) refers to signing transmitted data. AES (Advanced Encryption Standard) is an advanced encryption standard employed for blocks, which is a symmetric encryption algorithm that uses the same key for encryption and decryption.
For example, the data movement circuit 1 generates the indication information 3 and/or the indication information 4 in response to executing the data movement command to move the indicated data to be moved. For example, the data movement circuit 1 may generate the instruction information 3 in response to completion of the movement of the aforementioned data to be moved. For another example, the data transfer circuit 1 may generate the instruction information 4 in response to the start of the transfer of the data to be transferred. It should be noted that the description of the process of generating the instruction information is merely an exemplary illustration, and the timing of generating the instruction information of the specific data movement command may be set according to the application requirements. It should be understood that the DMA unit in this application sets one of the generation instruction information 1, the instruction information 2, the instruction information 3, and the instruction information 4 at the time of processing each data move command.
In the above data movement command processing process, each component in the DMA unit may generate corresponding instruction information according to the configured timing. As an example, in some implementations, the data movement circuit 1 may execute the data movement command 1 and generate the indication information 3 in response to receiving the data movement command 1. And the data move circuit 1 executes the data move command and generates the instruction information 4 in response to receiving the data move command 2.
As an example, in some implementations, data mover circuit 1 is responsive to executing data mover command 2 and generates indication information 4. The data protection and detection circuit may generate the indication information 2 in response to the encryption processing of the data to be moved indicated by the data movement command 1.
For example, in some implementations, the data protection and detection circuit generates the indication information 2 in response to encrypting the data to be moved indicated by the data move command 1. And the data moving circuit 2 responds to the received data moving command 1, executes the data moving command 1 and generates the indication information 1.
Fig. 3B illustrates another schematic diagram of an indication information generating process according to an embodiment of the present application. As shown in fig. 3B, when an NVMe command is received, the NVMe command may be parsed to obtain an SGL field, and then a data move command pair is generated according to information described by each SGL descriptor in the SGL, where the data move command pair includes a class a data move command and a class B data move command. For example, the SGL descriptor may include a data block descriptor and a hole descriptor, where the source address of the class a data move command corresponding to the data block descriptor is the host address described by the SGL descriptor and its destination address is the cache circuit address, and the source address of the class B data move command is the cache circuit address and its destination address is the memory address. The source address of the class a data move command corresponding to the hole descriptor is the empty address described by the SGL descriptor, and its destination address is the cache circuit address, while the source address of the class B data move command is the cache circuit address, and its destination address is the memory address.
For example, the data movement circuit 1 generates the indication information 3 and/or the indication information 4 in response to executing the class a data movement command to move the indicated data to be moved. As another example, the data moving circuit 2 generates the indication information 1 in response to executing the class B data moving command to move the indicated data to be moved. Also for example, the data movement circuit 1 may generate the indication information 4 in response to starting to execute the class a data movement command, and/or the data movement circuit 1 may generate the indication information 3 in response to completing to execute the class a data movement command. Also by way of example, data mover circuit 2 may generate indication 1 in response to executing a complete class B data mover command. The data protection and detection circuit generates indication information 2 in response to the encryption processing of the data to be moved in the buffer circuit.
Further, as an example, when the indication information of one, a plurality of or all the data movement commands corresponding to the NVMe command is received, the completion information may be generated in response to the indication information of one data movement command corresponding to the NVMe command, the completion information may be generated in response to the indication information of a plurality of data movement commands corresponding to the NVMe command, or the completion information may be generated in response to the indication information of all the data movement commands corresponding to the NVMe command. In some embodiments, the NVMe commands may be parsed into one or more data movement commands. In particular, when the NVMe command is parsed into a plurality of data movement commands, it is determined that the completion information indicating the completion of the NVMe command processing can be generated based on the indication information of a single, a plurality or all of the plurality of data movement commands according to the actual application requirements.
Further, in some embodiments, the time required for each part of the circuitry of the DMA unit to process the corresponding operation may also be measured based on the aforementioned indication information. As an example, the time required for the data transfer circuit 1 to process the data transfer command may be measured according to the time when the foregoing reading initiation circuit receives the instruction information 3 and the instruction information 4. For example, the time required for the data to be moved can also be processed by the protection and detection circuit according to the time measurement data received by the reading initiating circuit and the indication information 2 and the indication information 4. Also by way of example, the time required for the data movement command to be processed may be measured by the data movement circuit 2 in accordance with the time at which the indication information 1 and the indication information 2 are received by the read initiating circuit.
Fig. 4 shows a schematic structural diagram of a control unit according to an embodiment of the present application.
As shown in fig. 4, the control part includes: and the DMA unit is used for responding to the received data movement command, processing the data movement command and generating indication information according to configured time. The instruction information is used for indicating that the data movement command processing is completed.
Further, the control component further includes a command parsing circuit and a read initiation circuit, wherein the command parsing circuit generates one or more data movement commands in response to receiving the NVMe commands. And the DMA unit sends the indication information to the read initiate circuit. Then, the read initiating circuit responds to the indication information of all the data moving commands corresponding to the received NVMe command to generate the completion information, wherein the completion information indicates that the NVMe command processing is completed.
Further, as an example, the DMA unit generates the indication information in response to the data to be moved indicated by the DMA unit in response to the data to be moved being moved by the DMA unit, and/or generates the indication information in response to the data to be moved being moved.
Further, the DMA unit may include, for example, a data moving circuit 1, a data moving circuit 2, a data protection and detection circuit and a buffer (not shown in fig. 4, refer to the DMA unit in fig. 3B). The data moving circuit 1 is configured to move data to be moved indicated by the data moving command from the source end to the cache. The data moving circuit 2 is used for moving the data to be moved indicated by the data moving command from the cache to the destination. The data protection and detection circuit is used for calculating the data to be moved indicated by the data movement command.
Further, as an example, the data movement circuit 2 generates the instruction information 1 in response to executing the data movement command to move the data to be moved indicated by the data movement circuit. The data protection and detection circuit generates indication information 2 in response to the processing of the data to be moved. The data moving circuit 1 generates the indication information 3 and/or the indication information 4 in response to executing the data moving command to move the indicated data to be moved. It should be noted that the timing of generating the indication information is merely an example, and the timing of generating the indication information of any one or more components in the DMA unit may be set to meet different application requirements. For example, it may be set in a DMA command, whereby the generation timing of the respective instruction information may be different for a plurality of DMA commands of the NVMe command. For another example, the generation occasions of all DMA commands may also be globally configured by the read initiate circuit.
The present application also provides a storage device that may include a storage medium and the control unit described above.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application. It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.
Claims (10)
1. A method for controlling a component, comprising:
and processing the data movement command and generating indication information according to the configured time in response to the received data movement command, wherein the indication information is used for indicating that the data movement command processing is completed.
2. The method of claim 1, further comprising:
generating one or more data movement commands in response to receiving the NVMe commands;
And generating completion information in response to receiving indication information of one, more or all data movement commands corresponding to the NVMe command, wherein the completion information indicates that the NVMe command processing is completed.
3. The method of claim 1, wherein,
the data movement command is processed, wherein the data movement command comprises the steps of obtaining data to be moved indicated by the data movement command from a source end, calculating the data to be moved, and moving the data to be moved to a destination end;
the configured time includes before the data to be moved is acquired from the source end, after the data to be moved is calculated, and/or after the data to be moved is moved to the destination end; the processing of the data movement command is not completed before the data to be moved is acquired from the source end, after the data to be moved is acquired from the source end and after the data to be moved is calculated, and the processing of the data movement command is completed at the timing after the data to be moved is moved to the destination end.
4. A method according to any of claims 1-3, wherein the control unit comprises a DMA unit comprising a first data movement circuit, a second data movement circuit and a data protection and detection circuit, the method comprising:
The second data moving circuit generates first indication information in the process of responding to the execution of the data moving command to move the indicated data to be moved; and/or
The data protection and detection circuit responds to the second indication information generated in the data processing process to be moved; and/or
The first data moving circuit generates third indication information and/or fourth indication information in the process of responding to the data moving command to move the indicated data to be moved.
5. The method of claim 4, wherein the second data movement circuit generating the first indication information in response to executing the data movement command to move the indicated data to be moved comprises:
the second data moving circuit responds to the completion of moving the data to be moved to generate the first indication information.
6. The method of claim 4, wherein the data protection and detection circuitry generating second indication information in response to processing the data to be moved comprises:
and when the data protection and detection circuit finishes the data processing to be moved, generating the second indication information.
7. The method of claim 4, wherein the first data movement circuit generating third and/or fourth indication information in response to executing the data movement command to move the indicated data to be moved comprises:
the first data moving circuit responds to the completion of moving the data to be moved to generate the third indication information; and/or
The first data moving circuit responds to the start of moving the data to be moved, and generates the fourth indication information.
8. The method according to any of claims 4-7, wherein the DMA unit receives a pair of data move commands, the pair of data move commands comprising a first type of data move command and a second type of data move command;
the first data moving circuit generates the third indication information and/or the fourth indication information in response to the process of executing the first type data moving command to move the indicated data to be moved; and/or
The second data moving circuit generates the first indication information in response to the second class data moving command being executed to move the indicated data to be moved.
9. The method of any of claims 4-8, wherein the control component further comprises a read initiation circuit;
The reading initiating circuit measures the time required by the first data moving circuit to process the data moving command according to the time for receiving the third indication information and the fourth indication information;
measuring the time required by the data protection and detection circuit to process the to-be-moved data according to the time when the reading initiating circuit receives the second indication information and the fourth indication information;
the reading initiating circuit measures the time required by the second data moving circuit to process the data moving command according to the time for receiving the first indication information and the second indication information.
10. A control unit, characterized by comprising: a DMA unit, wherein,
the DMA unit responds to the received data movement command, processes the data movement command and generates indication information according to configured time, wherein the indication information is used for indicating that the data movement command processing is completed.
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