CN117354256B - Rate matching method, device, equipment and storage medium - Google Patents
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Abstract
The invention belongs to the technical field of wireless communication, and discloses a rate matching method, a device, equipment and a storage medium. The method comprises the following steps: determining input data according to the parallel path number of the parallel gardner time synchronization; after configuring a valid enabling signal for the input data, grouping the input data to obtain a plurality of grouping data; counting the number of valid bits of each packet data based on the valid enable signal; determining initial addresses corresponding to the packet data according to the effective bit number; writing the effective data of each packet data into the FIFO array according to the initial address; and when the cache data of the FIFO array is larger than the threshold value, reading the cache data of the FIFO array to complete the rate matching of the data. By the method, the effective data can be buffered into the FIFO array in sequence easily and quickly.
Description
Technical Field
The present invention relates to the field of wireless communications technologies, and in particular, to a rate matching method, apparatus, device, and storage medium.
Background
The traditional rate matching method is generally carried out by traversing the effective positions of all data, the traditional method can solve the problem of low-speed or less parallel path number data extraction, and the 8-path, 16-path and 32-path or even higher parallel path numbers can greatly improve the complexity of the system, and if the parallel path number is more, the traditional method is still adopted for rate matching, so that the hardware resource consumption is high.
Disclosure of Invention
The invention mainly aims to provide a rate matching method, a device, equipment and a storage medium, and aims to solve the technical problem that the hardware resource consumption is high due to the fact that the rate matching is carried out in a traditional mode when the number of parallel paths is large in the prior art.
To achieve the above object, the present invention provides a rate matching method, including the steps of:
determining input data according to the parallel path number of the parallel gardner time synchronization;
after configuring a valid enabling signal for the input data, grouping the input data to obtain a plurality of grouping data;
counting the number of valid bits of each packet data based on the valid enable signal;
determining initial addresses corresponding to the packet data according to the effective bit number;
writing the effective data of each packet data into the FIFO array according to the initial address;
and when the cache data of the FIFO array is larger than the threshold value, reading the cache data of the FIFO array to complete the rate matching of the data.
Optionally, the counting the number of valid bits of each packet data based on the valid enable signal includes:
and adding all bits which are the preset value in the effective enabling signals of each piece of grouping data to obtain the effective bit number of each piece of grouping data.
Optionally, the determining the initial address corresponding to each packet data according to the valid bit number includes:
determining a packet sequence number of each packet data;
accumulating the valid bit number of the packet data corresponding to the preset packet sequence number to obtain the inter-group valid bit number of each packet sequence number, wherein the preset packet sequence number comprises the current packet sequence number and all the previous packet sequence numbers corresponding to the current packet sequence number;
and determining the initial address corresponding to each packet data according to the number of the inter-group valid bits.
Optionally, the determining the initial address corresponding to each packet data according to the inter-group valid bit number includes:
determining a total initial address of the FIFO array;
and determining the initial address corresponding to each packet data according to the total initial address and the number of the inter-group valid bits.
Optionally, the determining the initial address corresponding to each packet data according to the total initial address and the inter-group valid bit number includes:
determining the total initial address as a first write address of the FIFO array, and determining the inter-group significant bit as an address offset of each group of data;
when the current packet data is first-time writing data, the first-time writing address is used as an initial address corresponding to the current packet data;
when the current packet data is not the first written data, determining the previous packet data of the current packet data, and determining the initial address corresponding to the current packet data according to the initial address and the address offset of the previous packet data.
Optionally, writing the valid data of each packet data into the FIFO array according to the initial address includes:
determining a target number of FIFOs in the FIFO array;
judging whether the initial address is larger than a preset number or not, wherein the preset number is determined according to the target number;
when the initial address is larger than the preset number, performing modulo processing on the initial address based on the target number to obtain an updated initial address;
and writing the effective data of each packet data into the FIFO array according to the updated initial address.
Optionally, when the buffered data of the FIFO array is greater than the threshold value, reading the buffered data of the FIFO array to complete rate matching of the data, including:
determining a fixed rate of the input data;
and when the cache data of the FIFO array is larger than a threshold value, reading the cache data from the lower part to the upper part of the FIFO array according to the fixed rate until the cache data is smaller than or equal to the threshold value, wherein the threshold value is determined according to the FIFO setting depth.
In addition, in order to achieve the above object, the present invention also proposes a rate matching device, including:
the determining module is used for determining input data according to the parallel path number of the parallel gardner time synchronization;
a configuration module, configured to group the input data after configuring a valid enable signal for the input data, so as to obtain a plurality of group data;
a statistics module, configured to count the number of valid bits of each packet data based on the valid enable signal;
the determining module is further used for determining an initial address corresponding to each piece of packet data according to the valid bit number;
the writing module is used for writing the effective data of each packet data into the FIFO array according to the initial address;
and the reading module is used for reading the cache data of the FIFO array when the cache data of the FIFO array is larger than the threshold value so as to complete the rate matching of the data.
In addition, in order to achieve the above object, the present invention also proposes a rate matching device including: a memory, a processor, and a rate matching program stored on the memory and executable on the processor, the rate matching program configured to implement the steps of the rate matching method as described above.
In addition, in order to achieve the above object, the present invention also proposes a storage medium having stored thereon a rate matching program which, when executed by a processor, implements the steps of the rate matching method as described above.
The rate matching method, the device, the equipment and the storage medium provided by the invention determine input data according to the parallel path number of the parallel gardner time synchronization; after configuring a valid enabling signal for the input data, grouping the input data to obtain a plurality of grouping data; counting the number of valid bits of each packet data based on the valid enable signal; determining initial addresses corresponding to the packet data according to the effective bit number; writing the effective data of each packet data into the FIFO array according to the initial address; and when the cache data of the FIFO array is larger than the threshold value, reading the cache data of the FIFO array to complete the rate matching of the data. By adopting the data grouping processing structure, the judgment of the multi-channel condition is simplified, the time sequence requirement of FPGA wiring is reduced, the code quantity can be reduced, the FPGA resource consumption can be greatly reduced, the method is suitable for data rate matching after time synchronization of all even number parallel paths, various data rate relations are adapted, the number of output data parallel paths is flexible and settable, the method has strong flexibility, universality and expandability, and compared with the traditional processing mode, the advantage of the method is more obvious when the number of parallel channels is larger.
Drawings
FIG. 1 is a schematic diagram of a rate matching device of a hardware operating environment according to an embodiment of the present invention;
FIG. 2 is a flow chart of a first embodiment of the rate matching method of the present invention;
FIG. 3 is a flow chart of the rate matching in the first embodiment of the rate matching method of the present invention;
fig. 4 is a schematic diagram of a specific flow chart of rate matching after 32 paths of parallel time synchronization in the first embodiment of the rate matching method of the present invention;
FIG. 5 is a flow chart of a second embodiment of the rate matching method of the present invention;
fig. 6 is a block diagram of a first embodiment of the rate matching device of the present invention.
The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Referring to fig. 1, fig. 1 is a schematic diagram of a rate matching device in a hardware operating environment according to an embodiment of the present invention.
As shown in fig. 1, the rate matching device may include: a processor 1001, such as a central processing unit (Central Processing Unit, CPU), a communication bus 1002, a user interface 1003, a network interface 1004, a memory 1005. Wherein the communication bus 1002 is used to enable connected communication between these components. The user interface 1003 may include a Display, an input unit such as a Keyboard (Keyboard), and the optional user interface 1003 may further include a standard wired interface, a wireless interface. The network interface 1004 may optionally include a standard wired interface, a Wireless interface (e.g., a Wireless-Fidelity (Wi-Fi) interface). The Memory 1005 may be a high-speed random access Memory (Random Access Memory, RAM) Memory or a stable nonvolatile Memory (NVM), such as a disk Memory. The memory 1005 may also optionally be a storage device separate from the processor 1001 described above.
Those skilled in the art will appreciate that the structure shown in fig. 1 is not limiting of the rate matching device and may include more or fewer components than shown, or may combine certain components, or may be a different arrangement of components.
As shown in fig. 1, an operating system, a network communication module, a user interface module, and a rate matching program may be included in the memory 1005 as one type of storage medium.
In the rate matching device shown in fig. 1, the network interface 1004 is mainly used for data communication with a network server; the user interface 1003 is mainly used for data interaction with a user; the processor 1001 and the memory 1005 in the rate matching apparatus of the present invention may be provided in the rate matching apparatus, and the rate matching apparatus calls the rate matching program stored in the memory 1005 through the processor 1001 and executes the rate matching method provided by the embodiment of the present invention.
Based on the hardware structure, the embodiment of the rate matching method is provided.
Referring to fig. 2, fig. 2 is a flow chart of a first embodiment of a rate matching method according to the present invention.
In this embodiment, the rate matching method includes the following steps:
step S10: the input data is determined based on the parallel number of parallel lanes of the parallel gardner time sync.
It should be noted that, the execution body of the embodiment may be a computing service device with functions of data processing, network communication and program running, such as a mobile phone, a tablet computer, a personal computer, or an electronic device or a rate matching device capable of implementing the above functions. The present embodiment and the following embodiments will be described below by taking the rate matching device as an example.
It should be noted that parallel Gardner time synchronization is a clock synchronization technique, and mainly uses monitoring of clock deviation in a received signal to adjust a local clock to keep synchronization with a transmission clock, so as to achieve reliable transmission of data, where the received signal is divided into several parallel paths.
In a specific implementation, as shown in fig. 3, if the number of parallel paths of the parallel gardner time synchronization is N, N paths of Data (i.e. input Data) are input, where the time sequence of the N paths of input Data is data_in [0], data_in [1], data_in [2], … data_in [ N-1], and the output N paths of Data are fifin [0], fifin [1], fifin [2], … fifin [ N-1] in sequence.
Step S20: after the valid enabling signal is configured for the input data, the input data is grouped to obtain a plurality of grouping data.
In a specific implementation, the valid enable signal configured for the input data is underwlow [ N-1:0]; the input data packet is specifically: n parallel inputs (n=4, 6, 8, 10, 12 … …), wherein each m input data is divided into one group (m=2/3/4, m=4 is generally higher in efficiency), and the N parallel inputs are matched with an effective enabling signal Underflow configured by the input data, and each m data is divided into one group, K groups are all provided, and k=n/m; the Data of the first group of Data is data_CH [0], data_CH [1], … data_CH [ m-1] and the effective Data enabling signal corresponding to the first group of Data is underwlow [ m-1:0]; the Data of the second group of packet Data is data_ch [ m ], data_ch [ m+1], … data_ch [2*m-1] and the valid Data enable signal corresponding to the second group of packet Data is underwlow [2*m-1:m ]. Data of the K-th group of packet Data is data_ch [ (K-1) ×m+0], data_ch [ (K-1) ×m+1], … data_ch [ N-1] and the valid Data enable signal corresponding to the K-th group of packet Data is underwlow [ N-1 (K-1) ×m ].
Step S30: and counting the number of valid bits of each packet data based on the valid enable signal.
In an embodiment, the counting the number of valid bits of each packet data based on the valid enable signal includes:
and adding all bits which are the preset value in the effective enabling signals of each piece of grouping data to obtain the effective bit number of each piece of grouping data.
In a specific implementation, the preset value is 1, taking the first packet data as an example, adding all the 1-bit numbers in the Underflow [ m-1:0] to count the effective bit number sum_group_1 of the first packet data, so as to count the effective bit number of the K packet data, and obtaining the effective bit numbers of each packet data as sum_group_1, sum_group_2 and sum_group_3.
Step S40: and determining the initial address corresponding to each packet data according to the valid bit number.
In an embodiment, the determining the initial address corresponding to each packet data according to the valid bit number includes:
determining a packet sequence number of each packet data;
accumulating the valid bit number of the packet data corresponding to the preset packet sequence number to obtain the inter-group valid bit number of each packet sequence number, wherein the preset packet sequence number comprises the current packet sequence number and all the previous packet sequence numbers corresponding to the current packet sequence number;
and determining the initial address corresponding to each packet data according to the number of the inter-group valid bits.
It should be noted that, the current packet sequence number refers to a packet sequence number that needs to determine the significance of the packet at the current time, specifically, for example, the packet sequence number of each packet is 1,2, and the number of the packet is 4, and if the current packet sequence number is 3, then all the previous packet sequence numbers corresponding to the current packet sequence number are 1 and 2, that is, the significance of the packet sequence number between the packets is determined to be 1,2, and 3.
In a specific implementation, sum_1_1=sum_group_1, sum_1_2=sum_group_1+sum_group_2, sum_group_1_3=sum_group_3, … … sum_1_k=sum_1_n/m_1+sum_group_k, where sum_1_1_1 is the number of valid bits of Group1 (first packet data), sum_1_2 is the Sum of the number of valid bits of Group1 (first packet data) and Group2 (second packet data), sum_1_3 is the Sum of the number of valid bits of Group1 (first packet data), group2 (second packet data), group3 (third packet data), and so on, the number of valid bits between groups of each packet sequence numbers is counted and can be used for subsequent calculation of the FIFO array address.
In one embodiment, the determining the initial address corresponding to each packet data according to the inter-group significant bit number includes:
determining a total initial address of the FIFO array;
and determining the initial address corresponding to each packet data according to the total initial address and the number of the inter-group valid bits.
It should be noted that, the total initial address of the FIFO array is the first write address of the FIFO array, and the total initial address of the FIFO array defaults to 0.
In one embodiment, the determining the initial address corresponding to each packet data according to the total initial address and the inter-group valid bit number includes:
determining the total initial address as a first write address of the FIFO array, and determining the inter-group significant bit as an address offset of each group of data;
when the current packet data is first-time writing data, the first-time writing address is used as an initial address corresponding to the current packet data;
when the current packet data is not the first written data, determining the previous packet data of the current packet data, and determining the initial address corresponding to the current packet data according to the initial address and the address offset corresponding to the previous packet data.
It should be noted that, when the first write address is generally default to 0 and the current packet data is the first write data, the first write address may be directly used as the initial address corresponding to the packet data; when the current packet data is not the first-time written data, the previous packet data of the current packet data needs to be determined first, and then the initial address corresponding to the current packet data is determined based on the initial address and the address offset of the previous packet data.
In a specific implementation, the initial address of each packet data is calculated as follows:
，
，
in the formula, the address offset of each packet data is respectively:、/>、/> ；/>representing the first write address, each clock beatUpdating the initial address of the FIFO array after writing the packet data +.>。
Step S50: and writing the effective data of each packet data into the FIFO array according to the initial address.
It should be noted that, each clock beat arrives, the effective enabling signal of each packet data is determined, the effective data of each packet data is written into the FIFO array in parallel according to the corresponding FIFO array packet address range, and the effective data of each packet data is written into the FIFO array at the same time in sequence, so that the buffer storage of the effective data into the FIFO array is completed according to the way that the parallel channel number is arranged from small to large and the corresponding FIFO array channel is arranged from small to large.
In one embodiment, writing the valid data of each packet data into the FIFO array according to the initial address includes:
determining a target number of FIFOs in the FIFO array;
judging whether the initial address is larger than a preset number or not, wherein the preset number is determined according to the target number;
when the initial address is larger than the preset number, performing modulo processing on the initial address based on the target number to obtain an updated initial address;
and writing the effective data of each packet data into the FIFO array according to the updated initial address.
It should be noted that, the target number refers to the number of FIFOs in the FIFO array, and the target number is N, so that it may be determined that the FIFO array is composed of N FIFOs, and the preset number is N-1.
In a specific implementation, when the initial address of the packet data is greater than a preset number, the updated initial address can be obtained after performing modulo processing on the initial address, and specifically, the calculation mode of the updated initial address is as follows:。
step S60: and when the cache data of the FIFO array is larger than the threshold value, reading the cache data of the FIFO array to complete the rate matching of the data.
It should be noted that, the buffer data of the FIFO array may be read according to the input/output rate matching relationship, when the buffer data amount of the FIFO array is greater than the threshold value, the read operation is performed, and when the buffer data amount of the FIFO array is less than or equal to the threshold value, the read operation is stopped, and when the buffer data amount of the FIFO array is less than or equal to the threshold value, the valid enable signal of the output data is in an invalid state, and all the buffer data in the FIFO array may be read once every time the buffer data is read, or some buffer data p=n/2, N/4, N/8 … … may be read.
In a specific implementation, as shown in fig. 4, the description is given by taking the parallel gardner time synchronization output data as 32 paths of parallel, and taking the rate matching relationship as the input data and taking 16 paths of output data as an example:
(1) Data packet:
in cooperation with the Data valid enable signals Underflow, every 4 paths of Data are divided into one Group, the Data data_CH0, data_CH1, data_CH2, data_CH3 and the corresponding valid Data enable signals Underflow [3:0] are the first Group1, the data_CH4, data_CH5, data_CH6, data_CH7 and the corresponding valid Data enable signals Underflow [7:4] are the second Group2, and the … data_CH28, data_CH29, data_CH30, data_CH31 and the corresponding valid Data enable signals Underflow [31:28] are the eighth Group8, which is 8 groups.
(2) Grouping statistics of the number of valid data bits:
taking Group1 as an example, when Underflow [3:0] =4' b0101, all bits of 1 are added, the number of statistics significant bits is sum_group_1=2, so that statistics of 8 groups of significant data bits are completed, and sum_group_1, sum_group_2, sum_group_3 … … sum_group_8 are generated.
(3) Counting the number of accumulated significant digits between groups:
sum_1_1=sum_group_1, sum_1_2=sum_group_1+sum_group_2, sum_group_1_3=sum_1_2+sum_group_3, … … sum_1_8=sum_1_7+sum_group_8. Where sum_1_1 is the Sum of the valid data bits of Group1, sum_1_2 is the Sum of the valid data bits of Group1 and Group2, sum_1_3 is the Sum of the valid data bits of Group1, group2, group3, and so on, statistics of inter-Group valid bit statistics is used for the subsequent write FIFO array address calculation.
(4) Writing FIFO array initial addresses：
The minimum channel number of the FIFO array is written in each clock beat, the initial value is 0, which means that the first time of writing the FIFO array from the FIFO channel 0, the sum_1_8 data is written in each clock beat to the sum_1_8 FIFO channels, and the initial address of the FIFO array is updated after the data is writtenUpdate mode->The write FIFO array is sequentially written from small to large FIFO channel numbers, and after the channel numbers exceed 31, the cyclic writing is started from channel 0, so that the initial address of the write FIFO array needs to be updated by module 32.
(5) Calculating initial addresses of write FIFO arrays of each group, and knowing the initial addresses of the write FIFO arraysThe initial address of each set of write FIFO arrays is determined as follows:
，
，
(6) Write FIFO array
Each clock beat arrives, each group of data enabling signals is judged, and corresponding valid data in the group is written into the FIFO array from the FIFO channel corresponding to the initial address of the write FIFO array. Data enable signals underwlow [3:0] such as Group1]=4’b0101,=12, then data_ch0 is written into FIFO channel 12 and data_ch2 is written into FIFO channel 13. And similarly, each group simultaneously writes the effective data into the corresponding FIFO channel to finish the data caching.
(7) When the number of the FIFO array caches is larger than the threshold, performing FIFO array reading operation, wherein the threshold is determined according to the user requirement and the FIFO setting depth, and reading FIFO queue data repeatedly by reading the low 16 channels and then reading the high 16 channels, so that the rate matching of the data is completed.
The present embodiment determines input data by the number of parallel ways according to the parallel gardner time synchronization; after configuring a valid enabling signal for the input data, grouping the input data to obtain a plurality of grouping data; counting the number of valid bits of each packet data based on the valid enable signal; determining initial addresses corresponding to the packet data according to the effective bit number; writing the effective data of each packet data into the FIFO array according to the initial address; and when the cache data of the FIFO array is larger than the threshold value, reading the cache data of the FIFO array to complete the rate matching of the data. By adopting the data grouping processing structure, the judgment of the multi-channel condition is simplified, the time sequence requirement of FPGA wiring is reduced, the code quantity can be reduced, the FPGA resource consumption can be greatly reduced, the method is suitable for data rate matching after time synchronization of all even number parallel paths, various data rate relations are adapted, the number of output data parallel paths is flexible and settable, the method has strong flexibility, universality and expandability, and compared with the traditional processing mode, the advantage of the method is more obvious when the number of parallel channels is larger.
Referring to fig. 5, fig. 5 is a flowchart of a second embodiment of a rate matching method according to the present invention.
Based on the above first embodiment, in the rate matching method of this embodiment, when the buffered data of the FIFO array is greater than the threshold value, the buffered data of the FIFO array is read to complete the rate matching of the data, including:
step S601: determining a fixed rate of the input data;
step S602: and when the cache data of the FIFO array is larger than a threshold value, reading the cache data from the lower part to the upper part of the FIFO array according to the fixed rate until the cache data is smaller than or equal to the threshold value, wherein the threshold value is determined according to the FIFO setting depth.
It should be noted that, the buffer data of the FIFO array may be read according to the input/output rate matching relationship, when the buffer data amount of the FIFO array is greater than the threshold value, the read operation is performed, and when the buffer data amount of the FIFO array is less than or equal to the threshold value, the read operation is stopped, and when the buffer data amount of the output data is less than or equal to the threshold value, the valid enable signal of the output data is in an invalid state, all the buffer data in the FIFO array may be read once when the buffer data is read each time, or some buffer data p=n/2, N/4, N/8 … …, etc. may be added, and the read needs to be sequentially read from the low-order part to the high-order part according to the input/output rate matching relationship, for example, the N/4 is used to read the low-P channel data first, then the 2*P-1~P channel data, then the 3*P-1 2*P channel data, then the N-1-3P channel data, and then the P-1~0 channel data may be read repeatedly and continuously, so as to complete the rate matching of the data.
The present embodiment provides for determining a fixed rate of the input data; and when the cache data of the FIFO array is larger than a threshold value, reading the cache data from the lower part to the upper part of the FIFO array according to the fixed rate until the cache data is smaller than or equal to the threshold value, wherein the threshold value is determined according to the FIFO setting depth. By adopting the mode, the structure of enabling the driving output data is adopted, so that the flexibility of rate matching is greatly improved, and the scheme is more adaptive.
In addition, the embodiment of the invention also provides a storage medium, wherein the storage medium stores a rate matching program, and the rate matching program realizes the steps of the rate matching method when being executed by a processor.
Referring to fig. 6, fig. 6 is a block diagram of a first embodiment of the rate matching device according to the present invention.
As shown in fig. 6, the rate matching device according to the embodiment of the present invention includes:
a determining module 10 for determining the input data according to the parallel path number of the parallel gardner time synchronization.
A configuration module 20, configured to group the input data after configuring the valid enable signal for the input data, so as to obtain a plurality of group data.
A statistics module 30, configured to count the number of valid bits of each packet data based on the valid enable signal.
The determining module 10 is further configured to determine an initial address corresponding to each packet data according to the valid bit number.
A writing module 40, configured to write the valid data of each packet data into the FIFO array according to the initial address.
And the reading module 50 is configured to read the buffered data of the FIFO array to complete rate matching of the data when the buffered data of the FIFO array is greater than the threshold value.
It should be understood that the foregoing is illustrative only and is not limiting, and that in specific applications, those skilled in the art may set the invention as desired, and the invention is not limited thereto.
The present embodiment determines input data by the number of parallel ways according to the parallel gardner time synchronization; after configuring a valid enabling signal for the input data, grouping the input data to obtain a plurality of grouping data; counting the number of valid bits of each packet data based on the valid enable signal; determining initial addresses corresponding to the packet data according to the effective bit number; writing the effective data of each packet data into the FIFO array according to the initial address; and when the cache data of the FIFO array is larger than the threshold value, reading the cache data of the FIFO array to complete the rate matching of the data. By adopting the data grouping processing structure, the judgment of the multi-channel condition is simplified, the time sequence requirement of FPGA wiring is reduced, the code quantity can be reduced, the FPGA resource consumption can be greatly reduced, the method is suitable for data rate matching after time synchronization of all even number parallel paths, various data rate relations are adapted, the number of output data parallel paths is flexible and settable, the method has strong flexibility, universality and expandability, and compared with the traditional processing mode, the advantage of the method is more obvious when the number of parallel channels is larger.
In an embodiment, the statistics module 30 is further configured to:
and adding all bits which are the preset value in the effective enabling signals of each piece of grouping data to obtain the effective bit number of each piece of grouping data.
In an embodiment, the determining module 10 is further configured to:
determining a packet sequence number of each packet data;
accumulating the valid bit number of the packet data corresponding to the preset packet sequence number to obtain the inter-group valid bit number of each packet sequence number, wherein the preset packet sequence number comprises the current packet sequence number and all the previous packet sequence numbers corresponding to the current packet sequence number;
and determining the initial address corresponding to each packet data according to the number of the inter-group valid bits.
In an embodiment, the determining module 10 is further configured to:
determining a total initial address of the FIFO array;
and determining the initial address corresponding to each packet data according to the total initial address and the number of the inter-group valid bits.
In an embodiment, the determining module 10 is further configured to:
determining the total initial address as a first write address of the FIFO array, and determining the inter-group significant bit as an address offset of each group of data;
when the current packet data is first-time writing data, the first-time writing address is used as an initial address corresponding to the current packet data;
when the current packet data is not the first written data, determining the previous packet data of the current packet data, and determining the initial address corresponding to the current packet data according to the initial address and the address offset of the previous packet data.
In an embodiment, the writing module 40 is further configured to:
determining a target number of FIFOs in the FIFO array;
judging whether the initial address is larger than a preset number or not, wherein the preset number is determined according to the target number;
when the initial address is larger than the preset number, performing modulo processing on the initial address based on the target number to obtain an updated initial address;
and writing the effective data of each packet data into the FIFO array according to the updated initial address.
In an embodiment, the reading module 50 is further configured to:
determining a fixed rate of the input data;
and when the cache data of the FIFO array is larger than a threshold value, reading the cache data from the lower part to the upper part of the FIFO array according to the fixed rate until the cache data is smaller than or equal to the threshold value, wherein the threshold value is determined according to the FIFO setting depth.
It should be noted that the above-described working procedure is merely illustrative, and does not limit the scope of the present invention, and in practical application, a person skilled in the art may select part or all of them according to actual needs to achieve the purpose of the embodiment, which is not limited herein.
In addition, technical details not described in detail in this embodiment may refer to the rate matching method provided in any embodiment of the present invention, which is not described herein.
Furthermore, it should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The foregoing embodiment numbers of the present invention are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.
From the above description of embodiments, it will be clear to a person skilled in the art that the above embodiment method may be implemented by means of software plus a necessary general hardware platform, but may of course also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. Read Only Memory (ROM)/RAM, magnetic disk, optical disk) and comprising several instructions for causing a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method according to the embodiments of the present invention.
The foregoing description is only of the preferred embodiments of the present invention, and is not intended to limit the scope of the invention, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.
Claims (7)
1. A rate matching method, the rate matching method comprising:
determining input data according to the parallel path number of the parallel gardner time synchronization;
after configuring a valid enabling signal for the input data, grouping the input data to obtain a plurality of grouping data;
counting the number of valid bits of each packet data based on the valid enable signal;
determining initial addresses corresponding to the packet data according to the effective bit number;
writing the effective data of each packet data into the FIFO array according to the initial address;
when the cache data of the FIFO array is larger than the threshold value, reading the cache data of the FIFO array to complete the rate matching of the data;
the determining the initial address corresponding to each packet data according to the valid bit number comprises the following steps:
determining a packet sequence number of each packet data;
accumulating the valid bit number of the packet data corresponding to the preset packet sequence number to obtain the inter-group valid bit number of each packet sequence number, wherein the preset packet sequence number comprises the current packet sequence number and all the previous packet sequence numbers corresponding to the current packet sequence number;
determining initial addresses corresponding to the packet data according to the number of the inter-group valid bits;
the determining the initial address corresponding to each packet data according to the inter-group valid bit number comprises the following steps:
determining a total initial address of the FIFO array;
determining an initial address corresponding to each packet data according to the total initial address and the inter-group valid bit number;
the determining the initial address corresponding to each packet data according to the total initial address and the inter-group valid bit number comprises the following steps:
determining the total initial address as a first write address of the FIFO array, and determining the inter-group significant bit as an address offset of each group of data;
when the current packet data is first-time writing data, the first-time writing address is used as an initial address corresponding to the current packet data;
when the current packet data is not the first written data, determining the previous packet data of the current packet data, and determining the initial address corresponding to the current packet data according to the initial address and the address offset of the previous packet data.
2. The method of claim 1, wherein counting the number of valid bits of each packet data based on the valid enable signal comprises:
and adding all bits which are the preset value in the effective enabling signals of each piece of grouping data to obtain the effective bit number of each piece of grouping data.
3. The method of claim 1, wherein writing valid data for each packet data into the FIFO array at the initial address comprises:
determining a target number of FIFOs in the FIFO array;
judging whether the initial address is larger than a preset number or not, wherein the preset number is determined according to the target number;
when the initial address is larger than the preset number, performing modulo processing on the initial address based on the target number to obtain an updated initial address;
and writing the effective data of each packet data into the FIFO array according to the updated initial address.
4. The method of claim 1, wherein reading the buffered data of the FIFO array to complete rate matching of the data when the buffered data of the FIFO array is greater than a threshold value comprises:
determining a fixed rate of the input data;
and when the cache data of the FIFO array is larger than a threshold value, reading the cache data from the lower part to the upper part of the FIFO array according to the fixed rate until the cache data is smaller than or equal to the threshold value, wherein the threshold value is determined according to the FIFO setting depth.
5. A rate matching device, comprising:
the determining module is used for determining input data according to the parallel path number of the parallel gardner time synchronization;
a configuration module, configured to group the input data after configuring a valid enable signal for the input data, so as to obtain a plurality of group data;
a statistics module, configured to count the number of valid bits of each packet data based on the valid enable signal;
the determining module is further used for determining an initial address corresponding to each piece of packet data according to the valid bit number;
the writing module is used for writing the effective data of each packet data into the FIFO array according to the initial address;
the reading module is used for reading the cache data of the FIFO array when the cache data of the FIFO array is larger than a threshold value so as to complete the rate matching of the data;
the determining module is further configured to:
determining a packet sequence number of each packet data;
accumulating the valid bit number of the packet data corresponding to the preset packet sequence number to obtain the inter-group valid bit number of each packet sequence number, wherein the preset packet sequence number comprises the current packet sequence number and all the previous packet sequence numbers corresponding to the current packet sequence number;
determining initial addresses corresponding to the packet data according to the number of the inter-group valid bits;
the determining module is further configured to:
determining a total initial address of the FIFO array;
determining an initial address corresponding to each packet data according to the total initial address and the inter-group valid bit number;
the determining module is further configured to:
determining the total initial address as a first write address of the FIFO array, and determining the inter-group significant bit as an address offset of each group of data;
when the current packet data is first-time writing data, the first-time writing address is used as an initial address corresponding to the current packet data;
when the current packet data is not the first written data, determining the previous packet data of the current packet data, and determining the initial address corresponding to the current packet data according to the initial address and the address offset of the previous packet data.
6. A rate matching device, the device comprising: a memory, a processor, and a rate matching program stored on the memory and executable on the processor, the rate matching program configured to implement the steps of the rate matching method of any of claims 1 to 4.
7. A storage medium having a rate matching program stored thereon, which when executed by a processor, implements the steps of the rate matching method according to any of claims 1 to 4.
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