CN117352023A - Ferroelectric memory, reading circuit and reading method of ferroelectric memory - Google Patents
Ferroelectric memory, reading circuit and reading method of ferroelectric memory Download PDFInfo
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- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
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- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
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- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
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Abstract
The application provides a ferroelectric memory, a reading circuit of the ferroelectric memory and a reading method, wherein the reading circuit comprises a first switching tube, a second switching tube, an equalizer and a sensitive amplifier. The equalizer is connected with the first ferroelectric memory cell through a first bit line, the equalizer is also connected with the second ferroelectric memory cell through a second bit line, the first switch tube and the second switch tube are respectively connected with the equalizer and the sense amplifier, and the first ferroelectric memory cell and the second ferroelectric memory cell share a first word line. By arranging the first switch tube and the second switch tube between the equalizer and the sense amplifier, the first ferroelectric memory unit and the second ferroelectric memory unit can share the same word line, and when the transistor in the first ferroelectric memory unit and the transistor in the second ferroelectric memory unit are conducted simultaneously, the load end connected with the ferroelectric memory can be ensured to be in an equilibrium state, so that the sense amplifier can be utilized to accurately read or write the stored information in the ferroelectric memory.
Description
Technical Field
The present disclosure relates to the field of ferroelectric memories, and in particular, to a ferroelectric memory, a readout circuit of a ferroelectric memory, and a readout method.
Background
Currently, dynamic random access memories (Dynamic Random Access Memory, DRAM) include: a memory unit, an equalizer and a sense amplifier. The output modes of the conventional DRAM mainly comprise: an output mode of a Folded Bit Line (FBL) and an output mode of an Open Bit Line (OBL).
For the folded Bit Line output mode and the open Bit Line output mode, since the memory cells in the DRAM store free charges, only one memory cell exists on the same Word Line (WL), the Bit Line (Bit Line, BL) and the reference Bit Line. This can lead to load mismatch problems in the DRAM connection, which in turn can affect the accuracy of the sense amplifier reading the data.
Disclosure of Invention
In view of this, the present application provides a ferroelectric memory, a readout circuit of the ferroelectric memory, and a readout method, so as to accurately read or write stored information in the ferroelectric memory using a sense amplifier.
In a first aspect, the present application provides a readout circuit of a ferroelectric memory, comprising: the device comprises a first switching tube, a second switching tube, an equalizer and a sense amplifier; the equalizer is connected with the first ferroelectric memory cell through a first bit line; the first switching tube is respectively connected with the equalizer and the sense amplifier; the equalizer is also connected with a second ferroelectric memory cell through a second bit line; the second switching tube is respectively connected with the equalizer and the sense amplifier; the first ferroelectric memory cell and the second ferroelectric memory cell share a first word line; the first ferroelectric memory cell and the second ferroelectric memory cell are any two ferroelectric memory cells in a ferroelectric memory cell array; the equalizer is used for balancing the voltage between the first bit line and the second bit line; the sense amplifier is used for amplifying voltages on the first bit line and the second bit line respectively so that the read-out circuit reads out or writes in storage information of ferroelectric storage units in the ferroelectric storage unit array.
Compared with the prior art, the first switch tube and the second switch tube are arranged between the equalizer and the sense amplifier, so that the first ferroelectric memory unit and the second ferroelectric memory unit share the same word line, and when the transistor in the first ferroelectric memory unit and the transistor in the second ferroelectric memory unit are conducted simultaneously, the load end connected with the ferroelectric memory can be guaranteed to be in an equilibrium state, and the sense amplifier can be used for accurately reading or writing the stored information in the ferroelectric memory.
In one possible design, in a first stage, the first switching tube and the second switching tube are both in an on state; in the second stage, the first switching tube and the second switching tube are in a closed state. In the third stage, the first switching tube is in a conducting state, and the second switching tube is in a closing state; in the fourth stage, the first switching tube and the second switching tube are both in a conducting state.
According to the method, the first switch tube and the second switch tube are controlled to be in the on state or the off state, when the storage information of the ferroelectric storage unit in the ferroelectric storage is read, the ferroelectric storage unit is isolated from the sense amplifier, the problem that the ferroelectric storage unit bears long-time interference is avoided, and the accuracy of reading the storage information is improved.
In a second aspect, the present application provides a ferroelectric memory comprising: an array of ferroelectric memory cells and a sensing circuit as described in any of the designs of the first aspect and the first aspect.
In one possible design, a first ferroelectric memory cell in the ferroelectric memory cell array includes one transistor and n capacitors; wherein n is a positive integer, the grid electrode of the transistor is connected with a first word line, the source electrode of the transistor is connected with a first bit line, the drain electrode of the transistor is connected with a first floating grid gate, the first floating grid gate is also connected with one end of each capacitor, and the other end of each capacitor is respectively connected with different plate lines.
The present application can increase the amount of stored data of the first ferroelectric memory cell by setting the first ferroelectric memory cell to include one transistor and n capacitors. A first floating gate node may also be provided in the first ferroelectric memory cell to accurately adjust the voltage based on whether or not the first bit line and the first floating gate are on.
In a third aspect, the present application provides a method of reading out a ferroelectric memory, applied to the ferroelectric memory as in the second aspect and any one of its designs, the method comprising: when a first switch tube and a second switch tube are in a conducting state in a first stage under the condition that a first ferroelectric memory cell and a second ferroelectric memory cell in a ferroelectric memory cell array share a first word line, balancing the voltage between a first bit line connected with the first ferroelectric memory cell and a second bit line connected with the second ferroelectric memory cell by using an equalizer; and in the second stage, when the first switch tube and the second switch tube are in the closed state, amplifying the voltages on the first bit line and the second bit line respectively by using a sensitive amplifier to determine the storage information in the first ferroelectric storage unit.
In one possible design, the first stage further includes: after the voltage of the first word line connected with the first ferroelectric memory cell is adjusted to be a first voltage, determining the voltage of a first floating gate connected with the first ferroelectric memory cell based on the second voltage of the first plate line connected with the first ferroelectric memory cell; the balancing, with an equalizer, a voltage between a first bit line connected to the first ferroelectric memory cell and a second bit line connected to the second ferroelectric memory cell, comprising: adjusting the first voltage of the first bit line and the third voltage of the second bit line to be fourth voltages according to the equalizer; the voltage values of the first voltage, the fourth voltage, the third voltage and the second voltage are sequentially increased.
In one possible design, after balancing the voltage between the first bit line connected to the first ferroelectric memory cell and the second bit line connected to the second ferroelectric memory cell with an equalizer, the first stage further comprises: after the first voltage of the first word line is adjusted to be a fifth voltage, the fourth voltage of the first bit line and the voltage of the first floating gate are both changed; wherein the fifth voltage is greater than the second voltage; the amplifying, by a sense amplifier, voltages on the first bit line and the second bit line, respectively, in the second stage, determining stored information in the first ferroelectric memory cell, including: and amplifying the changed voltage of the first bit line and the changed fourth voltage of the second bit line based on the sense amplifier, and determining storage information in the first ferroelectric storage unit.
In one possible design, before the determining the voltage of the first floating gate to which the first ferroelectric memory cell is connected based on the second voltage of the first plate line to which the first ferroelectric memory cell is connected, the method further comprises: after the voltage of the first word line is adjusted to the fifth voltage, adjusting the voltage of the first floating gate to the first voltage according to the first voltage of the first bit line; the determining the voltage of the first floating gate connected to the first ferroelectric memory cell based on the second voltage of the first plate line connected to the first ferroelectric memory cell comprises: if the first ferroelectric memory cell contains first memory information, changing the voltage of the first floating gate from the first voltage to a sixth voltage; if the first ferroelectric memory cell contains second memory information, changing the voltage of the first floating gate from the first voltage to a seventh voltage; the voltage values of the sixth voltage, the fourth voltage and the seventh voltage are sequentially reduced, and the first storage information and the second storage information are different storage information.
The first voltage of the first bit line is utilized to enable the first floating gate to have an initial voltage before determining the voltage of the first floating gate, and then the voltage of the first floating gate is respectively determined through different stored information in the first ferroelectric memory cell. After the first floating gate has an initial voltage, the voltage of the first floating gate can be more accurately adjusted. The voltage of the first floating gate, which is determined according to different stored information in the ferroelectric memory cell, is more accurate.
In one possible design, an equalizer includes a first transistor and a second transistor; the first transistor is used for controlling the voltage of the first bit line, and the second transistor is used for controlling the voltage of the second bit line; and when the voltage of the first floating gate is adjusted to be the first voltage according to the first voltage of the first bit line, the first transistor is in a conducting state, and the second transistor is in a closing state. The accuracy of the voltage of the first floating gate to the first voltage can be made higher by the on state of the first transistor and the off state of the second transistor in the equalizer.
In one possible design, the first transistor and the second transistor are both in a conductive state when the voltage of the first floating gate to which the first ferroelectric memory cell is connected is determined. The accuracy of the determined voltage of the first floating gate can be made higher by the on-state of the first transistor and the on-state of the second transistor in the equalizer.
In one possible design, the first transistor is in an off state before the first voltage of the first word line is adjusted to a fifth voltage; after the first voltage of the first word line is adjusted to a fifth voltage, the second transistor is in an off state. The on state and the off state of the first transistor and the second transistor are determined at the time before and after the conduction between the first bit line and the first floating gate, so that the fourth voltage of the first bit line and the voltage of the first floating gate can be more accurately shared.
In one possible design, the first transistor and the second transistor are both in an on state when determining the stored information in the first ferroelectric memory cell. Through the first transistor and the second transistor which are in the on state and the first switch tube and the second switch tube which are in the off state at this time, when the storage information of the ferroelectric storage unit in the ferroelectric storage is read, the ferroelectric storage unit is isolated from the sense amplifier, the problem that the ferroelectric storage unit bears long-time interference is avoided, and the accuracy of reading the storage information is improved.
In one possible design, the method further comprises: in the third stage, when the first transistor and the second transistor are both in an off state and the voltage of the first word line is the fifth voltage, the voltage of the first plate line is reduced to change the capacitance polarity state in the first ferroelectric memory cell. The polarity state of the capacitor in the first ferroelectric memory cell can be adjusted only by the on-state and the off-state of the first switch tube and the second switch tube, and the on-state and the off-state of the first transistor and the second transistor, so that the polarity state of the capacitor in the second ferroelectric memory cell is not changed.
In a fourth aspect, the present application provides an electronic device comprising a ferroelectric memory of any one of the designs of the second aspect and a circuit board, the ferroelectric memory being disposed on the circuit board.
In a fifth aspect, the present application provides a computer readable storage medium storing computer instructions that, when executed by a ferroelectric memory in the second aspect and any one of the designs thereof, cause the ferroelectric memory in the second aspect and any one of the designs thereof to perform the method of any one of the designs described above.
In a sixth aspect, the present application provides a computer program product comprising computer instructions which, when executed by a ferroelectric memory in the second aspect and any one of the designs thereof, cause the ferroelectric memory in the second aspect and any one of the designs thereof to perform the method of any one of the designs described above.
Drawings
FIG. 1 is a schematic diagram of a prior art read-out circuit of a memory;
fig. 2 is a schematic structural diagram of a readout circuit of a ferroelectric memory according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a read circuit of a ferroelectric memory when the first floating gate is precharged according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of a read circuit of a ferroelectric memory when the first floating gate voltage is redetermined according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a read-out circuit of a ferroelectric memory during charge sharing according to an embodiment of the present disclosure;
FIG. 6 is a schematic diagram of a readout circuit of a ferroelectric memory when a sense amplifier provided in an embodiment of the present application amplifies a voltage;
fig. 7 is a schematic structural diagram of a read circuit of a ferroelectric memory when information is stored in a first ferroelectric memory cell according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of a readout circuit of a ferroelectric memory when recovering a capacitor polarity state in a first ferroelectric memory cell according to an embodiment of the present application;
fig. 9 is a schematic structural diagram of a readout circuit of a ferroelectric memory in a standby state after completing a read/write operation according to an embodiment of the present application;
fig. 10 is a schematic diagram of a circuit simulation waveform according to an embodiment of the present application.
Detailed Description
In order to enable those skilled in the art to better understand the technical solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.
It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the present application described herein may be implemented in other sequences than those illustrated or otherwise described herein. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.
Currently, dynamic random access memories include: a memory unit, an Equalizer (EQ) and a Sense Amplifier (SA). The output modes of the conventional DRAM mainly comprise: an output mode of a folded bit line and an output mode of an open bit line. In the folded bit line output scheme and the open bit line output scheme, since the memory cells in the DRAM store free charges, only one memory cell is present in the bit line and the reference bit line on the same word line. As shown in fig. 1, when a first memory cell is present between a first word line and a first bit line, no memory cell is present between the first word line and a second bit line, and a second memory cell is present between the second bit line and the second word line. This can lead to load mismatch problems in the DRAM connection, which in turn can affect the accuracy of the sense amplifier reading the data.
Here, SAN and SAP in fig. 1 represent low and high voltages of the sense amplifier, respectively. The functional implementation of EQ, CSL, WE in fig. 1 and the like are described in detail below, and are not described in detail herein.
In view of this, embodiments of the present application provide a ferroelectric memory, a readout circuit of the ferroelectric memory, and a readout method. For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail with reference to the accompanying drawings.
As shown in fig. 2, a readout circuit of a ferroelectric memory according to an embodiment of the present application includes: the switching device comprises a first switching tube, a second switching tube, an equalizer and a sense amplifier. The equalizer is connected with the first ferroelectric memory cell through a first bit line, the first switch tube is respectively connected with the equalizer and the sensitive amplifier, the equalizer is also connected with the second ferroelectric memory cell through a second bit line, and the second switch tube is respectively connected with the equalizer and the sensitive amplifier. The first ferroelectric memory cell and the second ferroelectric memory cell share a first word line, where the first ferroelectric memory cell and the second ferroelectric memory cell are any two ferroelectric memory cells in the ferroelectric memory cell array.
Optionally, the equalizer includes a first transistor and a second transistor, and a source of the first transistor is connected to a drain of the second transistor. The drain electrode of the first transistor is connected with the first bit line, the source electrode of the second transistor is connected with the second bit line, and the voltage between the first bit line and the second bit line can be balanced through the equalizer.
The sense amplifier includes two inverters, and the two inverters are connected end to end, one inverter may include a P-type transistor and an N-type transistor, and the gates of the P-type transistor and the N-type transistor are connected. SAN and SAP represent the low voltage and high voltage of the sense amplifier, respectively. The voltages on the first bit line and the second bit line can be amplified by sense amplifiers, respectively, so that the read-out circuit reads out or writes in the stored information of the ferroelectric memory cells in the ferroelectric memory cell array.
According to the method, the first switch tube and the second switch tube are arranged between the equalizer and the sense amplifier, so that the first ferroelectric memory unit and the second ferroelectric memory unit share the same word line, and when the transistor in the first ferroelectric memory unit and the transistor in the second ferroelectric memory unit are conducted simultaneously, the load end connected with the ferroelectric memory can be guaranteed to be in an equilibrium state, and therefore the sense amplifier can be used for accurately reading or writing storage information in the ferroelectric memory.
Alternatively, as shown in fig. 2, a first ferroelectric memory cell in the ferroelectric memory cell array includes one transistor and n capacitors, for example, denoted by 1TnC (One Transistor and one Capacitors). Wherein n is a positive integer, the Gate of the transistor is connected with a first word line, the source of the transistor is connected with a first bit line, the drain of the transistor is connected with a first Floating Gate (FG), the first Floating Gate is also connected with one end of each capacitor, and the other end of each capacitor is respectively connected with a first plate line, a second plate line, … and an nth plate line. Here, each capacitor is connected in parallel. By setting the first ferroelectric memory cell to a structure of 1TnC, the amount of memory data of the first ferroelectric memory cell can be increased.
It should be understood that the first ferroelectric memory cell in the ferroelectric memory cell array is merely illustrated herein, and the specific structure of the first ferroelectric memory cell is not limited in this application. The ferroelectric memory cell array has the advantages of low power consumption, high read-write speed and high irradiation resistance compared with other memory cells, and can accurately read or write the memory information of the ferroelectric memory cells in the ferroelectric memory cell array.
In one possible design, the embodiments of the present application further provide a ferroelectric memory, including: the ferroelectric memory cell array, the first switching tube, the second switching tube, the equalizer and the sense amplifier. Here, the connection relationship between each device may refer to the connection relationship shown in fig. 2, and will not be described herein. For example, the ferroelectric memory may be a ferroelectric random access memory (Ferroelectric Random Access Memory, feRAM).
After describing the connection relation between the ferroelectric memory and the readout circuit of the ferroelectric memory provided by the embodiment of the present application, the readout method of the ferroelectric memory provided by the embodiment of the present application is further described, and may be applied to the ferroelectric memory described above, and specifically includes the following steps:
it is assumed that the stored information of a first ferroelectric memory cell in the ferroelectric memory cell array is read out, a second ferroelectric memory cell in the ferroelectric memory cell array serves as a reference ferroelectric memory cell for the first ferroelectric memory cell, and the second ferroelectric memory cell shares the same word line with the first ferroelectric memory cell. The initial voltage of the first word line connected with the first ferroelectric memory cell is V0, the initial voltage of the first plate line is V1, the initial voltage of the first bit line is V1, and the initial voltage of the second bit line connected with the second ferroelectric memory cell is V1. At this time, the first transistor and the second transistor, and the first switching transistor and the second switching transistor in the equalizer are all in on states. Here, V0 is smaller than V1, V0 may be 0V, V1 may be 1V, and this is merely illustrative.
First, as shown in fig. 3, the initial voltage of the first word line is adjusted, that is, the initial voltage V0 of the first word line is adjusted to V2.5. At this time, the first bit line and the first floating gate are in a conductive state, and the second bit line and the second floating gate are in a conductive state. The second transistor is set to an off state by setting the first transistor in the equalizer to an on state such that the first ferroelectric memory cell and the second ferroelectric memory cell are in an off state. That is, the voltage of the first bit line may be transferred to the first floating gate and the voltage of the second bit line may be transferred to the second floating gate, but the voltage of the first bit line and the voltage of the second bit line may not be transferred to each other. The first floating gate may be supplied with an initial voltage V0 in order to ensure that a voltage difference exists across the capacitor of the first ferroelectric memory cell in a subsequent step. Here, V2.5 may be 2.5V, which is only exemplified herein.
Next, as shown in fig. 4, the voltage of the first word line is continuously adjusted, that is, the voltage V2.5 of the first word line is adjusted to V0. At this time, the first bit line and the first floating gate are in a closed state, and the second bit line and the second floating gate are in a closed state. After the initial voltage V1 of the first Plate Line (PL) is adjusted to V2, the voltage of the first floating gate is re-determined according to the voltage V2 of the first Plate Line, the voltage V0 of the first floating gate, and the stored information of the first ferroelectric memory cell. Here, V2 may be 2V, which is only exemplified herein.
For example, if the first ferroelectric memory cell includes the first stored information "1", and both ends of the capacitor in the first ferroelectric memory cell are in the negative polarization state, when the voltage V2 of the first plate line is greater than the voltage V0 of the first floating gate, the polarization state of the capacitor in the first ferroelectric memory cell is changed, that is, the capacitor is changed from the negative polarization state to the positive polarization state, because the voltage difference between the first plate line and the first floating gate is in the positive polarization state. In this process, the charge on the capacitor in the first ferroelectric memory cell is transferred to the first floating gate such that the voltage of the first floating gate is adjusted from V0 to Vfg1.
If the first ferroelectric memory cell includes the second stored information "0", and both ends of the capacitor in the first ferroelectric memory cell are in the positive state, when the voltage V2 of the first plate line is greater than the voltage V0 of the first floating gate, the polarization state of the capacitor in the first ferroelectric memory cell will not be changed because the voltage difference between the first plate line and the first floating gate is in the positive state. In this process, the charge on the capacitor in the first ferroelectric memory cell is transferred to the first floating gate in small amounts, so that the voltage of the first floating gate is adjusted from V0 to Vfg0.
When the voltage of the first floating gate is redetermined, the first transistor and the second transistor in the equalizer may be set to be in a conductive state, and the voltage V0 of the first bit line and the voltage V1 of the second bit line may be adjusted to Vref by the equalizer. By simultaneously performing the above two steps, the processing speed can be increased. Here, vref is greater than V0 and less than V1.
Then, as shown in fig. 5, the voltage of the first plate line and the voltage of the first word line are continuously adjusted, that is, the voltage V2 of the first plate line is adjusted to V1, and the voltage V0 of the first word line is adjusted to V2.5. At this time, the first transistor of the equalizer is in an off state before adjusting the voltage of the first word line, and the second transistor of the equalizer is in an off state after adjusting the voltage of the first word line. This allows the voltage of the second floating gate to be adjusted to Vref in response to the voltage Vref of the second bit line. At the same time, the capacitance CBL of the first bit line and the capacitance Cfg of the first floating gate can be charge-shared. Charge sharing is performed, for example, by the following formulas one and two:
vfg1 cfg+vref cbl=vrd1 (cfg+cbl) equation one
Vfg0 cfg+vref cbl=vrd0 (cfg+cbl) formula two
After the charge sharing is completed, the voltage of the first bit line and the voltage of the first floating gate are both adjusted to Vrd1 or Vrd0. At this time, the voltage of the second bit line and the voltage of the second floating gate are both Vref. As shown in fig. 6, when the stored information in the first ferroelectric memory cell is "1", and the stored information is read from the first ferroelectric memory cell, the voltage of the first bit line is Vrd1, the voltage of the second bit line is Vref, and if Vref is smaller than Vrd1, the voltage of the first bit line and the voltage of the second bit line are amplified to V2 and V0, respectively, by the sense amplifier. When the stored information in the first ferroelectric memory cell is "0", and the first ferroelectric memory cell is read, the voltage of the first bit line is Vrd0, the voltage of the second bit line is Vref, and if Vref is greater than Vrd0, the voltage of the first bit line and the voltage of the second bit line are amplified to V0 and V2, respectively, by the sense amplifier.
As shown in fig. 7, the stored information in the first ferroelectric memory cell can be read or written by always driving the voltage of the first bit line and the voltage of the second bit line at V2 and V0 through the sense amplifier, or by always driving the voltage of the first bit line and the voltage of the second bit line at V0 and V2 through the sense amplifier. At this time, the first floating gate is in a conductive state with the first bit line, and the voltage of the first floating gate is also V0 or V2. Since the voltage of the first plate line is V1, in order to reduce the interference effect caused by the difference of the voltages across the capacitor of the first ferroelectric memory cell, the first switching transistor and the second switching transistor are turned off, and the first transistor and the second transistor in the equalizer are turned on. The voltage of the first bit line, the voltage of the first floating grid gate, the voltage of the second bit line and the voltage of the second floating grid gate are all adjusted to be V1 by utilizing the equalizer, and then the interference influence caused by different pressures at two ends of the capacitor of the first ferroelectric memory unit can be reduced.
After reading or writing the stored information of the first ferroelectric memory cell, since the polarity of the capacitor in the first ferroelectric memory cell is changed in the case of reading the stored information "1" of the first ferroelectric memory cell, it is necessary to restore the polarity of the capacitor. As shown in fig. 8, to ensure that only the capacitor polarity of the first ferroelectric memory cell is changed, the capacitor polarity of the second ferroelectric memory cell is not changed, the first transistor and the second transistor in the equalizer are both turned off, and the first switching transistor is in an on state, and the second switching transistor is in an off state. At this point, the sense amplifier transmits V2 to the first bit line and the first floating gate. By further adjusting the voltage of the first plate line, i.e. the voltage V1 of the first plate line is adjusted to V0, a voltage difference exists in the capacitor of the first ferroelectric memory cell, so that the polarity of the capacitor of the first ferroelectric memory cell can be restored.
After the capacitor polarity of the first ferroelectric memory cell is restored, as shown in fig. 9, the first transistor and the second transistor in the equalizer are both in an on state, and the first switching transistor and the second switching transistor are both in an on state. The voltage of the first plate line is adjusted from V0 to V1, and the voltage of the first bit line and the voltage of the second bit line are both adjusted to V1 by using an equalizer. Since the first bit line is in a conductive state with the first floating gate, the voltage of the first floating gate is also V1. At this time, the voltage difference across the capacitor of the first ferroelectric memory cell is 0, and the polarity state is not changed.
Finally, the voltage of the first word line is adjusted from V2.5 to V0, and the voltage of the first bit line, the voltage of the second bit line, the voltage of the first plate line, the voltage of the first floating gate and the voltage of the second floating gate are all V1. At this time, the voltage difference across the capacitor of the first ferroelectric memory cell is 0, and the polarity state is not changed. As shown in fig. 10, a schematic diagram of a circuit simulation waveform corresponding to each of the above steps is shown.
In addition, fig. 2 also shows the connection relationship of the second word line, the third ferroelectric memory cell, and the fourth ferroelectric memory cell, and the functional implementation may refer to the first word line, the first ferroelectric memory cell, and the second ferroelectric memory cell, which are not described herein. The Write Enable (WE) in fig. 2 may be used for writing stored information to the ferroelectric memory cells, and the current control logic (current steering logic, CSL) may be used for control of the current in the read-out circuits of the ferroelectric memory.
According to the method, the switching tube is arranged between the equalizer and the sense amplifier, and the polarity of the capacitor of the first ferroelectric memory unit can be recovered by utilizing the on state and the off state of the switching tube, and the interference influence caused by different pressures at two ends of the capacitor can be reduced when the stored information of the first ferroelectric memory unit is read or written. And further, the problem of lower accuracy in information storage of the ferroelectric memory unit is solved, and the power consumption is reduced.
The embodiment of the application also provides electronic equipment, which comprises the ferroelectric memory and a circuit board, wherein the ferroelectric memory is arranged on the circuit board.
The embodiments also provide a computer-readable storage medium storing computer instructions that, when executed by a ferroelectric memory, cause a readout method of the ferroelectric memory to be performed.
The embodiments also provide a computer program product comprising computer instructions which, when executed by a ferroelectric memory, cause the readout method of the ferroelectric memory to be performed.
That is, aspects of the methods provided herein may also be implemented in the form of a program product comprising program code for causing a computer device to carry out the steps of the method of reading out a ferroelectric memory as described herein above when the program code is run on a computer device or on a circuit product.
Furthermore, although the operations of the methods of the present application are depicted in the drawings in a particular order, this is not required to or suggested that these operations must be performed in this particular order or that all of the illustrated operations must be performed in order to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk ferroelectric memory, CD-ROM, optical ferroelectric memory, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable ferroelectric memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable ferroelectric memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.
Claims (15)
1. A read-out circuit of a ferroelectric memory, comprising: the device comprises a first switching tube, a second switching tube, an equalizer and a sense amplifier;
the equalizer is connected with the first ferroelectric memory cell through a first bit line; the first switching tube is respectively connected with the equalizer and the sense amplifier; the equalizer is also connected with a second ferroelectric memory cell through a second bit line; the second switching tube is respectively connected with the equalizer and the sense amplifier; the first ferroelectric memory cell and the second ferroelectric memory cell share a first word line; the first ferroelectric memory cell and the second ferroelectric memory cell are any two ferroelectric memory cells in a ferroelectric memory cell array;
the equalizer is used for balancing the voltage between the first bit line and the second bit line;
the sense amplifier is used for amplifying voltages on the first bit line and the second bit line respectively so that the read-out circuit reads out or writes in storage information of ferroelectric storage units in the ferroelectric storage unit array.
2. The readout circuit of claim 1, wherein in a first phase, the first switching tube and the second switching tube are both in an on state; in the second stage, the first switching tube and the second switching tube are in a closed state.
3. A sensing circuit according to claim 1 or 2, wherein in a third phase the first switching tube is in an on state and the second switching tube is in an off state; in the fourth stage, the first switching tube and the second switching tube are both in a conducting state.
4. A ferroelectric memory, comprising: an array of ferroelectric memory cells and a read-out circuit as claimed in any one of claims 1 to 3.
5. The ferroelectric memory of claim 4 wherein a first ferroelectric memory cell in said array of ferroelectric memory cells comprises a transistor and n capacitors; wherein n is a positive integer, the grid electrode of the transistor is connected with a first word line, the source electrode of the transistor is connected with a first bit line, the drain electrode of the transistor is connected with a first floating grid gate, the first floating grid gate is also connected with one end of each capacitor, and the other end of each capacitor is respectively connected with different plate lines.
6. An electronic device comprising the ferroelectric memory according to claim 4 or 5 and a circuit board, the ferroelectric memory being provided on the circuit board.
7. A method of reading out a ferroelectric memory as claimed in claim 4 or 5, applied to a ferroelectric memory, the method comprising:
when a first switch tube and a second switch tube are in a conducting state in a first stage under the condition that a first ferroelectric memory cell and a second ferroelectric memory cell in a ferroelectric memory cell array share a first word line, balancing the voltage between a first bit line connected with the first ferroelectric memory cell and a second bit line connected with the second ferroelectric memory cell by using an equalizer;
and in the second stage, when the first switch tube and the second switch tube are in the closed state, amplifying the voltages on the first bit line and the second bit line respectively by using a sensitive amplifier to determine the storage information in the first ferroelectric storage unit.
8. The readout method of claim 7, wherein the first stage further comprises:
after the voltage of the first word line connected with the first ferroelectric memory cell is adjusted to be a first voltage, determining the voltage of a first floating gate connected with the first ferroelectric memory cell based on the second voltage of the first plate line connected with the first ferroelectric memory cell;
the balancing, with an equalizer, a voltage between a first bit line connected to the first ferroelectric memory cell and a second bit line connected to the second ferroelectric memory cell, comprising:
adjusting the first voltage of the first bit line and the third voltage of the second bit line to be fourth voltages according to the equalizer; the voltage values of the first voltage, the fourth voltage, the third voltage and the second voltage are sequentially increased.
9. The sensing method of claim 8, wherein after balancing the voltage between the first bit line connected to the first ferroelectric memory cell and the second bit line connected to the second ferroelectric memory cell with an equalizer, the first stage further comprises:
after the first voltage of the first word line is adjusted to be a fifth voltage, the fourth voltage of the first bit line and the voltage of the first floating gate are both changed; wherein the fifth voltage is greater than the second voltage;
the amplifying, by a sense amplifier, voltages on the first bit line and the second bit line, respectively, in the second stage, determining stored information in the first ferroelectric memory cell, including:
and amplifying the changed voltage of the first bit line and the changed fourth voltage of the second bit line based on the sense amplifier, and determining storage information in the first ferroelectric storage unit.
10. The sensing method of claim 8, wherein prior to the determining the voltage of the first floating gate to which the first ferroelectric memory cell is connected based on the second voltage of the first plate line to which the first ferroelectric memory cell is connected, the method further comprises:
after the voltage of the first word line is adjusted to the fifth voltage, adjusting the voltage of the first floating gate to the first voltage according to the first voltage of the first bit line;
the determining the voltage of the first floating gate connected to the first ferroelectric memory cell based on the second voltage of the first plate line connected to the first ferroelectric memory cell comprises:
if the first ferroelectric memory cell contains first memory information, changing the voltage of the first floating gate from the first voltage to a sixth voltage; if the first ferroelectric memory cell contains second memory information, changing the voltage of the first floating gate from the first voltage to a seventh voltage; the voltage values of the sixth voltage, the fourth voltage and the seventh voltage are sequentially reduced, and the first storage information and the second storage information are different storage information.
11. The readout method of claim 10, wherein the equalizer comprises a first transistor and a second transistor; the first transistor is used for controlling the voltage of the first bit line, and the second transistor is used for controlling the voltage of the second bit line;
and when the voltage of the first floating gate is adjusted to be the first voltage according to the first voltage of the first bit line, the first transistor is in a conducting state, and the second transistor is in a closing state.
12. The method of sensing of claim 11, wherein the first transistor and the second transistor are both in an on state when determining a voltage of a first floating gate to which the first ferroelectric memory cell is connected.
13. The readout method of claim 11 or 12, wherein the first transistor is in an off state before adjusting the first voltage of the first word line to a fifth voltage; after the first voltage of the first word line is adjusted to a fifth voltage, the second transistor is in an off state.
14. The method of any of claims 11-13, wherein the first transistor and the second transistor are both in an on state when determining stored information in the first ferroelectric memory cell.
15. The readout method according to any one of claims 11 to 14, wherein the method further comprises:
in the third stage, when the first transistor and the second transistor are both in an off state and the voltage of the first word line is the fifth voltage, the voltage of the first plate line is reduced to change the capacitance polarity state in the first ferroelectric memory cell.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210744834.8A CN117352023A (en) | 2022-06-27 | 2022-06-27 | Ferroelectric memory, reading circuit and reading method of ferroelectric memory |
| PCT/CN2023/096131 WO2024001622A1 (en) | 2022-06-27 | 2023-05-24 | Ferroelectric memory, and reading circuit and method for ferroelectric memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210744834.8A CN117352023A (en) | 2022-06-27 | 2022-06-27 | Ferroelectric memory, reading circuit and reading method of ferroelectric memory |
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| CN202210744834.8A Pending CN117352023A (en) | 2022-06-27 | 2022-06-27 | Ferroelectric memory, reading circuit and reading method of ferroelectric memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2005332513A (en) * | 2004-05-21 | 2005-12-02 | Matsushita Electric Ind Co Ltd | Ferroelectric storage device and its read-out method |
| JP4147536B2 (en) * | 2005-06-22 | 2008-09-10 | セイコーエプソン株式会社 | Ferroelectric memory device and display driving IC |
| US7230868B2 (en) * | 2005-07-28 | 2007-06-12 | Texas Instruments Incorporated | Stable source-coupled sense amplifier |
| JP2016066394A (en) * | 2014-09-24 | 2016-04-28 | ラピスセミコンダクタ株式会社 | Ferroelectric memory |
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- 2022-06-27 CN CN202210744834.8A patent/CN117352023A/en active Pending
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