CN117350235A - Wiring method for reducing power consumption of clock network, computer equipment and storage medium - Google Patents
Wiring method for reducing power consumption of clock network, computer equipment and storage medium Download PDFInfo
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Abstract
The invention provides a wiring method for reducing power consumption of a clock network, computer equipment and a storage medium, wherein the method comprises the following steps: performing clock tree synthesis on the target metal wiring layer; determining the dynamic power consumption and the illegal time sequence path of the target metal wiring layer according to the comprehensive result of the clock tree; constructing an optimization factor according to the dynamic power consumption and the worst time sequence violation value in the violation time sequence path; sequentially adjusting the clock line width and the clock line spacing in the target metal wiring layer with the aim of minimizing the optimization factor; in response to insufficient wiring space when the clock line spacing is adjusted, the corresponding clock lines and the clock lines nearby are subjected to node fusion, and the clock line spacing after the node fusion is adjusted. The wiring method can realize the simultaneous consideration of power consumption and time sequence, and the node fusion is carried out in the process of adjusting the space between the clock lines, so that a larger wiring space is reserved for the adjustment of the space between the clock lines, and the dynamic power consumption can be further reduced.
Description
Technical Field
The present invention relates to the field of integrated circuit design, and in particular, to a wiring method, a computer device, and a storage medium for reducing power consumption of a clock network.
Background
In the current deep submicron design, the scale of the chip is increasingly complex and huge, the size of the transistor is smaller, the working frequency is higher, and accordingly, the power consumption of the chip is larger. Undoubtedly, reducing power consumption is a hot spot and difficult problem in the physical implementation of chips. In the whole chip working process, the clock signal is continuously turned over, so the power consumption on the clock network accounts for an important component of the total power consumption of the chip. Under the current advanced technology node, the power consumption on the clock network can be up to more than 50% of the total power consumption of the chip. Therefore, optimizing the power consumption on the clock network has significant consequences for reducing the total power consumption of the chip, which is a serious issue in the physical implementation process of the chip. The width and the wiring spacing of the clock net can be set by corresponding instructions in the EDA tool for the physical realization of the back end, and the dynamic power consumption on the clock net can be reduced by directly modifying the width and the wiring spacing. However, no standard theoretical design flow guidance exists at present, and only the individual experience of a chip designer is used for directly modifying the width of a clock line (clock net) and the wiring distance to optimize, so that on one hand, the dynamic power consumption of a clock network is difficult to optimize to the best; on the other hand, the clock line width and the wiring pitch change may cause a problem of timing deterioration. For example, when the width of the clock line is reduced and the wiring pitch of the clock line is increased, it is disadvantageous to satisfy the hold time; the width and wiring pitch of the clock lines have an effect on both cross talk (cross talk) and Electromigration (EM), which also have an effect on timing. Therefore, both power consumption optimization and timing optimization cannot be considered at the same time, and in order to modify the width and the wiring pitch by using the existing EDA tool instruction, further, power consumption reduction and timing convergence are realized, which can only be tried continuously according to experience of engineers. However, this method is time consuming and labor intensive and the resulting error per plate is relatively large.
Therefore, how to simultaneously consider the power consumption and the timing of the chip design is a technical problem that needs to be solved in the art.
Disclosure of Invention
In order to simultaneously consider the power consumption and the time sequence of chip design, in a first aspect of the invention, a wiring method for reducing the power consumption of a clock network is provided, and the method comprises the following steps: performing clock tree synthesis on the target metal wiring layer; determining the dynamic power consumption and the violation time sequence path of the target metal wiring layer according to the clock tree synthesis result; constructing an optimization factor according to the dynamic power consumption and the worst time sequence violation value in the violation time sequence path; sequentially adjusting the clock line width and the clock line spacing in the target metal wiring layer with the aim of minimizing the optimization factor; in response to insufficient wiring space when the clock line spacing is adjusted, the corresponding clock lines and the clock lines nearby are subjected to node fusion, and the clock line spacing after the node fusion is adjusted.
In one or more embodiments, the calculating the dynamic power consumption of the target metal wiring layer from the clock tree includes calculating using the following formula:
P dynamic state ＝P Switch +P Short circuit ＝C load *f*V DD 2 +C eff *f*V DD 2 ；
Wherein C is load Is the load capacitance, f is the clock frequency, V DD Is the power supply voltage, C eff Is the equivalent power consumption capacitance of the device when no load is applied.
In one or more embodiments, said constructing an optimization factor from said dynamic power consumption and a worst timing violation value in said violating timing path comprises constructing an optimization factor using the following formula:
K＝P dynamic state k1 *|WNS| k2 ；
Wherein K is an optimization factor, P Dynamic state For dynamic power consumption of the target metal wiring layer, |WNS| is the absolute value of the worst time sequence violation value in the violation time sequence path in the target metal wiring layer, and k1 and k2 are regulating coefficients for regulating P respectively Dynamic state And the convergence speed of the |wns| to the K value.
In one or more embodiments, the method further includes setting the regulation coefficient according to a requirement, and configuring the k1 to be greater than k2 when power consumption of the chip design needs to be guaranteed to be prioritized; when the time sequence priority of chip design needs to be ensured, configuring the k1 to be smaller than k2; wherein the value of k1 is set to 2 by default, and the value of k2 is set to 1.
In one or more embodiments, when a target chip design has a plurality of metal wiring layers, the sequentially adjusting the clock line width and the clock line pitch in the target metal wiring layers with the objective of minimizing the optimization factor includes: hold M i The clock line spacing of the layers is unchanged, the clock line width is gradually decreased according to a preset step value, and clock tree synthesis is carried out again; re-calculating the figure-of-merit according to the result of the clock tree synthesis, repeating the above processes until the minimum figure-of-merit value is obtained, and recording the corresponding clock line width as M i Optimal clock line width W of layer i The method comprises the steps of carrying out a first treatment on the surface of the Will M i The clock line width of the layer is set to W i Gradually increasing the clock line spacing according to a preset step value, and carrying out clock tree synthesis again; re-calculating a figure-of-merit factor according to the result of the clock tree synthesis, repeating the above processes until the minimum figure-of-merit factor value is obtained, and recording the corresponding clock line spacing as the optimal clock line spacing S of the Mi layer i The method comprises the steps of carrying out a first treatment on the surface of the Wherein the Mi layer is an i-th metal wiring layer.
In one or more embodiments, the methods of the present invention further include preferentially adjusting clock lines having a single bit register when adjusting the clock line spacing.
In one or more embodiments, in response to insufficient wiring space when adjusting the clock line pitch, performing node fusion on the corresponding clock line and the clock lines nearby, and adjusting the clock line pitch after the node fusion, including: and carrying out node fusion on the single-bit register node on the target clock line and the single-bit register nodes nearby to form the multi-bit register.
In one or more embodiments, the adjusting the clock now spacing in the target metal routing layer includes: the length of the target clock line and the distance between the target clock line and other clock lines are adjusted.
In a second aspect of the present invention, a computer device is presented, comprising: at least one processor; and a memory having stored therein an executable computer program which when executed by the at least one processor is adapted to carry out the steps of a wiring method for reducing power consumption of a clock network in any one of the method embodiments described below, comprising: performing clock tree synthesis on the target metal wiring layer; determining the dynamic power consumption and the violation time sequence path of the target metal wiring layer according to the clock tree synthesis result; constructing an optimization factor according to the dynamic power consumption and the worst time sequence violation value in the violation time sequence path; sequentially adjusting the clock line width and the clock line spacing in the target metal wiring layer with the aim of minimizing the optimization factor; in response to insufficient wiring space when the clock line spacing is adjusted, the corresponding clock lines and the clock lines nearby are subjected to node fusion, and the clock line spacing after the node fusion is adjusted.
In one or more embodiments, the calculating the dynamic power consumption of the target metal wiring layer from the clock tree includes calculating using the following formula:
pdynamic=pswitch+pshort=cload×f×vdd2+ceff×f×vdd2;
where Cload is the load capacitance, f is the clock frequency, VDD is the supply voltage, ceff is the equivalent power consumption capacitance of the device when it is idle.
In one or more embodiments, said constructing an optimization factor from said dynamic power consumption and a worst timing violation value in said violating timing path comprises constructing an optimization factor using the following formula:
K＝P dynamic state k1 *|WNS| k2 ；
Wherein, K is an optimization factor, P dynamic is the dynamic power consumption of the target metal wiring layer, WNS is the absolute value of the worst time sequence violation value in the violation time sequence path in the target metal wiring layer, and K1 and K2 are regulation coefficients respectively used for adjusting the convergence speed of P dynamic and WNS to the K value.
In one or more embodiments, the method further includes setting the regulation coefficient according to a requirement, and configuring the k1 to be greater than k2 when power consumption of the chip design needs to be guaranteed to be prioritized; when the time sequence priority of chip design needs to be ensured, configuring the k1 to be smaller than k2; wherein the value of k1 is set to 2 by default, and the value of k2 is set to 1.
In one or more embodiments, when a target chip design has a plurality of metal wiring layers, the sequentially adjusting the clock line width and the clock line pitch in the target metal wiring layers with the objective of minimizing the optimization factor includes: keeping the interval of clock lines of the Mi layer unchanged, gradually decreasing the width of the clock lines according to a preset step value, and carrying out clock tree synthesis again; re-calculating a figure-of-merit factor according to the result of the clock tree synthesis, repeating the above processes until the minimum figure-of-merit factor value is obtained, and marking the corresponding clock line width as the optimal clock line width Wi of the Mi layer; setting the clock line width of the Mi layer as Wi, gradually increasing the clock line spacing according to a preset step value, and carrying out clock tree synthesis again; re-calculating a figure-of-merit factor according to the comprehensive result of the clock tree, repeating the above processes until the minimum figure-of-merit factor value is obtained, and marking the corresponding clock line spacing as the optimal clock line spacing Si of the Mi layer; wherein the Mi layer is an i-th metal wiring layer.
In one or more embodiments, the methods of the present invention further include preferentially adjusting clock lines having a single bit register when adjusting the clock line spacing.
In one or more embodiments, in response to insufficient wiring space when adjusting the clock line pitch, performing node fusion on the corresponding clock line and the clock lines nearby, and adjusting the clock line pitch after the node fusion, including: and carrying out node fusion on the single-bit register node on the target clock line and the single-bit register nodes nearby to form the multi-bit register.
In one or more embodiments, the adjusting the clock now spacing in the target metal routing layer includes: the length of the target clock line and the distance between the target clock line and other clock lines are adjusted.
In a third aspect of the present invention, there is provided a readable storage medium comprising: an executable computer program which when executed by an executor is configured to implement the steps of a routing method for reducing power consumption of a clock network in any one of the method embodiments described below, comprising: performing clock tree synthesis on the target metal wiring layer; determining the dynamic power consumption and the violation time sequence path of the target metal wiring layer according to the clock tree synthesis result; constructing an optimization factor according to the dynamic power consumption and the worst time sequence violation value in the violation time sequence path; sequentially adjusting the clock line width and the clock line spacing in the target metal wiring layer with the aim of minimizing the optimization factor; in response to insufficient wiring space when the clock line spacing is adjusted, the corresponding clock lines and the clock lines nearby are subjected to node fusion, and the clock line spacing after the node fusion is adjusted.
In one or more embodiments, the calculating the dynamic power consumption of the target metal wiring layer from the clock tree includes calculating using the following formula:
pdynamic=pswitch+pshort=cload×f×vdd2+ceff×f×vdd2;
where Cload is the load capacitance, f is the clock frequency, VDD is the supply voltage, ceff is the equivalent power consumption capacitance of the device when it is idle.
In one or more embodiments, said constructing an optimization factor from said dynamic power consumption and a worst timing violation value in said violating timing path comprises constructing an optimization factor using the following formula:
wherein, K is an optimization factor, P dynamic is the dynamic power consumption of the target metal wiring layer, WNS is the absolute value of the worst time sequence violation value in the violation time sequence path in the target metal wiring layer, and K1 and K2 are regulation coefficients respectively used for adjusting the convergence speed of P dynamic and WNS to the K value.
In one or more embodiments, the method further includes setting the regulation coefficient according to a requirement, and configuring the k1 to be greater than k2 when power consumption of the chip design needs to be guaranteed to be prioritized; when the time sequence priority of chip design needs to be ensured, configuring the k1 to be smaller than k2; wherein the value of k1 is set to 2 by default, and the value of k2 is set to 1.
In one or more embodiments, when a target chip design has a plurality of metal wiring layers, the sequentially adjusting the clock line width and the clock line pitch in the target metal wiring layers with the objective of minimizing the optimization factor includes: keeping the interval of clock lines of the Mi layer unchanged, gradually decreasing the width of the clock lines according to a preset step value, and carrying out clock tree synthesis again; re-calculating a figure-of-merit factor according to the result of the clock tree synthesis, repeating the above processes until the minimum figure-of-merit factor value is obtained, and marking the corresponding clock line width as the optimal clock line width Wi of the Mi layer; setting the clock line width of the Mi layer as Wi, gradually increasing the clock line spacing according to a preset step value, and carrying out clock tree synthesis again; re-calculating a figure-of-merit factor according to the comprehensive result of the clock tree, repeating the above processes until the minimum figure-of-merit factor value is obtained, and marking the corresponding clock line spacing as the optimal clock line spacing Si of the Mi layer; wherein the Mi layer is an i-th metal wiring layer.
In one or more embodiments, the methods of the present invention further include preferentially adjusting clock lines having a single bit register when adjusting the clock line spacing.
In one or more embodiments, in response to insufficient wiring space when adjusting the clock line pitch, performing node fusion on the corresponding clock line and the clock lines nearby, and adjusting the clock line pitch after the node fusion, including: and carrying out node fusion on the single-bit register node on the target clock line and the single-bit register nodes nearby to form the multi-bit register.
In one or more embodiments, the adjusting the clock now spacing in the target metal routing layer includes: the length of the target clock line and the distance between the target clock line and other clock lines are adjusted.
The beneficial effects of the invention include: the invention provides a wiring method for reducing power consumption of a clock network, which realizes the simultaneous consideration of power consumption and time sequence by constructing an optimization factor according to the dynamic power consumption of a target metal wiring layer and the worst time sequence violation value in a violation time sequence path and sequentially adjusting the clock line width and the clock line interval in the target metal wiring layer by taking the minimum optimization factor as a target, and can not only leave a larger wiring space for adjusting the clock line interval but also further reduce the dynamic power consumption by carrying out a node fusion technology in the process of adjusting the clock line interval.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are necessary for the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention and that other embodiments may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a wiring method for reducing power consumption of a clock network according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a strategy for adjusting clock line width and clock line spacing during primary clock tree synthesis according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a node fusion process according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a computer device according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a readable storage medium according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention will be described in further detail with reference to the accompanying drawings.
It should be noted that, in the embodiments of the present invention, all the expressions "first" and "second" are used to distinguish two entities with the same name but different entities or different parameters, and it is noted that the "first" and "second" are only used for convenience of expression, and should not be construed as limiting the embodiments of the present invention, and the following embodiments are not described one by one.
In order to simultaneously consider the power consumption and the time sequence of chip design, the invention provides a wiring method for reducing the power consumption of a clock network. The following describes the implementation method of the present invention in more detail with reference to the accompanying drawings:
referring to fig. 1, a workflow of a wiring method for reducing power consumption of a clock network according to an embodiment of the invention is shown, including: s1, performing clock tree synthesis on a target metal wiring layer; s2, determining the dynamic power consumption and the violation time sequence path of the target metal wiring layer according to the clock tree synthesis result; s3, constructing an optimization factor according to the worst time sequence violation value in the dynamic power consumption and the violation time sequence path; step S4, sequentially adjusting the clock line width and the clock line spacing in the target metal wiring layer with the aim of minimizing the optimization factor; and S5, in response to insufficient wiring space when the clock line spacing is adjusted, carrying out node fusion on the corresponding clock lines and the clock lines nearby the corresponding clock lines, and adjusting the clock line spacing after the node fusion.
In particular, in digital integrated circuit designs, clock signals are fundamental to data transmission, which is decisive for the function, performance and stability of synchronous digital systems, so the nature of the clock signals and their distribution network are of paramount importance. Generally, clock signals have the greatest fan-out, the longest distance and the highest speed in the whole chip design, which must ensure that the time sequence can meet the requirements under various extreme conditions, and clock tree synthesis is used as a key step in the back-end design flow, so as to provide a method for balancing and distributing clock signals. Clock tree synthesis (Clock tree synthesis, CTS) is a process of de-balancing the delays of clock paths through a clock network that establishes buffers/inverters, where timing paths that do not meet timing requirements (e.g., setup time and hold time requirements) and clock frequencies on each clock line are determined. The purpose of step S1 is to obtain the result of the clock tree synthesis, which is the timing path and the clock frequency on each clock line that do not satisfy the timing requirement.
In a further embodiment, calculating the dynamic power consumption of the target metal wiring layer from the clock tree includes calculating using the following formula:
pdynamic=pswitch+pshort=c load *f*V DD 2 +C eff *f*V DD 2 (1)；
Wherein C is load Is the load capacitance, f is the clock frequency, V DD Is the power supply voltage, C eff Is the equivalent power consumption capacitance of the device when no load is applied.
As can be seen from the above formula (1), if the dynamic power consumption of the clock network is to be reduced, only three ways are possible: 1. reducing the power supply voltage; 2. load capacitance is reduced; 3. the clock frequency is reduced. Wherein the clock frequency f and the power supply voltage V DD It has been determined in chip architecture design that these two variables are difficult to adjust and optimize, so a common approach is by reducing the load capacitance (C load ) To reduce dynamic power consumption. Therefore, the invention selects the mode of combining two technologies of adjusting the width and the spacing of the clock lines and fusing the nodes of the clock lines to realize the reduction of the load capacitance (C load ) Thereby reducing dynamic power consumption.
In a further embodiment, constructing the optimization factor from the dynamic power consumption and the worst timing violation value in the violation timing path includes constructing the optimization factor using the following formula:
K＝P dynamic state k1 *|WNS| k2 (2)；
Wherein K is an optimization factor, P Dynamic state For dynamic power consumption of the target metal wiring layer, |WNS| is the absolute value of the worst time sequence violation value in the violation time sequence path in the target metal wiring layer, and k1 and k2 are regulating coefficients for regulating P respectively Dynamic state And the convergence speed of the |wns| to the K value.
In an alternative embodiment, the method of the invention further comprises setting a regulation and control coefficient according to the requirement, and when the priority of the power consumption of the chip design needs to be ensured, configuring k1 to be larger than k2; when the time sequence priority of chip design needs to be ensured, configuring k1 to be smaller than k2; wherein, the default value of k1 is 2, and the value of k2 is 1. Wherein the value ranges of k1 and k2 are positive integers which are more than or equal to 1 and less than or equal to 3.
In a further embodiment, when the target chip design has a plurality of metal wiring layers, sequentially adjusting the clock line width and the clock line pitch in the target metal wiring layers with the objective of minimizing the optimization factor, includes: keeping the interval of clock lines of the Mi layer unchanged, gradually decreasing the width of the clock lines according to a preset step value, and carrying out clock tree synthesis again; re-calculating a figure-of-merit factor according to the result of the clock tree synthesis, repeating the above processes until the minimum figure-of-merit factor value is obtained, and marking the corresponding clock line width as the optimal clock line width Wi of the Mi layer; setting the clock line width of the Mi layer as Wi, gradually increasing the clock line spacing according to a preset step value, and carrying out clock tree synthesis again; re-calculating a figure-of-merit factor according to the comprehensive result of the clock tree, repeating the above processes until the minimum figure-of-merit factor value is obtained, and marking the corresponding clock line spacing as the optimal clock line spacing Si of the Mi layer; wherein the Mi layer is an i-th metal wiring layer.
In an alternative embodiment, when clock tree synthesis is performed for the first time, the clock tree synthesis may be performed by setting to double the default wiring width and double the default wiring pitch, and then wiring the clock lines according to the clock tree synthesis result. Referring to fig. 2 for an embodiment, this approach can accelerate the iterative optimization efficiency.
In a further embodiment, the method of the present invention further comprises preferentially adjusting the clock lines with the single bit registers when adjusting the clock line spacing. Specifically, the advantage of preferentially adjusting the clock line with the single-bit register is that, firstly, the fan-out of the single-bit register is less, and the influence time sequence path is less when the clock line is adjusted; secondly, when the positions of the single-bit registers need to be adjusted simultaneously, fusion among the nodes of the single-bit registers is simpler.
In a further embodiment, in response to insufficient wiring space when adjusting the clock line pitch, performing node fusion on the corresponding clock line and the clock lines in the vicinity thereof and adjusting the clock line pitch after the node fusion, including: and carrying out node fusion on the single-bit register node on the target clock line and the single-bit register nodes nearby to form the multi-bit register. In the node fusion process, referring to fig. 3, as shown in fig. 3, the node fusion mode can reduce the length of a clock line, reduce the number of buffers and sink points (register nodes for receiving data), and simplify the wiring complexity.
In a further embodiment, adjusting the clock now pitch in the target metal wiring layer includes: the length of the target clock line and the distance between the target clock line and other clock lines are adjusted.
In a second aspect of the present invention, a computer device is presented, see fig. 4, comprising:
at least one processor 31; and a memory 30, the memory 30 having stored therein an executable computer program which, when executed by the at least one processor 31, is adapted to carry out the steps of a wiring method for reducing power consumption of a clock network as in any of the method embodiments described above.
In particular, memory 30 may include one or more computer-readable storage media, which may be non-transitory. Memory 30 may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 30 is at least used for storing a computer program 301, where the computer program, after being loaded and executed by the processor 31, can implement the relevant steps of the wiring method for reducing power consumption of the clock network according to the foregoing embodiment. In addition, the resources stored in the memory 30 may further include an operating system 302, data 303, and the like, where the storage manner may be transient storage or permanent storage. The operating system 302 may include Windows, unix, linux, among other things. The data 303 may include, but is not limited to, data corresponding to the execution result, and the like.
Processor 31 may include one or more processing cores, such as a 4-core processor, an 8-core processor, or the like. The processor 31 may be implemented in at least one hardware form of DSP (Digital Signal Processing ), FPGA (Field-Programmable Gate Array, field programmable gate array), PLA (Programmable Logic Array ). The processor 31 may also comprise a main processor, which is a processor for processing data in an awake state, also called CPU (Central Processing Unit ); a coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 31 may integrate a GPU (Graphics Processing Unit, image processor) for rendering and drawing of content required to be displayed by the display screen. In some embodiments, the processor 31 may also include an AI (Artificial Intelligence ) processor for processing computing operations related to machine learning.
In some embodiments, the computer device of the present invention may further include a display screen 32, an input-output interface 33, a communication interface 34, a power supply 35, and a communication bus 36. Those skilled in the art will appreciate that the architecture shown in fig. 3 is not limiting of the computer device of the present invention, and may include more or fewer components than illustrated.
In a third aspect of the present invention, a readable storage medium 40 is provided, please refer to fig. 5, comprising: an executable computer program which, when executed by an executor, is adapted to carry out the steps of a wiring method for reducing power consumption of a clock network as in any of the method embodiments described above.
In particular, if a wiring method for reducing power consumption of a clock network in the above-described embodiments is implemented in the form of a software functional unit and sold or used as a separate product, it may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in part or in whole or in part in the form of a software product stored in a storage medium for performing all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random-access Memory (Random Access Memory, RAM), an electrically erasable programmable ROM, registers, a hard disk, a removable disk, a CD-ROM, a magnetic disk, or an optical disk, etc. various media capable of storing program codes.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that as used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The foregoing embodiment of the present invention has been disclosed with reference to the number of embodiments for the purpose of description only, and does not represent the advantages or disadvantages of the embodiments.
Those of ordinary skill in the art will appreciate that: the above discussion of any embodiment is merely exemplary and is not intended to imply that the scope of the disclosure of embodiments of the invention, including the claims, is limited to such examples; combinations of features of the above embodiments or in different embodiments are also possible within the idea of an embodiment of the invention, and many other variations of the different aspects of the embodiments of the invention as described above exist, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. of the embodiments should be included in the protection scope of the embodiments of the present invention.
Claims (10)
1. A wiring method for reducing power consumption of a clock network, the method comprising:
performing clock tree synthesis on the target metal wiring layer;
determining the dynamic power consumption and the violation time sequence path of the target metal wiring layer according to the clock tree synthesis result;
constructing an optimization factor according to the dynamic power consumption and the worst time sequence violation value in the violation time sequence path;
sequentially adjusting the clock line width and the clock line spacing in the target metal wiring layer with the aim of minimizing the optimization factor;
in response to insufficient wiring space when the clock line spacing is adjusted, the corresponding clock lines and the clock lines nearby are subjected to node fusion, and the clock line spacing after the node fusion is adjusted.
2. The wiring method for reducing power consumption of a clock network according to claim 1, wherein said calculating the dynamic power consumption of said target metal wiring layer from said clock tree comprises calculating using the following formula:
P dynamic state ＝P Switch +P Short circuit ＝C load *f*V DD 2 +C eff *f*V DD 2 ；
Wherein C is load Is the load capacitance, f is the clock frequency, V DD Is the power supply voltage, C eff Is the equivalent power consumption capacitance of the device when no load is applied.
3. The routing method for reducing power consumption of a clock network of claim 1, wherein said constructing an optimization factor based on said dynamic power consumption and a worst-case timing violation value in said violation timing path comprises constructing an optimization factor using the following formula:
K＝P dynamic state k1 *|WNS| k2 ；
Wherein K is an optimization factor, P Dynamic state For dynamic power consumption of the target metal wiring layer, |WNS| is the absolute value of the worst time sequence violation value in the violation time sequence path in the target metal wiring layer, and k1 and k2 are regulating coefficients for regulating P respectively Dynamic state And the convergence speed of the |wns| to the K value.
4. A wiring method for reducing power consumption of a clock network according to claim 3, further comprising setting the regulation factor according to a demand,
when the priority of the power consumption of chip design needs to be ensured, configuring the k1 to be larger than the k2;
when the time sequence priority of chip design needs to be ensured, configuring the k1 to be smaller than k2;
wherein the value of k1 is set to 2 by default, and the value of k2 is set to 1.
5. A wiring method for reducing power consumption of a clock network according to claim 3, wherein when a target chip design has a plurality of metal wiring layers, said sequentially adjusting clock line widths and clock line pitches in the target metal wiring layers with the aim of minimizing the optimization factor comprises:
hold M i The clock line spacing of the layers is unchanged, the clock line width is gradually decreased according to a preset step value, and clock tree synthesis is carried out again;
re-calculating the optimal value factor according to the clock tree comprehensive result, repeating the above process until the minimum optimal value is obtainedThe value factor value and the corresponding clock line width is recorded as M i Optimal clock line width W of layer i ；
Will M i The clock line width of the layer is set to W i Gradually increasing the clock line spacing according to a preset step value, and carrying out clock tree synthesis again;
re-calculating a figure-of-merit factor according to the result of the clock tree synthesis, repeating the above processes until the minimum figure-of-merit factor value is obtained, and recording the corresponding clock line spacing as the optimal clock line spacing S of the Mi layer i ；
Wherein the Mi layer is an i-th metal wiring layer.
6. The method of claim 5, further comprising preferentially adjusting the clock lines having the single bit registers when adjusting the clock line spacing.
7. The wiring method for reducing power consumption of a clock network according to claim 1, wherein in response to insufficient wiring space when adjusting the pitch of clock lines, performing node fusion on the corresponding clock lines and clock lines in the vicinity thereof and adjusting the pitch of the clock lines after the node fusion, comprises:
and carrying out node fusion on the single-bit register node on the target clock line and the single-bit register nodes nearby to form the multi-bit register.
8. A wiring method for reducing power consumption of a clock network as described in any one of claims 1-7, wherein said adjusting the clock now pitch in said target metal wiring layer comprises:
the length of the target clock line and the distance between the target clock line and other clock lines are adjusted.
9. A computer device, comprising:
at least one processor; and
a memory having stored therein an executable computer program which when executed by the at least one processor is adapted to implement the steps of a wiring method for reducing power consumption of a clock network as claimed in any one of claims 1-8.
10. A readable storage medium, comprising:
an executable computer program for implementing the steps of a wiring method for reducing power consumption of a clock network as claimed in any one of claims 1-8 when executed by an executor.
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