CN117349904B - Method for realizing software encryption processing based on FPGA - Google Patents
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- 238000013475 authorization Methods 0.000 claims abstract description 16
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- 238000003672 processing method Methods 0.000 claims description 5
- 238000006467 substitution reaction Methods 0.000 claims description 5
- 238000004590 computer program Methods 0.000 claims description 4
- 238000009825 accumulation Methods 0.000 claims description 3
- 230000006870 function Effects 0.000 description 12
- 238000013461 design Methods 0.000 description 8
- 238000005429 filling process Methods 0.000 description 2
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- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
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Abstract
The invention relates to a method for realizing software encryption processing based on an FPGA, wherein the method comprises the following steps: the method comprises the steps of (1) powering up an FPGA to obtain local information; (2) Judging the DNA type of the current FPGA, if the DNA type is a first DNA number, entering the step (3), and if the DNA type is a second DNA number, entering the step (4); (3) Filling the first DNA number according to a first preset rule; (4) Filling the second DNA number according to a second preset rule; (5) Encrypting the data after the filling processing according to the DES encryption principle to obtain a software authorization code; (6) And matching the obtained software authorization code with the local authorization code, if the matching is consistent, the FPGA works normally, otherwise, the FPGA stops working.
Description
Technical Field
The invention relates to the technical field of FPGA (field programmable gate array), in particular to the technical field of FPGA encryption processing, and specifically relates to a method for realizing software encryption processing based on FPGA.
Background
In the process of cooperation of two or more companies required for project development, exchange of engineering source codes among the companies often occurs, but some engineering source codes have soft core part with high commercial value. At present, the code encryption mechanism such as ngc, edif, dcp and other netlist type packages are difficult to achieve the effect of protecting the prokaryotes. Although the internal structure of the soft core cannot be known, the operation usage of the soft core can be known by referring to the logic in the external interface and the source code, and the software can be copied and applied to other products of own companies.
The DNA bit width of the Xilinx FPGA is inconsistent, the DNA bit width is 57bits before 7series and 7series, but 96bits under the Ultrascale architecture. The current DNA encryption authorization function can only aim at one of the DNA encryption authorization functions, cannot be compatible with two bit widths, and has certain limitation.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a method, a device, a processor and a computer readable storage medium for realizing software encryption processing based on an FPGA.
In order to achieve the above object, the method, the device, the processor and the computer readable storage medium thereof for implementing software encryption processing based on FPGA according to the present invention are as follows:
the method for realizing software encryption processing based on the FPGA is mainly characterized by comprising the following steps:
(1) The FPGA is powered on to acquire local information;
(2) Judging the DNA type of the current FPGA, if the DNA type is the first DNA number, entering the step (3), and if the DNA type is the second DNA number, entering the step (4);
(3) Filling the first DNA number according to a first preset rule, and entering a step (5) after finishing;
(4) Filling the second DNA number according to a second preset rule, and entering a step (5) after finishing;
(5) Encrypting the data after the filling processing according to the DES encryption principle to obtain a software authorization code;
(6) And matching the obtained software authorization code with the local authorization code, if the matching is consistent, the FPGA works normally, otherwise, the FPGA stops working.
Preferably, the method further comprises, before step (1):
(0) The following information is provided locally:
xilinx DNA type: 1bit wide 1:57bit 0:96bit;
software authorization code type: 64 bits; and
the FPGA DNA number is provided using a directional encryptor.
Preferably, the step (2) specifically includes:
when the DNA type of the FPGA is the first DNA number, the bit width of the current DNA number is 57 bits;
when the DNA type of the FPGA is the second DNA number, the bit width of the current DNA number is 96bits.
More preferably, when the bit width of the DNA number is 57bits, it is bit width-stuffed: 57bit+57bit=14bit, because the total bit width is less than 128bits, then intercept low order bit width 128 bits-114 bit=14bit and fill again first DNA number, specifically:
so that the bit width of the first DNA number as described in the present is filled with 128 bits.
More preferably, when the bit width of the DNA number is 96bits, it is bit width-stuffed: 96bit+96bit=192 bit, because the total bit width is higher than 128bit, then intercept the 128 bit-96 bit=32 bit of low order bit width and pack again the second DNA number, specifically:
so that the bit width of the presently described second DNA number is filled with 128 bits.
Preferably, the step (5) specifically includes the following steps:
(5.1) grouping the data subjected to the filling processing according to 64 bits to obtain two plaintext groups;
(5.2) encrypting the plaintext block in a bit-wise substitution or exchange manner by using a 64-bit key, wherein the processing rule is as follows:
performing bit-wise exchange according to the sequence to obtain two groups of processed data;
(5.3) carrying out exclusive or processing on the data obtained in the steps and the secret key to obtain two groups of ciphertext;
and (5.4) performing accumulation processing on the two groups of ciphertext to obtain a final group of ciphertext, wherein the ciphertext is the software authorization code, so that the DES encryption processing is completed.
The device for realizing the FPGA-based software encryption processing method is mainly characterized by comprising the following components:
a processor configured to execute computer-executable instructions;
and a memory storing one or more computer executable instructions which, when executed by the processor, implement the steps of the method for implementing software encryption processing based on FPGA described above.
The processor for realizing the FPGA-based software encryption processing method is mainly characterized in that the processor is configured to execute computer executable instructions, and when the computer executable instructions are executed by the processor, the steps of the FPGA-based software encryption processing method are realized.
The computer readable storage medium is mainly characterized in that the computer program is stored thereon, and the computer program can be executed by a processor to realize the steps of the method for realizing the software encryption processing based on the FPGA.
The method, the device, the processor and the computer readable storage medium for realizing the software encryption processing based on the FPGA are adopted, and a layer of DNA encryption authorization function module is packaged in a soft core or dcp module with high commercial value, the function of the module is to detect the FPGA DNA number and compare the FPGA DNA number with the authorized DNA number, and an authorization sign signal is generated after the FPGA DNA number and the authorized DNA number are consistent with each other, so that the logic can utilize the sign signal to realize the situation that the code can only work normally when authorized. Because the DNA number of each FPGA has uniqueness and can not be modified, the outside of the module is not provided with a modified interface after being packaged, and even if a user takes the functional source code, the inner core can not be copied to other FPGAs to operate, so that the function of effectively protecting the intellectual property of the FPGA is achieved.
Drawings
Fig. 1 is a flow chart of a method of the present invention for implementing software encryption processing based on FPGAs.
FIG. 2 is a schematic diagram of a software interface for performing encryption processing in an embodiment of the present invention.
Detailed Description
In order to more clearly describe the technical contents of the present invention, a further description will be made below in connection with specific embodiments.
Before describing in detail embodiments that are in accordance with the present invention, it should be observed that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Before formally starting the software encryption processing for the FPGA, the following information needs to be provided locally:
1) Xilinx DNA type: 1bit wide 1:57bit 0:96bit;
2) Software authorization code: 64bit
The software authorization code is mainly obtained by:
1) The user (company) provides the FPGA DNA number to the encryptor (company);
2) The encryptor generates a software authorization code from the DNA number and provides it to the user.
Referring to fig. 1, the method for implementing software encryption processing based on the FPGA includes the following steps:
(1) The FPGA is powered on to acquire local information;
(2) Judging the DNA type of the current FPGA, if the DNA type is the first DNA number, entering the step (3), and if the DNA type is the second DNA number, entering the step (4);
(3) Filling the first DNA number according to a first preset rule, and entering a step (5) after finishing;
(4) Filling the second DNA number according to a second preset rule, and entering a step (5) after finishing;
(5) Encrypting the data after the filling processing according to the DES encryption principle to obtain a software authorization code;
(6) And matching the obtained software authorization code with the local authorization code, if the matching is consistent, the FPGA works normally, otherwise, the FPGA stops working.
As a preferred embodiment of the present invention, the method further comprises, before step (1):
(0) The following information is provided locally:
xilinx DNA type: 1bit wide 1:57bit 0:96bit;
software authorization code type: 64 bits; and
the FPGA DNA number is provided using a directional encryptor.
As a preferred embodiment of the present invention, the step (2) specifically includes:
when the DNA type of the FPGA is the first DNA number, the bit width of the current DNA number is 57 bits;
when the DNA type of the FPGA is the second DNA number, the bit width of the current DNA number is 96bits.
As a preferred embodiment of the present invention, when the bit width of the DNA number is 57bits, the step (3) is specifically to perform the filling process on the first DNA number in the following manner:
so that the bit width of the first DNA number as described in the present is filled with 128 bits.
As a preferred embodiment of the present invention, when the bit width of the DNA number is 96bits, the step (4) is specifically to perform the filling process on the second DNA number in the following manner:
so that the bit width of the presently described second DNA number is filled with 128 bits.
As a preferred embodiment of the present invention, the step (5) specifically includes the steps of:
(5.1) grouping the data subjected to the filling processing according to 64 bits to obtain a plaintext group;
(5.2) encrypting the plaintext group by adopting a 64bit key in a bit substitution or exchange mode to obtain two groups of ciphertext;
and (5.3) performing accumulation processing on the two groups of ciphertext to obtain a final group of ciphertext, wherein the ciphertext is the software authorization code, so that the DES encryption processing is completed.
Therefore, the technical scheme adopted by the method for realizing the software encryption processing based on the FPGA in the technical scheme is as follows:
1) After the FPGA is electrified, local information is acquired;
2) Reading the DNA number of the FPGA by using the primitives through the DNA type, and filling according to a certain rule, wherein the bit width is 128bits after filling;
3) Performing DES encryption on the filled 128bits to obtain an authorization code;
comparing the authorization code obtained in the step 3) with a local authorization code, if the authorization code is consistent, the FPGA is successfully matched, and the FPGA can work normally, otherwise, the FPGA stops working.
In practical application, the filling rule in the technical scheme is specifically as follows:
the filling rule is based on the principle that the high and low bit of the DNA number are reversed and sequentially supplemented, for example, 4bit data are decimal expressed as 5, binary expressed as 4'b0101, and after the high and low bit reversal filling is carried out according to the filling rule, the decimal becomes 10, and the binary becomes 4' b1010. Because the DNA number has two kinds of 57bit and 96bit, the filling mode has two kinds as follows:
1) And after the order is reversed and the total bit width is not up to 128bits, refilling in a low-bit interception mode. When the DNA is 57bits wide, after the supplement, the bit width is 57+57=114 bits, which is lower than 128bits, and the lower bit width is cut off to 128-114=14 bits for refilling, as shown below;
for example, the DNA code is 57'h002000001557426 and the data after filling is 128' h642d90baaa0000010002000001557426.
2) And after the order is reversed and the total bit width reaches 128bits, refilling in a low-bit interception mode. When the DNA is 96bits wide, after supplementing, the bit width is 96+96=192 bits, and is higher than 128bits, and the lower bit width is cut to 128-96=32 bits for filling, as shown below;
for example, the DNA code is 96'h40020000015574264C2163C5, and the data after filling is 128' h 3C6843240020000015574264C2163C5.
The DES encryption principle is that filled data are grouped according to 64 bits to obtain a plaintext group, the plaintext group is encrypted by adopting a 64bit key in a bit substitution or exchange mode to obtain two groups of ciphertext, and then the two groups of ciphertext are accumulated to finally obtain a group of ciphertext, namely the software authorization code.
The encryption principle adopts simplified DES encryption, and the main steps are as follows:
1) Grouping the filled data according to the high and low 64 bits to obtain two plaintext groups;
2) Processing the two plaintext groups in the step 1) according to a replacement rule to obtain two groups of processed data;
3) Performing exclusive or processing on the data obtained in the step 2) and the secret key to obtain two groups of ciphertext;
4) Accumulating the two groups of ciphertext in the step 3) to obtain a group of ciphertext, namely the software authorization code.
The substitution rule is to follow 64 bits
The order of (2) is bit-wise exchanged, i.e., the 1 st bit of the input 64-bit plaintext is replaced with 40 th bit, the 2 nd bit is replaced with 8 th bit, and the 3 rd bit is replaced with 48 th bit. Similarly, the last bit is the original 7 th bit.
For example, the data after filling is 128' ha3c6843240020000015574264c2163c5, the data can be divided into 64' ha3c6843240020000 and 64' h015574264c2163c5 according to the high-low 64bit group, and the two groups of plain texts are subjected to permutation treatment, and the two groups of plain texts are 64' hd40090e080601048 and 64' h12083601c779606b after permutation. Assuming that the 64bit key is 64' h5AA5_A5A5_A5A_AA55, the two sets of permuted data are exclusive-or processed with the key to obtain two sets of ciphertext, namely 64' h8ea 535da3aba1d and 64' h 48ade93a49d 233e. And finally, accumulating the two groups of ciphertext to obtain a final ciphertext, namely an authorization code, which is 64' hd752c8ea775e 84fb.
In one embodiment of the present invention, the encryption process is implemented as follows:
the user needs to provide the encryption party with FPGA DNA numbers, and the encryption party finally provides the user with the following files:
5) A dcp file;
6) The Black box port declares the file;
7) An authorization code.
After the user receives the data, two situations generally exist, namely, the function of the encryption party is added into self engineering design, the user does not have self engineering design, only the function provided by the encryption party is used, and the two situations are specifically realized as follows:
1) If the second condition is the second condition, a new project is required to be established, and a top-level file is generated according to the black box port declaration file. In the first case, starting from 2);
2) According to the black box port declaration file, carrying out modular instantiation in engineering design;
3) Importing a black box file and a dcp file into engineering design;
4) Integrating engineering design and laying out and wiring;
5) Generating bit and BSP files for subsequent debugging and use;
6) In the debugging process, when the FPGA DNA number is consistent with that provided by a user to an encryption party, the FPGA works normally, otherwise, the FPGA stops working, and the property of FPGA software is effectively protected.
There are currently two methods for importing black box files and dcp files into engineering designs: one is directly by adding the v file, i.e., the black box file and the dcp file are added to the engineering design by passing the add sources; one is to prepare a tcl file in which the reading position of the dcp file is formulated, import the black box file and tcl file into the engineering design by adding v file, and then associate the imported tcl file in tcl. Pre in opt_Deing in Implement Setting, as shown by the marked box in FIG. 2.
The device for realizing the FPGA-based software encryption processing method comprises the following steps:
a processor configured to execute computer-executable instructions;
and a memory storing one or more computer executable instructions which, when executed by the processor, implement the steps of the method for implementing software encryption processing based on FPGA described above.
The processor is configured to execute computer executable instructions, and when the computer executable instructions are executed by the processor, the steps of the method for implementing software encryption processing based on the FPGA are implemented.
The computer readable storage medium having stored thereon a computer program executable by a processor to perform the steps of the method for implementing a software encryption process based on FPGA described above.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and further implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.
It is to be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution device.
Those of ordinary skill in the art will appreciate that all or a portion of the steps carried out in the method of the above-described embodiments may be implemented by a program to instruct related hardware, and the program may be stored in a computer readable storage medium, where the program when executed includes one or a combination of the steps of the method embodiments.
The above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, or the like.
In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "examples," "specific examples," or "embodiments," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
The method, the device, the processor and the computer readable storage medium for realizing the software encryption processing based on the FPGA are adopted, and a layer of DNA encryption authorization function module is packaged in a soft core or dcp module with high commercial value, the function of the module is to detect the FPGA DNA number and compare the FPGA DNA number with the authorized DNA number, and an authorization sign signal is generated after the FPGA DNA number and the authorized DNA number are consistent with each other, so that the logic can utilize the sign signal to realize the situation that the code can only work normally when authorized. Because the DNA number of each FPGA has uniqueness and can not be modified, the outside of the module is not provided with a modified interface after being packaged, and even if a user takes the functional source code, the inner core can not be copied to other FPGAs to operate, so that the function of effectively protecting the intellectual property of the FPGA is achieved.
In this specification, the invention has been described with reference to specific embodiments thereof. It will be apparent, however, that various modifications and changes may be made without departing from the spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims (6)
1. The method for realizing the software encryption processing based on the FPGA is characterized by comprising the following steps:
(1) The FPGA is powered on to acquire local information;
(2) Judging the DNA type of the current FPGA, if the DNA type is the first DNA number, entering the step (3), and if the DNA type is the second DNA number, entering the step (4);
(3) Filling the first DNA number according to a first preset rule, and entering a step (5) after finishing;
(4) Filling the second DNA number according to a second preset rule, and entering a step (5) after finishing;
(5) Encrypting the data after the filling processing according to the DES encryption principle to obtain a software authorization code;
(6) Matching the obtained software authorization code with a local authorization code, if the matching is consistent, the FPGA works normally, otherwise, the FPGA stops working;
the step (2) is specifically as follows:
when the DNA type of the FPGA is the first DNA number, the bit width of the current DNA number is 57 bits;
when the DNA type of the FPGA is the second DNA number, the bit width of the current DNA number is 96 bits;
when the bit width of the DNA number is 57bits, filling the bit width: 57bit+57bit=14bit, because the total bit width is less than 128bits, then intercept low order bit width 128 bits-114 bit=14bit and fill again first DNA number, specifically:
；
thereby making the bit width of the first DNA number to be filled with 128bits;
when the bit width of the DNA number is 96bits, filling the bit width: 96bit+96bit=192 bit, because the total bit width is higher than 128bit, then intercept the 128 bit-96 bit=32 bit of low order bit width and pack again the second DNA number, specifically:
；
so that the bit width of the presently described second DNA number is filled with 128 bits.
2. The method for implementing software encryption processing based on FPGA of claim 1, further comprising, before step (1):
(0) The following information is provided locally:
xilinx DNA type: 1bit wide 1:57bit 0:96bit;
software authorization code type: 64 bits; and
the FPGA DNA number is provided using a directional encryptor.
3. The method for implementing software encryption processing based on FPGA of claim 1, wherein said step (5) specifically comprises the steps of:
(5.1) grouping the data subjected to the filling processing according to 64 bits to obtain two plaintext groups;
(5.2) encrypting the plaintext block in a bit-wise substitution or exchange manner by using a 64-bit key, wherein the processing rule is as follows:
；
performing bit-wise exchange according to the sequence to obtain two groups of processed data;
(5.3) carrying out exclusive or processing on the data obtained in the steps and the secret key to obtain two groups of ciphertext;
and (5.4) performing accumulation processing on the two groups of ciphertext to obtain a final group of ciphertext, wherein the ciphertext is the software authorization code, so that the DES encryption processing is completed.
4. An apparatus for implementing an FPGA-based software encryption processing method, wherein the apparatus includes:
a processor configured to execute computer-executable instructions;
a memory storing one or more computer-executable instructions which, when executed by the processor, perform the steps of the method of implementing software encryption processing based on FPGA of any one of claims 1 to 3.
5. A processor for implementing a method of FPGA-based software encryption processing, wherein the processor is configured to execute computer-executable instructions that, when executed by the processor, implement the steps of the method of FPGA-based software encryption processing of any one of claims 1 to 3.
6. A computer-readable storage medium, having stored thereon a computer program executable by a processor to perform the steps of the method of implementing a software encryption process based on an FPGA of any one of claims 1 to 3.
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