CN117349103A - System for verifying PCIE controller of SOC chip based on FPGA - Google Patents

Abstract

The invention discloses a system for verifying a PCIE controller of an SOC chip based on an FPGA, which comprises the PCIE controller of the SOC chip to be verified, a DFI-AXI bridge, the FPGA PCIE controller, FPGA PCIE PHY and PCIE equipment, wherein: the DFI-AXI bridge is connected with the PCIE controller of the SOC chip through a DFI interface and connected with the PCIE controller of the FPGA through an AXI interface, and is used for executing protocol conversion between the DFI and the AXI so as to interact between the PCIE controller of the SOC chip and the PCIE controller of the FPGA; the FPGA PCIE controller is connected with FPGA PCIE PHY through an FPGA internal bus and FPGA PCIE PHY is connected with PCIE equipment. The invention solves the problem that the prior FPGA hardware prototype verification platform cannot verify the PCIE controller of the SOC chip, realizes the verification of the PCIE controller of the SOC chip on the FPGA hardware prototype verification platform, improves the verification speed of the PCIE controller of the SOC chip, can verify more test programs and realize full verification, and therefore, also improves the success rate of chip streaming.

Description

System for verifying PCIE controller of SOC chip based on FPGA

Technical Field

The invention relates to a PCIE controller, in particular to a system for verifying a PCIE controller of an SOC chip based on an FPGA.

Background

With the widespread use of cloud computing and high-performance computing, in order to efficiently process a large amount of data, more and more system-on-chip (SOC) chips are integrated with PCIE controllers to improve internal communication capabilities. Fig. 1 shows an example of an SOC chip integrated with a PCIE controller, which is also referred to as an SOC chip PCIE controller, and the SOC chip PCIE controller is connected to a PCIE device outside the SOC chip through a SOC chip PCIE physical layer (PCIE PHY) and is used to control access to the device, including controlling a read-write request signal, an address signal, a data signal, a command signal, and the like. The verification SOC chip PCIE controller is a key link in the whole SOC chip verification process, and a platform for verifying the SOC chip at present mainly comprises an RTL software simulation verification platform and an FPGA hardware prototype verification platform, and SOC chip verification can be performed based on any one of the two platforms.

The scheme based on the RTL software simulation verification platform is that a PCIE equipment model is integrated into a verification environment, test excitation is written and provided for an SOC processor, and the SOC processor sends excitation to PCIE and receives response through a bus, so that verification of functions of an SOC chip is realized. According to the scheme, all signal waveforms in the SOC chip can be observed, so that the design problem of hardware can be found as soon as possible, however, because the logic of the PCIE controller of the SOC chip is larger and the test items are more, the simulation speed on the RTL software simulation verification platform is slower and quick iteration cannot be performed, and the research and development period of the SOC chip is prolonged. The scheme based on the FPGA hardware prototype verification platform uses the FPGA to splice out an effective flow so as to verify the function of the SOC chip. Because the PCIE PHY in the SOC chip is an actual circuit fixed in the SOC chip, it cannot be synthesized any more, and there may be a large difference between the FPGA PCIE PHY and SOC chip PCIE PHYs, which results in the FPGA PCIE PHY being incompatible with the SOC chip PCIE controller, so the current FPGA hardware prototype verification platform usually uses FPGA PCIE controllers and FPGA PCIE PHY to replace the SOC chip PCIE controller and SOC chip PCIE PHY respectively, so as to perform verification on the SOC chip. Obviously, the current FPGA hardware prototype verification platform cannot verify the PCIE controller of the SOC chip. On the one hand, the PCIE controller of the SOC chip is different from the PCIE controller of the FPGA, the verification result of the FPGA hardware prototype verification platform may be seriously error caused by replacing the PCIE controller and the PCIE PHY to verify the SOC chip, and PCIE versions supported by some of the FPGA hardware prototype verification platforms may not be compatible with the PCIE controller of the SOC chip and cannot be used for verification of the SOC chip; on the other hand, the FPGA hardware prototype verification platform cannot verify the PCIE controller of the SOC chip, so that the risk of chip flow failure is increased.

Disclosure of Invention

The invention aims at: in order to overcome the defects in the prior art, the invention provides a system for verifying a PCIE controller of an SOC chip based on an FPGA.

The technical scheme of the invention is as follows:

the system for verifying the PCIE controller of the SOC chip based on the FPGA comprises the PCIE controller of the SOC chip to be verified, a DFI-AXI bridge, the PCIE controller of the FPGA, FPGA PCIE PHY and PCIE equipment, wherein:

the DFI-AXI bridge is connected with the PCIE controller of the SOC chip through a DFI interface and connected with the PCIE controller of the FPGA through an AXI interface,

the DFI-AXI bridge is used for executing protocol conversion between the DFI and the AXI so as to interact between the PCIE controller of the SOC chip and the PCIE controller of the FPGA;

the FPGA PCIE controller is connected with FPGA PCIE PHY through an FPGA internal bus and FPGA PCIE PHY is connected with PCIE equipment.

Preferably, the DFI-AXI bridge includes a transmit transaction module and a receive transaction module;

the sending transaction processing module decodes a write command, a write address and write data from the PCIE controller of the SOC chip, performs protocol conversion from DFI to AXI on the write address and the write data according to the write command, and sends the write address and the write data after the protocol conversion to the FPGA PCIE controller;

and the receiving transaction processing module decodes the read command and the read address from the PCIE controller of the SOC chip, performs protocol conversion from DFI to AXI on the read address according to the read command, and sends the read address after the protocol conversion to the FPGA PCIE controller.

Preferably, the sending transaction processing module further decodes a write response from the FPGA PCIE controller, performs AXI to DFI protocol conversion on the write response, and sends the write response after the protocol conversion to the SOC chip PCIE controller; the receiving transaction processing module also decodes the read data from the FPGA PCIE controller, performs the protocol conversion from AXI to DFI on the read data, and sends the read data after the protocol conversion to the SOC chip PCIE controller.

Preferably, the sending transaction processing module comprises a writing operation control unit and a writing sending unit;

the write operation control unit decodes a write command, a write address and write data from the PCIE controller of the SOC chip, and writes the write command, the write address and the write data into a write command queue, a write address queue and a write data queue respectively;

the write transmitting unit obtains a write command from the write command queue, obtains a write address and write data from the write address queue and the write data queue respectively according to the write command, performs protocol conversion from DFI to AXI on the write address and the write data, and transmits the write address and the write data after the protocol conversion to the FPGA PCIE controller; the write command queue, the write address queue and the write data queue respectively realize the operation of crossing clock domains.

Preferably, the write sending unit further decodes a write response from the FPGA PCIE controller, performs AXI to DFI protocol conversion on the write response, and writes the protocol-converted write response into a write response queue; the write operation control unit also obtains a write response from the write response queue and sends the write response to the PCIE controller of the SOC chip; the write response queue realizes the operation of crossing clock domains;

the write operation control unit also performs control as follows:

for the write transmitting unit in the write idle state, when any one of the write command queue, the write address queue and the write data queue is not empty, the write operation control unit controls the write transmitting unit to enter a write enabling state;

for a write transmitting unit in a write enabling state, searching corresponding write addresses and write data in a write address queue and a write data queue according to a write command in the write command queue, if so, controlling the write transmitting unit to enter a write transmitting state, executing protocol conversion from DFI to AXI on the write addresses and the write data by the write transmitting unit in the write transmitting state, transmitting the protocol-converted write addresses and the write data to an FPGA PCIE controller, and if not, controlling the write transmitting unit to enter a write waiting state, and waiting until the corresponding write addresses and the write data in the write address queue and the write data queue are found, and then controlling the write transmitting unit to enter the write transmitting state;

for the write transmitting unit in the write transmitting state, when the write command queue, the write address queue, and the write data queue are all empty, the write operation control unit controls the write transmitting unit to enter a write idle state.

Preferably, the receiving transaction processing module comprises a read operation control unit and a read receiving unit;

the read operation control unit decodes a read command and a read address from the PCIE controller of the SOC chip, and writes the read command and the read address into a read command queue and a read address queue respectively;

the read receiving unit obtains a read command from the read command queue, obtains a read address from the read address queue according to the read command, performs protocol conversion from DFI to AXI on the read address, and sends the read address after protocol conversion to the FPGA PCIE controller; the read command queue and the read address queue respectively realize the operation of crossing clock domains.

Preferably, the read receiving unit further decodes the read data from the FPGA PCIE controller, performs AXI to DFI protocol conversion on the read data, and writes the read data after the protocol conversion into a read data queue; the read operation control unit also obtains read data from the read data queue and sends the read data to the PCIE controller of the SOC chip; the read data queue realizes the operation of crossing clock domains;

the read operation control unit further performs control as follows:

for the read receiving unit in the read idle state, when the read command queue or the read address queue is not empty, the read operation control unit controls the read receiving unit to enter a read enabling state;

for a read receiving unit in a read enabling state, searching a corresponding read address in a read address queue according to a read command in the read command queue, if the corresponding read address is found, controlling the read receiving unit to enter the read receiving state, executing protocol conversion from DFI to AXI on the read address by the read receiving unit in the read receiving state, sending the read address after the protocol conversion to an FPGA PCIE controller, if the corresponding read address is not found, controlling the read receiving unit to enter a read waiting state, and waiting until the corresponding read address is found in the read address queue, and controlling the read receiving unit to enter the read receiving state;

for the read receiving unit in the read receiving state, when the read command queue and the read address queue are empty, the read operation control unit controls the read receiving unit to enter a read idle state. The queues in the above system may employ asynchronous cross-clock domain FIFO queues.

The invention has the advantages that:

1. the invention provides a system for verifying an SOC (system on chip) PCIE (peripheral component interface express) controller based on an FPGA (field programmable gate array), which solves the problem that the traditional FPGA hardware prototype verification platform cannot verify the SOC PCIE controller and realizes verification of the SOC PCIE controller on the FPGA hardware prototype verification platform.

2. Compared with the verification scheme based on the RTL software simulation verification platform, the verification speed of the PCIE controller of the SOC chip is improved, and as the verification speed is higher, more test programs can be verified and full verification is realized, the success rate of chip streaming is improved.

3. The invention realizes protocol conversion between the PCIE controller of the SOC chip and the PCIE controller of the FPGA by designing the DFI-AXI bridge, so that verification of the PCIE controller of the SOC chip is independent of the specific model of the FPGA and the version of the PCIE, and the compatibility is good.

Drawings

The invention is further described below with reference to the accompanying drawings and examples:

fig. 1 is a block diagram of a system for verifying a PCIE controller of a SOC chip based on an FPGA of the present invention.

Description of the embodiments

As shown in fig. 1, the system for verifying a PCIE controller of an SOC chip based on an FPGA of the present invention includes a PCIE controller of an SOC chip to be verified, a DFI-AXI bridge, an FPGA PCIE controller, FPGA PCIE PHY, and PCIE devices, where:

the DFI-AXI bridge is connected with the PCIE controller of the SOC chip through a DFI interface and connected with the PCIE controller of the FPGA through an AXI interface,

the DFI-AXI bridge is used for executing protocol conversion between the DFI and the AXI so as to interact between the PCIE controller of the SOC chip and the PCIE controller of the FPGA;

the FPGA PCIE controller is connected with FPGA PCIE PHY through an FPGA internal bus and FPGA PCIE PHY is connected with PCIE equipment.

The DFI-AXI bridge comprises a sending transaction processing module and a receiving transaction processing module;

the sending transaction processing module decodes a write command, a write address and write data from the PCIE controller of the SOC chip, performs protocol conversion from DFI to AXI on the write address and the write data according to the write command, and sends the write address and the write data after the protocol conversion to the FPGA PCIE controller;

and the receiving transaction processing module decodes the read command and the read address from the PCIE controller of the SOC chip, performs protocol conversion from DFI to AXI on the read address according to the read command, and sends the read address after the protocol conversion to the FPGA PCIE controller.

The sending transaction processing module also decodes the write response from the FPGA PCIE controller, performs the protocol conversion from AXI to DFI on the write response, and sends the write response after the protocol conversion to the SOC chip PCIE controller; the receiving transaction processing module also decodes the read data from the FPGA PCIE controller, performs the protocol conversion from AXI to DFI on the read data, and sends the read data after the protocol conversion to the SOC chip PCIE controller.

The sending transaction processing module comprises a writing operation control unit and a writing sending unit;

the write operation control unit decodes a write command, a write address and write data from the PCIE controller of the SOC chip, and writes the write command, the write address and the write data into a write command queue, a write address queue and a write data queue respectively;

the write transmitting unit obtains a write command from the write command queue, obtains a write address and write data from the write address queue and the write data queue respectively according to the write command, performs protocol conversion from DFI to AXI on the write address and the write data, and transmits the write address and the write data after the protocol conversion to the FPGA PCIE controller; the write command queue, the write address queue and the write data queue respectively realize the operation of crossing clock domains.

The write transmitting unit also decodes the write response from the FPGA PCIE controller, performs the protocol conversion from AXI to DFI on the write response, and writes the write response after the protocol conversion into a write response queue; the write operation control unit also obtains a write response from the write response queue and sends the write response to the PCIE controller of the SOC chip; the write response queue realizes the operation of crossing clock domains;

the write operation control unit also performs control as follows:

for the write transmitting unit in the write idle state, when any one of the write command queue, the write address queue and the write data queue is not empty, the write operation control unit controls the write transmitting unit to enter a write enabling state;

for a write transmitting unit in a write enabling state, searching corresponding write addresses and write data in a write address queue and a write data queue according to a write command in the write command queue, if so, controlling the write transmitting unit to enter a write transmitting state, executing protocol conversion from DFI to AXI on the write addresses and the write data by the write transmitting unit in the write transmitting state, transmitting the protocol-converted write addresses and the write data to an FPGA PCIE controller, and if not, controlling the write transmitting unit to enter a write waiting state, and waiting until the corresponding write addresses and the write data in the write address queue and the write data queue are found, and then controlling the write transmitting unit to enter the write transmitting state;

for the write transmitting unit in the write transmitting state, when the write command queue, the write address queue, and the write data queue are all empty, the write operation control unit controls the write transmitting unit to enter a write idle state.

The receiving transaction processing module comprises a reading operation control unit and a reading receiving unit;

the read operation control unit decodes a read command and a read address from the PCIE controller of the SOC chip, and writes the read command and the read address into a read command queue and a read address queue respectively;

the read receiving unit obtains a read command from the read command queue, obtains a read address from the read address queue according to the read command, performs protocol conversion from DFI to AXI on the read address, and sends the read address after protocol conversion to the FPGA PCIE controller; the read command queue and the read address queue respectively realize the operation of crossing clock domains.

The read receiving unit also decodes the read data from the FPGA PCIE controller, performs the protocol conversion from AXI to DFI on the read data, and writes the read data after the protocol conversion into a read data queue; the read operation control unit also obtains read data from the read data queue and sends the read data to the PCIE controller of the SOC chip; the read data queue realizes the operation of crossing clock domains;

the read operation control unit further performs control as follows:

for the read receiving unit in the read idle state, when the read command queue or the read address queue is not empty, the read operation control unit controls the read receiving unit to enter a read enabling state;

for a read receiving unit in a read enabling state, searching a corresponding read address in a read address queue according to a read command in the read command queue, if the corresponding read address is found, controlling the read receiving unit to enter the read receiving state, executing protocol conversion from DFI to AXI on the read address by the read receiving unit in the read receiving state, sending the read address after the protocol conversion to an FPGA PCIE controller, if the corresponding read address is not found, controlling the read receiving unit to enter a read waiting state, and waiting until the corresponding read address is found in the read address queue, and controlling the read receiving unit to enter the read receiving state;

for the read receiving unit in the read receiving state, when the read command queue and the read address queue are empty, the read operation control unit controls the read receiving unit to enter a read idle state. The queues in the above system may employ asynchronous cross-clock domain FIFO queues.

The invention provides a system for verifying an SOC (system on chip) PCIE (peripheral component interface express) controller based on an FPGA (field programmable gate array), which solves the problem that the traditional FPGA hardware prototype verification platform cannot verify the SOC PCIE controller and realizes verification of the SOC PCIE controller on the FPGA hardware prototype verification platform. Compared with the verification scheme based on the RTL software simulation verification platform, the verification speed of the PCIE controller of the SOC chip is improved, and as the verification speed is higher, more test programs can be verified and full verification is realized, the success rate of chip streaming is improved. The invention realizes protocol conversion between the PCIE controller of the SOC chip and the PCIE controller of the FPGA by designing the DFI-AXI bridge, so that verification of the PCIE controller of the SOC chip is independent of the specific model of the FPGA and the version of the PCIE, and the compatibility is good.

The above embodiments are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement the same according to the content of the present invention, and are not intended to limit the scope of the present invention. All modifications made according to the spirit of the main technical proposal of the invention should be covered in the protection scope of the invention.

Claims (7)

1. The system for verifying the PCIE controller of the SOC chip based on the FPGA is characterized by comprising the PCIE controller of the SOC chip to be verified, a DFI-AXI bridge, the FPGA PCIE controller, FPGA PCIE PHY and PCIE equipment, wherein:

the DFI-AXI bridge is connected with the PCIE controller of the SOC chip through a DFI interface and connected with the PCIE controller of the FPGA through an AXI interface,

the DFI-AXI bridge is used for executing protocol conversion between the DFI and the AXI so as to interact between the PCIE controller of the SOC chip and the PCIE controller of the FPGA;

the FPGA PCIE controller is connected with FPGA PCIE PHY through an FPGA internal bus and FPGA PCIE PHY is connected with PCIE equipment.

2. The system for verifying a PCIE controller of a SOC chip based on an FPGA of claim 1, wherein the DFI-AXI bridge includes a transmit transaction module and a receive transaction module;

the sending transaction processing module decodes a write command, a write address and write data from the PCIE controller of the SOC chip, performs protocol conversion from DFI to AXI on the write address and the write data according to the write command, and sends the write address and the write data after the protocol conversion to the FPGA PCIE controller;

and the receiving transaction processing module decodes the read command and the read address from the PCIE controller of the SOC chip, performs protocol conversion from DFI to AXI on the read address according to the read command, and sends the read address after the protocol conversion to the FPGA PCIE controller.

3. The system for verifying the PCIE controller of the SOC chip based on the FPGA of claim 2, wherein the send transaction module further decodes a write response from the FPGA PCIE controller, performs AXI to DFI protocol conversion on the write response, and sends the protocol converted write response to the SOC chip PCIE controller; the receiving transaction processing module also decodes the read data from the FPGA PCIE controller, performs the protocol conversion from AXI to DFI on the read data, and sends the read data after the protocol conversion to the SOC chip PCIE controller.

4. The system for verifying a PCIE controller of a SOC chip based on an FPGA of claim 3, wherein the send transaction module includes a write operation control unit and a write send unit;

the write operation control unit decodes a write command, a write address and write data from the PCIE controller of the SOC chip, and writes the write command, the write address and the write data into a write command queue, a write address queue and a write data queue respectively;

the write transmitting unit obtains a write command from the write command queue, obtains a write address and write data from the write address queue and the write data queue respectively according to the write command, performs protocol conversion from DFI to AXI on the write address and the write data, and transmits the write address and the write data after the protocol conversion to the FPGA PCIE controller; the write command queue, the write address queue and the write data queue respectively realize the operation of crossing clock domains.

5. The system for verifying a PCIE controller of a SOC chip based on an FPGA of claim 4, wherein the write-transmit unit further decodes a write response from the FPGA PCIE controller, performs AXI to DFI protocol conversion on the write response, and writes the protocol-converted write response to a write-response queue; the write operation control unit also obtains a write response from the write response queue and sends the write response to the PCIE controller of the SOC chip; the write response queue realizes the operation of crossing clock domains;

the write operation control unit also performs control as follows:

for the write transmitting unit in the write idle state, when any one of the write command queue, the write address queue and the write data queue is not empty, the write operation control unit controls the write transmitting unit to enter a write enabling state;

for a write transmitting unit in a write enabling state, searching corresponding write addresses and write data in a write address queue and a write data queue according to a write command in the write command queue, if so, controlling the write transmitting unit to enter a write transmitting state, executing protocol conversion from DFI to AXI on the write addresses and the write data by the write transmitting unit in the write transmitting state, transmitting the protocol-converted write addresses and the write data to an FPGA PCIE controller, and if not, controlling the write transmitting unit to enter a write waiting state, and waiting until the corresponding write addresses and the write data in the write address queue and the write data queue are found, and then controlling the write transmitting unit to enter the write transmitting state;

for the write transmitting unit in the write transmitting state, when the write command queue, the write address queue, and the write data queue are all empty, the write operation control unit controls the write transmitting unit to enter a write idle state.

6. The system for verifying the PCIE controller of the SOC chip based on the FPGA of claim 5, wherein the receive transaction module comprises a read operation control unit and a read receiving unit;

the read operation control unit decodes a read command and a read address from the PCIE controller of the SOC chip, and writes the read command and the read address into a read command queue and a read address queue respectively;

the read receiving unit obtains a read command from the read command queue, obtains a read address from the read address queue according to the read command, performs protocol conversion from DFI to AXI on the read address, and sends the read address after protocol conversion to the FPGA PCIE controller; the read command queue and the read address queue respectively realize the operation of crossing clock domains.

7. The system for verifying the PCIE controller of the SOC chip based on the FPGA of claim 6, wherein the read receiving unit further decodes read data from the FPGA PCIE controller, performs AXI to DFI protocol conversion on the read data, and writes the protocol-converted read data to the read data queue; the read operation control unit also obtains read data from the read data queue and sends the read data to the PCIE controller of the SOC chip; the read data queue realizes the operation of crossing clock domains;

the read operation control unit further performs control as follows:

for the read receiving unit in the read idle state, when the read command queue or the read address queue is not empty, the read operation control unit controls the read receiving unit to enter a read enabling state;

for a read receiving unit in a read enabling state, searching a corresponding read address in a read address queue according to a read command in the read command queue, if the corresponding read address is found, controlling the read receiving unit to enter the read receiving state, executing protocol conversion from DFI to AXI on the read address by the read receiving unit in the read receiving state, sending the read address after the protocol conversion to an FPGA PCIE controller, if the corresponding read address is not found, controlling the read receiving unit to enter a read waiting state, and waiting until the corresponding read address is found in the read address queue, and controlling the read receiving unit to enter the read receiving state;

for the read receiving unit in the read receiving state, when the read command queue and the read address queue are empty, the read operation control unit controls the read receiving unit to enter a read idle state. The queues in the above system may employ asynchronous cross-clock domain FIFO queues.