CN117348655A - Bandgap circuit with adaptive startup design - Google Patents
Bandgap circuit with adaptive startup design Download PDFInfo
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Abstract
本发明公开一种具有自适应启动设计的带隙电路包括:带隙核心,使用成对的双极晶体管来消除温度敏感因子,从而产生与温度变化无关的带隙电压;以及启动电路,将该成对双极晶体管中的第一双极晶体管的发射极端子耦接到电源线以启动该带隙核心,其中,该启动电路包括参考双极晶体管,该参考双极晶体管提供阈值电压作为用于将该电源线与该第一双极晶体管的发射极端子断开的参考。本发明的上述方式可以使带隙电路具有的操作时间窗口更加宽裕,使所需要的带隙电压更加稳定的产生,并且更加容易控制。
The invention discloses a bandgap circuit with an adaptive start-up design, which includes: a bandgap core, which uses a pair of bipolar transistors to eliminate temperature-sensitive factors, thereby generating a bandgap voltage that is independent of temperature changes; and a start-up circuit, which An emitter terminal of a first bipolar transistor in a pair of bipolar transistors is coupled to the power line to activate the bandgap core, wherein the activation circuit includes a reference bipolar transistor that provides a threshold voltage as a A reference for disconnecting the power line from the emitter terminal of the first bipolar transistor. The above-described method of the present invention can make the operation time window of the bandgap circuit more generous, generate the required bandgap voltage more stably, and make it easier to control.
Description
技术领域Technical field
本发明涉及电路技术领域,尤其涉及一种具有自适应启动设计的带隙电路。The present invention relates to the field of circuit technology, and in particular, to a bandgap circuit with adaptive startup design.
背景技术Background technique
在集成电路(integrated circuit)中,需要带隙电压(bandgap voltage)参考(reference),其是与温度无关的(temperature independent)电压参考(voltagereference)。无论电源变化、温度变化或设备的电路负载如何,带隙电路都会产生恒定电压。In integrated circuits, a bandgap voltage reference is needed, which is a temperature independent voltage reference. Bandgap circuits produce a constant voltage regardless of changes in power supply, temperature changes, or circuit loading of the device.
带隙核的启动(start-up)是本领域的一个重要课题。The start-up of bandgap cores is an important issue in this field.
发明内容Contents of the invention
有鉴于此,本发明提供一种具有自适应启动设计的带隙电路,以解决上述问题。In view of this, the present invention provides a bandgap circuit with an adaptive startup design to solve the above problems.
根据本发明的第一方面,公开一种具有自适应启动设计的带隙电路,包括:According to a first aspect of the present invention, a bandgap circuit with adaptive startup design is disclosed, including:
带隙核心,使用成对的双极晶体管来消除温度敏感因子,从而产生与温度变化无关的带隙电压;以及a bandgap core, which uses pairs of bipolar transistors to eliminate temperature sensitivity factors, resulting in a bandgap voltage that is independent of temperature changes; and
启动电路,将该成对双极晶体管中的第一双极晶体管的发射极端子耦接到电源线以启动该带隙核心,activating a circuit that couples an emitter terminal of a first bipolar transistor of the pair of bipolar transistors to a power line to activate the bandgap core,
其中,该启动电路包括参考双极晶体管,该参考双极晶体管提供阈值电压作为用于将该电源线与该第一双极晶体管的发射极端子断开的参考。Wherein, the startup circuit includes a reference bipolar transistor that provides a threshold voltage as a reference for disconnecting the power line from the emitter terminal of the first bipolar transistor.
进一步的,该参考双极晶体管为二极管连接形式,与该第一双极晶体管相同。以顺利的产生阈值电压提供给比较器,用于更加准确地确定第一双极晶体管的发射极端子与电源线断开或连接。Further, the reference bipolar transistor is in a diode connection form, which is the same as the first bipolar transistor. The smoothly generated threshold voltage is provided to the comparator for more accurately determining whether the emitter terminal of the first bipolar transistor is disconnected or connected to the power line.
进一步的,该启动电路还包括:比较器,具有接收与从该带隙核心感测到的感测电流相关的感测电压的正输入端子、耦接到该参考双极晶体管的发射极端子的负输入端子、以及输出控制信号以将该第一双极晶体管的发射极端子连接至该电源线或将该第一双极晶体管的发射极端子与该电源线断开的输出端子。比较器地使用可以使确定第一双极晶体管的发射极端子与电源线断开或连接更加符合设计需求。Further, the startup circuit further includes: a comparator having a positive input terminal receiving a sensing voltage related to the sensing current sensed from the bandgap core, and an emitter terminal coupled to the reference bipolar transistor. a negative input terminal, and an output terminal that outputs a control signal to connect the emitter terminal of the first bipolar transistor to the power line or to disconnect the emitter terminal of the first bipolar transistor from the power line. The use of a comparator can make it more consistent with design requirements to determine whether the emitter terminal of the first bipolar transistor is disconnected or connected to the power line.
进一步的,该启动电路还包括:启动控制MOS晶体管,具有耦接至该比较器的输出端子的栅极端子、耦接至该电源线的源极端子、以及耦接至该第一双极晶体管的发射极端子的漏极端子。这样可以利用比较器的输出控制启动控制MOS晶体管,从而确定第一双极晶体管的发射极端子与电源线断开或连接。Further, the startup circuit further includes: a startup control MOS transistor having a gate terminal coupled to the output terminal of the comparator, a source terminal coupled to the power line, and a first bipolar transistor. the emitter terminal and the drain terminal. In this way, the output of the comparator can be used to control the activation of the MOS transistor, thereby determining that the emitter terminal of the first bipolar transistor is disconnected or connected to the power line.
进一步的,该启动电路还包括:第一电阻器,将该参考双极晶体管的发射极端子耦接至该电源线,Further, the startup circuit also includes: a first resistor coupling the emitter terminal of the reference bipolar transistor to the power line,
其中该第一电阻与该参考双极晶体管之间的连接端子耦接该比较器的负输入端子。从而产生阈值电压。The connection terminal between the first resistor and the reference bipolar transistor is coupled to the negative input terminal of the comparator. This creates a threshold voltage.
进一步的,该启动电路还包括:第二电阻器,耦接于该比较器的正输入端子与地之间,该感测电流流过该第二电阻器。以产生感测电压。Further, the startup circuit further includes: a second resistor coupled between the positive input terminal of the comparator and ground, and the sensing current flows through the second resistor. to generate sensing voltage.
进一步的,该启动电路还包括:电流镜MOS,镜像该带隙核心的电流以产生流过该第二电阻的该感测电流。从而顺利产生感测电压。Further, the startup circuit further includes: a current mirror MOS that mirrors the current of the bandgap core to generate the sensing current flowing through the second resistor. Thereby the sensing voltage is generated smoothly.
进一步的,该启动电路还包括:第一使能MOS,耦接于该电源线与该第一电阻之间,并受该启动电路的使能信号控制;以及Further, the startup circuit also includes: a first enable MOS, coupled between the power line and the first resistor, and controlled by the enable signal of the startup circuit; and
第二使能MOS,耦接于该电源线与该启动控制MOS晶体管的源极端子之间,并受该启动电路的使能信号控制。从而控制产生阈值电压和感测电压。The second enabling MOS is coupled between the power line and the source terminal of the startup control MOS transistor, and is controlled by the enable signal of the startup circuit. Thereby controlling the generation of threshold voltage and sensing voltage.
进一步的,该带隙核心还包括:第二双极晶体管,呈二极管连接形式,并与该第一双极晶体管配对;以及Further, the band gap core also includes: a second bipolar transistor in the form of a diode connection and paired with the first bipolar transistor; and
温度敏感因子消除电阻,该温度敏感因子消除电阻的第一端根据该第一双极型晶体管的基极-发射极电压偏置,该温度敏感因子消除电阻的第二端根据该第二双极型晶体管的基极-发射极电压偏置。a temperature sensitivity cancellation resistor having a first terminal biased according to the base-emitter voltage of the first bipolar transistor and a second terminal biased according to the second bipolar transistor base-emitter voltage bias of a transistor.
进一步的,该带隙核心还包括:Further, the bandgap core also includes:
单运算放大器;Single operational amplifier;
第一分压器,具有耦接在该第一双极晶体管的发射极端子和该单运算放大器的负输入端子之间的第一分压电阻器、以及耦接在该单运算放大器的负输入端子和地之间的第二分压电阻器;A first voltage divider having a first voltage dividing resistor coupled between the emitter terminal of the first bipolar transistor and the negative input terminal of the single operational amplifier, and a first voltage dividing resistor coupled between the negative input terminal of the single operational amplifier a second voltage dividing resistor between the terminals and ground;
第二分压器,具有耦接在该温度敏感因子消除电阻的第一端与该单运算放大器的正输入端子之间的第三分压电阻,以及耦接在该单运算放大器的正该输入端子和地之间的第四分压电阻。从而使单运算放大器可以适应于例如低电压的电源线设计。The second voltage divider has a third voltage dividing resistor coupled between the first terminal of the temperature sensitivity elimination resistor and the positive input terminal of the single operational amplifier, and a third voltage dividing resistor coupled between the positive input terminal of the single operational amplifier. Fourth voltage divider resistor between terminals and ground. This allows the single op amp to be adapted to, for example, low voltage power line designs.
进一步的,该带隙核心还包括:Further, the bandgap core also includes:
第一电流MOS,具有耦接至该电源线的源极端子、耦接至该第一双极晶体管的发射极端子与该第一分压电阻之间的连接端子的漏极端子;以及The first current MOS has a source terminal coupled to the power line, a drain terminal coupled to the connection terminal between the emitter terminal of the first bipolar transistor and the first voltage dividing resistor; and
第二电流MOS,具有耦接至该电源线的源极端子、耦接至该温度敏感因子消除电阻的第一端与该第三分压电阻的连接端子的漏极端子;The second current MOS has a source terminal coupled to the power line and a drain terminal coupled to the connection terminal of the first end of the temperature-sensitive factor elimination resistor and the third voltage dividing resistor;
其中:in:
该第一电流MOS的栅极端子与该第二电流MOS的栅极端子连接;以及The gate terminal of the first current MOS is connected to the gate terminal of the second current MOS; and
该单运算放大器的输出端子耦接该第一电流MOS的栅极端子与该第二电流MOS的栅极端子。The output terminal of the single operational amplifier is coupled to the gate terminal of the first current MOS and the gate terminal of the second current MOS.
进一步的,该带隙核心还包括:Further, the bandgap core also includes:
第三电流MOS,具有耦接该电源线的源极端子、耦接该第一电流MOS的栅极端子和第二电流MOS的栅极端子的栅极端子;以及The third current MOS has a source terminal coupled to the power line, a gate terminal coupled to the gate terminal of the first current MOS and a gate terminal of the second current MOS; and
第三电阻,将该第三电流MOS的漏极端子接地;The third resistor connects the drain terminal of the third current MOS to ground;
其中,该第三电流MOS的漏极端子与第该三电阻之间的连接端子耦接该带隙电路的输出端子。上述设计以顺利的产生带隙电压。Wherein, the connection terminal between the drain terminal of the third current MOS and the third resistor is coupled to the output terminal of the bandgap circuit. The above design can successfully generate the band gap voltage.
进一步的,该电源线的偏置电压为1.2V。因此本发明适用于低电压设计。Further, the bias voltage of the power line is 1.2V. The invention is therefore suitable for low voltage designs.
进一步的,该带隙核心还包括:Further, the bandgap core also includes:
第一运算放大器,具有耦接该第一双极型晶体管的发射极端子的负输入端子、以及耦接该温度敏感因子消除电阻的第一端的正输入端子。The first operational amplifier has a negative input terminal coupled to the emitter terminal of the first bipolar transistor, and a positive input terminal coupled to the first terminal of the temperature sensitivity elimination resistor.
进一步的,该带隙核心还包括:Further, the bandgap core also includes:
第一电流MOS,具有耦接至该电源线的源极端子、耦接至该第一双极晶体管的发射极端子的漏极端子;以及A first current MOS having a source terminal coupled to the power line, a drain terminal coupled to the emitter terminal of the first bipolar transistor; and
第二电流MOS,具有耦接于该电源线的源极端子、耦接于该温度敏感因子消除电阻的第一端的漏极端子;The second current MOS has a source terminal coupled to the power line and a drain terminal coupled to the first end of the temperature-sensitive factor elimination resistor;
其中:in:
该第一电流MOS的栅极端子与该第二电流MOS的栅极端子连接;The gate terminal of the first current MOS is connected to the gate terminal of the second current MOS;
该第一运算放大器的输出端子耦接该第一电流MOS的栅极端子与该第二电流MOS的栅极端子。The output terminal of the first operational amplifier is coupled to the gate terminal of the first current MOS and the gate terminal of the second current MOS.
进一步的,该带隙核心还包括:Further, the bandgap core also includes:
第三电流MOS,具有耦接该电源线的源极端子、耦接该第一电流MOS的栅极端子和该第二电流MOS的栅极端子的栅极端子;以及The third current MOS has a source terminal coupled to the power line, a gate terminal coupled to the gate terminal of the first current MOS and a gate terminal of the second current MOS; and
第三电阻,将该第三电流MOS的漏极端子接地;The third resistor connects the drain terminal of the third current MOS to ground;
其中,该第三电流MOS的漏极端子与该第三电阻之间的连接端子耦接该带隙电路的输出端子。上述设计以顺利的产生带隙电压。Wherein, the connection terminal between the drain terminal of the third current MOS and the third resistor is coupled to the output terminal of the bandgap circuit. The above design can successfully generate the band gap voltage.
进一步的,该带隙核心还包括:Further, the bandgap core also includes:
第二运算放大器,具有耦接至该第一双极型晶体管的发射极端子的负输入端子;a second operational amplifier having a negative input terminal coupled to the emitter terminal of the first bipolar transistor;
第四电阻,将该第二运算放大器的正输入端子接地;a fourth resistor to connect the positive input terminal of the second operational amplifier to ground;
第四电流MOS,具有耦接该电源线的源极端子、耦接该第二运算放大器的输出端子的栅极端子、通过该第四电阻接地的漏极端子;以及The fourth current MOS has a source terminal coupled to the power line, a gate terminal coupled to the output terminal of the second operational amplifier, and a drain terminal connected to ground through the fourth resistor; and
第五电流MOS,具有耦接该电源线的源极端子、耦接该第四电流MOS的栅极端子的栅极端子、通过该第三电阻接地的漏极端子。第一运算放大器和第二运算放大器的设计可以适应于例如高电压的电源线设计。The fifth current MOS has a source terminal coupled to the power line, a gate terminal coupled to the gate terminal of the fourth current MOS, and a drain terminal connected to ground through the third resistor. The design of the first operational amplifier and the second operational amplifier may be adapted to, for example, high voltage power line designs.
进一步的,该电源线的偏置电压为1.5V。因此本发明适用于高电压设计。Further, the bias voltage of the power line is 1.5V. The invention is therefore suitable for high voltage designs.
本发明的具有自适应启动设计的带隙电路由于包括:带隙核心,使用成对的双极晶体管来消除温度敏感因子,从而产生与温度变化无关的带隙电压;以及启动电路,将该成对双极晶体管中的第一双极晶体管的发射极端子耦接到电源线以启动该带隙核心,其中,该启动电路包括参考双极晶体管,该参考双极晶体管提供阈值电压作为用于将该电源线与该第一双极晶体管的发射极端子断开的参考。本发明的上述方式可以使带隙电路具有的操作时间窗口更加宽裕,使所需要的带隙电压更加稳定的产生,并且更加容易控制。The bandgap circuit with adaptive start-up design of the present invention includes: a bandgap core, which uses pairs of bipolar transistors to eliminate temperature-sensitive factors, thereby generating a bandgap voltage that is independent of temperature changes; and a start-up circuit that converts this into An emitter terminal of a first of the pair of bipolar transistors is coupled to the power line to activate the bandgap core, wherein the activation circuit includes a reference bipolar transistor that provides a threshold voltage as the The power line is a reference disconnected from the emitter terminal of the first bipolar transistor. The above-described method of the present invention can make the operation time window of the bandgap circuit more generous, generate the required bandgap voltage more stably, and make it easier to control.
附图说明Description of drawings
图1是描绘根据本发明示例性实施例的带隙电路100的框图;1 is a block diagram depicting a bandgap circuit 100 according to an exemplary embodiment of the present invention;
图2描绘了根据本发明示例性实施例的具有低电压带隙核心(low-voltagebandgap core)202的带隙电路200;以及2 depicts a bandgap circuit 200 having a low-voltage bandgap core 202 in accordance with an exemplary embodiment of the present invention; and
图3描绘了根据本发明示例性实施例的具有高电压带隙核心(high-voltagebandgap core)302的带隙电路300。Figure 3 depicts a bandgap circuit 300 with a high-voltage bandgap core 302 in accordance with an exemplary embodiment of the present invention.
具体实施方式Detailed ways
在下面对本发明的实施例的详细描述中,参考了附图,这些附图构成了本发明的一部分,并且在附图中通过图示的方式示出了可以实践本发明的特定的优选实施例。对这些实施例进行了足够详细的描述,以使本领域技术人员能够实践它们,并且应当理解,在不脱离本发明的精神和范围的情况下,可以利用其他实施例,并且可以进行机械,结构和程序上的改变。本发明。因此,以下详细描述不应被理解为限制性的,并且本发明的实施例的范围仅由所附权利要求限定。所描述的附图仅是示意性的而非限制性的。在附图中,为了说明的目的,一些元件的尺寸可能被放大而不是按比例绘制。在本发明的实践中,尺寸和相对尺寸不对应于实际尺寸。In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form a part hereof and which illustrate by way of illustration certain preferred embodiments in which the invention may be practiced. . These embodiments are described in sufficient detail to enable those skilled in the art to practice them, and it is to be understood that other embodiments may be utilized and mechanical, structural and structural changes may be made without departing from the spirit and scope of the invention. and procedural changes. this invention. Accordingly, the following detailed description is not to be construed as limiting, and the scope of embodiments of the invention is defined only by the appended claims. The drawings described are illustrative only and not restrictive. In the drawings, the dimensions of some elements may be exaggerated and not drawn to scale for illustrative purposes. In the practice of the invention, dimensions and relative dimensions do not correspond to actual dimensions.
将理解的是,尽管术语“第一”、“第二”、“第三”、“主要”、“次要”等在本文中可用于描述各种组件、组件、区域、层和/或部分,但是这些组件、组件、区域、这些层和/或部分不应受到这些术语的限制。这些术语仅用于区分一个组件、组件、区域、层或部分与另一区域、层或部分。因此,在不脱离本发明构思的教导的情况下,下面讨论的第一或主要组件、组件、区域、层或部分可以称为第二或次要组件、组件、区域、层或部分。It will be understood that, although the terms "first," "second," "third," "primary," "secondary," etc. may be used herein to describe various components, components, regions, layers and/or sections , but these components, components, regions, layers and/or portions shall not be limited by these terms. These terms are only used to distinguish one component, component, region, layer or section from another region, layer or section. Thus, a first or primary component, component, region, layer or section discussed below could be termed a secondary or secondary component, component, region, layer or section without departing from the teachings of the inventive concept.
此外,为了便于描述,本文中可以使用诸如“在...下方”、“在...之下”、“在...下”、“在...上方”、“在...之上”之类的空间相对术语,以便于描述一个组件或特征与之的关系。如图所示的另一组件或特征。除了在图中描述的方位之外,空间相对术语还意图涵盖设备在使用或运行中的不同方位。该设备可以以其他方式定向(旋转90度或以其他定向),并且在此使用的空间相对描述语可以同样地被相应地解释。另外,还将理解的是,当“层”被称为在两层“之间”时,它可以是两层之间的唯一层,或者也可以存在一个或多个中间层。In addition, for convenience of description, terms such as “below”, “under”, “below”, “above”, “between” may be used herein. Spatially relative terms such as "on" to describe the relationship of a component or feature to it. Another component or feature as shown in a figure. In addition to the orientation depicted in the figures, the spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a "layer" is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
术语“大约”、“大致”和“约”通常表示规定值的±20%、或所述规定值的±10%、或所述规定值的±5%、或所述规定值的±3%、或规定值的±2%、或规定值的±1%、或规定值的±0.5%的范围内。本发明的规定值是近似值。当没有具体描述时,所述规定值包括“大约”、“大致”和“约”的含义。本文所使用的术语仅出于描述特定实施例的目的,并不旨在限制本发明。如本文所使用的,单数术语“一”,“一个”和“该”也旨在包括复数形式,除非上下文另外明确指出。本文所使用的术语仅出于描述特定实施例的目的,并不旨在限制本发明构思。如本文所使用的,单数形式“一个”、“一种”和“该”也旨在包括复数形式,除非上下文另外明确指出。The terms "about", "approximately" and "approximately" generally mean ±20% of the stated value, or ±10% of the stated value, or ±5% of the stated value, or ±3% of the stated value , or within the range of ±2% of the specified value, or ±1% of the specified value, or ±0.5% of the specified value. The values specified in this invention are approximate. When not specifically described, stated values include the meanings of "about," "approximately," and "approximately." The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular terms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the inventive concept. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
将理解的是,当将“组件”或“层”称为在另一组件或层“上”、“连接至”、“耦接至”或“邻近”时,它可以直接在其他组件或层上、与其连接、耦接或相邻、或者可以存在中间组件或层。相反,当组件称为“直接在”另一组件或层“上”、“直接连接至”、“直接耦接至”或“紧邻”另一组件或层时,则不存在中间组件或层。It will be understood that when a "component" or "layer" is referred to as being "on," "connected to," "coupled to" or "adjacent" another component or layer, it can be directly on the other component or layer Intermediate components or layers may be present on, connected to, coupled to, or adjacent thereto. In contrast, when a component is referred to as being "directly on," "directly connected to," "directly coupled to" or "immediately adjacent" another component or layer, there are no intervening components or layers present.
注意:(i)在整个附图中相同的特征将由相同的附图标记表示,并且不一定在它们出现的每个附图中都进行详细描述,并且(ii)一系列附图可能显示单个项目的不同方面,每个方面都与各种参考标签相关联,这些参考标签可能会出现在整个序列中,或者可能只出现在序列的选定图中。Note: (i) like features will be designated by the same reference numerals throughout the Figures and will not necessarily be described in detail in every Figure in which they appear, and (ii) a series of Figures may show a single item Each aspect is associated with various reference labels that may appear throughout the sequence, or may appear only in selected plots of the sequence.
图1是描绘根据本发明示例性实施例的带隙电路100的框图。FIG. 1 is a block diagram depicting a bandgap circuit 100 according to an exemplary embodiment of the present invention.
带隙电路100包括带隙核心(bandgap core)102和启动电路(start-up circuit)104。带隙核心102使用成对的(paired)双极晶体管(bipolar transistor,BJT)来消除温度敏感因子(factor),从而产生与温度变化无关的带隙电压(bandgap voltage)Vbg。启动电路104将带隙核心102的成对的BJT(一对BJT)中的第一BJT的发射极(emitter)端子耦接到电源线以启动带隙核心102。特别地,启动电路104包括参考(reference)BJT,参考BJT提供阈值电压(threshold voltage)作为断开电源线与第一BJT的发射极端子的参考(reference)(电压)。The bandgap circuit 100 includes a bandgap core 102 and a start-up circuit 104 . The bandgap core 102 uses paired bipolar transistors (BJTs) to eliminate temperature sensitivity factors, thereby generating a bandgap voltage Vbg that is independent of temperature changes. Startup circuit 104 couples the emitter terminal of a first BJT in a pair of BJTs of bandgap core 102 to a power line to turn on bandgap core 102 . In particular, the startup circuit 104 includes a reference BJT that provides a threshold voltage as a reference (voltage) for disconnecting the power line from the emitter terminal of the first BJT.
启动电路104内的参考BJT的阈值电压可以真实地反映带隙核心102的第一BJT的导通阈值(turn-on threshold)。因此,启动电路104不会过早地断开从电源线到带隙核心102的第一BJT的发射极端子的耦接。带隙核心102的第一BJT的发射极端子保持与电源线耦接,直到真正导通。带隙电路100不会陷入死锁区域(deadlock region)。本发明实施例图1所示的带隙电路100可以由图2所示的带隙电路200实现,也可以由图3所示的带隙电路300实现。The threshold voltage of the reference BJT within the startup circuit 104 may truly reflect the turn-on threshold of the first BJT of the bandgap core 102 . Therefore, the startup circuit 104 does not prematurely decouple the power line from the emitter terminal of the first BJT of the bandgap core 102 . The emitter terminal of the first BJT of bandgap core 102 remains coupled to the power line until true conduction. The bandgap circuit 100 will not fall into a deadlock region. The bandgap circuit 100 shown in FIG. 1 according to the embodiment of the present invention can be implemented by the bandgap circuit 200 shown in FIG. 2 , or can also be implemented by the bandgap circuit 300 shown in FIG. 3 .
在传统技术中,启动电路使用反相器的阈值电压作为参考(电压)来将电源线与带隙核心的第一BJT的发射极端子断开。传统的启动电路可能过早地将电源线与带隙核心的第一BJT的发射极端子断开。传统的带隙电路可能陷入死锁区域。In conventional technology, the startup circuit uses the threshold voltage of the inverter as a reference (voltage) to disconnect the power line from the emitter terminal of the first BJT of the bandgap core. A conventional startup circuit may prematurely disconnect the power line from the emitter terminal of the first BJT of the bandgap core. Traditional bandgap circuits can fall into deadlock regions.
图2描绘了根据本发明示例性实施例的带隙电路200。Figure 2 depicts a bandgap circuit 200 according to an exemplary embodiment of the present invention.
带隙电路200包括带隙核心202和启动电路204。带隙核心202使用成对的BJT Ql和Q2来消除温度敏感因子(例如,由温度敏感因子消除电阻Rte的电压差消除),从而产生与温度变化无关的带隙电压Vbg。启动电路204将第一BJT Q1的发射极端子耦接到电源线AVDD12以启动带隙核心202。启动电路204包括参考BJT Q0,参考BJT Q0提供阈值电压Vbe0作为用于将电源线AVDD12与第一BJT Q1的发射极端子断开的参考(电压)。如图所示,参考BJT Q0为二极管连接形式(diode-connected form),就像第一BJT Q1一样。参考BJT Q0的基极与集电极直接电性连接,并且均连接到地;第一BJT Q1的基极与集电极直接电性连接,并且均连接到地;第二BJT Q2的基极与集电极直接电性连接,并且均连接到地。Bandgap circuit 200 includes bandgap core 202 and enabling circuit 204 . The bandgap core 202 uses a pair of BJTs Q1 and Q2 to eliminate temperature sensitivity factors (eg, voltage difference cancellation by the temperature sensitivity factor elimination resistor Rte), thereby generating a bandgap voltage Vbg that is independent of temperature changes. Enablement circuit 204 couples the emitter terminal of first BJT Q1 to power line AVDD12 to enable bandgap core 202 . The startup circuit 204 includes a reference BJT Q0 that provides a threshold voltage Vbe0 as a reference (voltage) for disconnecting the power supply line AVDD12 from the emitter terminal of the first BJT Q1. As shown in the figure, the reference BJT Q0 is in diode-connected form, just like the first BJT Q1. The base and collector of the reference BJT Q0 are directly electrically connected, and both are connected to ground; the base and collector of the first BJT Q1 are directly electrically connected, and both are connected to ground; the base and collector of the second BJT Q2 The electrodes are directly electrically connected and are connected to ground.
启动电路204还具有比较器Comp,比较器Comp具有接收与从带隙核心202感测到的感测电流Ise相关的感测电压Vse的正输入端子‘+’、耦合到参考BJT Q0的发射极端子以接收参考BJT Q0的基极-发射极电压Vbe0的负输入端子“-”、以及输出控制信号CS以控制第一BJT Q1的发射极端子是否连接至电源线AVDD12的输出端子。Start-up circuit 204 also has a comparator Comp having a positive input terminal '+' that receives a sense voltage Vse related to sense current Ise sensed from bandgap core 202, an emitter terminal coupled to reference BJT Q0 to receive a negative input terminal "-" that refers to the base-emitter voltage Vbe0 of the BJT Q0, and output a control signal CS to control whether the emitter terminal of the first BJT Q1 is connected to the output terminal of the power line AVDD12.
启动电路204还包括启动控制MOS(metal–oxide–semiconductor field-effect)晶体管Msu,启动控制MOS晶体管Msu为PMOS,启动控制MOS晶体管Msu的栅极端子耦接比较器Comp的输出端子,并受控制信号CS控制,启动控制MOS晶体管Msu的源极端子耦接到电源线AVDD12(例如通过使能MOS Me2偶接到电源线AVDD12),启动控制MOS晶体管Msu的漏极端子耦接到第一BJT Q1的发射极端子。The startup circuit 204 also includes a startup control MOS (metal-oxide-semiconductor field-effect) transistor Msu. The startup control MOS transistor Msu is PMOS. The gate terminal of the startup control MOS transistor Msu is coupled to the output terminal of the comparator Comp and is controlled. The signal CS controls, the source terminal of the start-up control MOS transistor Msu is coupled to the power line AVDD12 (for example, by enabling the MOS Me2 to be coupled to the power line AVDD12), and the drain terminal of the start-up control MOS transistor Msu is coupled to the first BJT Q1 emitter terminal.
启动电路204还具有第一电阻器R1,第一电阻器R1将参考BJT Q0的发射极端子耦接到电源线AVDD12。启动电路204还具有第二电阻R2,二电阻R2耦接在比较器Comp的正输入端“+”与地(接地)之间,感测电流Ise流经第二电阻R2以产生感测电压Vse。启动电路204还具有电流镜MOS Mcm,电流镜MOS Mcm镜像带隙核心202的电流以产生流经第二电阻R2的感测电流Ise。Startup circuit 204 also has a first resistor R1 coupling the emitter terminal of reference BJT Q0 to power line AVDD12. The startup circuit 204 also has a second resistor R2. The two resistors R2 are coupled between the positive input terminal "+" of the comparator Comp and ground (ground). The sensing current Ise flows through the second resistor R2 to generate the sensing voltage Vse. . The startup circuit 204 also has a current mirror MOS Mcm that mirrors the current of the bandgap core 202 to generate a sensing current Ise flowing through the second resistor R2.
启动电路204还具有可选的使能(enable)MOS Me1和Me2。第一使能MOS Me1耦接在电源线AVDD12与第一电阻器R1之间,并受启动电路204的使能(或启用)信号Enb控制。第二使能MOS Me2耦接在电源线AVDD12和启动控制MOS晶体管Msu的源极端子之间,并受启动电路204的使能信号Enb控制。The startup circuit 204 also has optional enable MOS Me1 and Me2. The first enable MOS Me1 is coupled between the power line AVDD12 and the first resistor R1 and is controlled by the enable (or enable) signal Enb of the startup circuit 204 . The second enable MOS Me2 is coupled between the power line AVDD12 and the source terminal of the startup control MOS transistor Msu, and is controlled by the enable signal Enb of the startup circuit 204 .
在这样的电路架构中,使能的启动电路204向带隙核心202消耗功率,直到带隙核心202真正启动。当感测到的电压Vse大于BJT的基极-发射极电压(Vbe0)时,意味着带隙核心202内的第一BJT Q1真正工作,并且带隙核心202成功地产生带隙电压Vbg。确保启动电路204不会过早地将电源线AVDD12与第一BJT Q1的发射极端断开。在一个实施例中,带隙核心202成功地产生带隙电压Vbg为不等于零的电压,例如为0.6V或者其他数值,本发明实施例不做具体限制。In such a circuit architecture, the enabled startup circuit 204 consumes power from the bandgap core 202 until the bandgap core 202 actually starts. When the sensed voltage Vse is greater than the base-emitter voltage of the BJT (Vbe0), it means that the first BJT Q1 within the bandgap core 202 is actually working, and the bandgap core 202 successfully generates the bandgap voltage Vbg. Ensure that startup circuit 204 does not prematurely disconnect power line AVDD12 from the emitter terminal of first BJT Q1. In one embodiment, the bandgap core 202 successfully generates a bandgap voltage Vbg that is not equal to zero, such as 0.6V or other values, which is not specifically limited in this embodiment of the present invention.
图2所示低电压设计,电源线AVDD12偏置为1.2V,带隙核心202采用单(single)运算放大器(operational amplifier)Op。带隙核心202使用两个分压器(voltage divider)将信号移位到适当的电平(level)以输入低电压设计的单运算放大器Op。第一分压器具有耦接在第一BJT Q1的发射极端子与单运算放大器Op的负输入端子“-”之间的第一分压电阻器Rd1以及耦合在单运算放大器Op的负输入端子“-”与地(接地)之间的第二分压电阻器Rd2。第二分压器具有耦接在温度敏感因子消除电阻Rte的第一端(end)与单运算放大器Op的正输入端子“+”之间的第三分压电阻Rd3,以及耦接在单运算放大器Op的正输入端“+”与地之间的第四分压电阻Rd4。The low-voltage design shown in Figure 2 has the power line AVDD12 biased at 1.2V, and the bandgap core 202 uses a single operational amplifier Op. The bandgap core 202 uses two voltage dividers to shift the signal to the appropriate level for input to a single operational amplifier Op of a low voltage design. The first voltage divider has a first voltage dividing resistor Rd1 coupled between the emitter terminal of the first BJT Q1 and the negative input terminal "-" of the single operational amplifier Op, and a first voltage dividing resistor Rd1 coupled between the negative input terminal of the single operational amplifier Op. The second voltage dividing resistor Rd2 between "-" and ground (ground). The second voltage divider has a third voltage dividing resistor Rd3 coupled between the first end (end) of the temperature sensitivity factor elimination resistor Rte and the positive input terminal "+" of the single operational amplifier Op, and is coupled to the single operational amplifier Op. The fourth voltage dividing resistor Rd4 between the positive input terminal "+" of the amplifier Op and ground.
带隙核心202还具有第一电流MOS Mc1和第二电流MOS Mc2。第一电流MOS Mc1的源极端子耦接到电源线AVDD12,第一电流MOS Mc1的漏极端子耦接到第一BJT Q1的发射极端子和第一分压电阻器Rd1之间的连接端子。第二电流MOS Mc2的源极耦接电源线AVDD12,其漏极耦接温度敏感因子消除电阻Rte的第一端与第三分压电阻Rd3之间的连接端子。第一电流MOS Mc1的栅极端子连接到第二电流MOS Mc2的栅极端子。单运算放大器Op的输出端子耦接第一电流MOS Mc1的栅极端子与第二电流MOS Mc2的栅极端子。温度敏感因子消除电阻Rte的第一端连接至第三分压电阻Rd3并且还连接至第二电流MOS Mc2的漏极。温度敏感因子消除电阻Rte的第二端连接至第二BJT Q2的发射极。The bandgap core 202 also has a first current MOS Mc1 and a second current MOS Mc2. The source terminal of the first current MOS Mc1 is coupled to the power line AVDD12, and the drain terminal of the first current MOS Mc1 is coupled to the connection terminal between the emitter terminal of the first BJT Q1 and the first voltage dividing resistor Rd1. The source of the second current MOS Mc2 is coupled to the power line AVDD12, and its drain is coupled to the connection terminal between the first end of the temperature-sensitive factor elimination resistor Rte and the third voltage dividing resistor Rd3. The gate terminal of the first current MOS Mc1 is connected to the gate terminal of the second current MOS Mc2. The output terminal of the single operational amplifier Op is coupled to the gate terminal of the first current MOS Mc1 and the gate terminal of the second current MOS Mc2. The first end of the temperature sensitivity factor elimination resistor Rte is connected to the third voltage dividing resistor Rd3 and is also connected to the drain of the second current MOS Mc2. The second terminal of the temperature sensitivity elimination resistor Rte is connected to the emitter of the second BJT Q2.
带隙核心202还具有第三电流MOS Mc3和第三电阻器R3。第三电流MOS Mc3具有耦接至电源线AVDD12的源极端子以及耦接至第一电流MOS Mc1和第二电流MOS Mc2的栅极端子的栅极端子。第三电阻R3将第三电流MOS Mc3的漏极端子耦接至地。第三电流MOS Mc3的漏极端子与第三电阻器R3之间的连接端子耦接至带隙电路200的输出端子(Vbg)。Bandgap core 202 also has a third current MOS Mc3 and a third resistor R3. The third current MOS Mc3 has a source terminal coupled to the power supply line AVDD12 and a gate terminal coupled to the gate terminals of the first and second current MOS Mc1 and MOS Mc2. The third resistor R3 couples the drain terminal of the third current MOS Mc3 to ground. The connection terminal between the drain terminal of the third current MOS Mc3 and the third resistor R3 is coupled to the output terminal (Vbg) of the bandgap circuit 200 .
当带隙核心202尚未导通时,使能的启动电路204无法感测到任何电流(Ise为0),并且感测到的电压Vse低于参考BJT Q0的基极-发射极电压Vbe0,比较器Comp输出低电平控制信号CS以导通启动控制(start-up control)MOS晶体管Msu,从而将来自电源线AVDD12的电源强制到带隙核心202中。单运算放大器Op的负输入端子“-”处的电压电平升高,使得电流MOS 的栅极被拉低,带隙核心202开始工作。感测电压Vse增加。当感测电压Vse大于BJT阈值电压(Vbe0)时,意味着第一BJT Q1的发射极电压足够大以导通第一BJTQ1。比较器Comp将启动电路204与带隙核心202断开。与没有参考BJT Q0的传统启动电路相比,直到第一BJT Q1的发射极电压确实大于BJT的阈值电压且第一BJT Q1导通时,启动电路204才会断开电源线AVDD12与带隙核心202之间的连接。基于参考BJT Q0,启动电路204适应各种PVT(工艺,电压,温度,Process,Voltage,Temperature)角(corner)。本发明上述实施例的方式可以使带隙电路具有的操作时间窗口更加宽裕,使所需要的带隙电压Vbg(例如为非零电压)更加稳定的产生,并且更加容易控制。本发明实施例的方式由于可以适用的时间窗口更加宽裕,并且适用的电源电压范围更加宽泛,因此可以具有自适应启动设计,并且带隙电路可以适应各种PVT角,具有更广泛的适用性,通用性更强。When the bandgap core 202 is not yet conducting, the enabled start-up circuit 204 cannot sense any current (Ise is 0), and the sensed voltage Vse is lower than the base-emitter voltage Vbe0 of the reference BJT Q0, compare The device Comp outputs a low-level control signal CS to turn on a start-up control MOS transistor Msu, thereby forcing power from the power line AVDD12 into the bandgap core 202 . The voltage level at the negative input terminal "-" of the single operational amplifier Op increases, causing the current MOS The gate is pulled low and the bandgap core 202 begins to operate. The sensing voltage Vse increases. When the sensing voltage Vse is greater than the BJT threshold voltage (Vbe0), it means that the emitter voltage of the first BJT Q1 is large enough to turn on the first BJT Q1. Comparator Comp disconnects enable circuit 204 from bandgap core 202 . Compared with the traditional startup circuit without reference to BJT Q0, the startup circuit 204 will not disconnect the power line AVDD12 from the bandgap core until the emitter voltage of the first BJT Q1 is indeed greater than the threshold voltage of the BJT and the first BJT Q1 is turned on. 202 connection. Based on the reference BJT Q0, the startup circuit 204 adapts to various PVT (Process, Voltage, Temperature) corners. The above-mentioned embodiments of the present invention can make the operation time window of the bandgap circuit more generous, so that the required bandgap voltage Vbg (for example, a non-zero voltage) can be generated more stably, and can be more easily controlled. The method of the embodiment of the present invention has a wider applicable time window and a wider applicable power supply voltage range, so it can have an adaptive startup design, and the bandgap circuit can adapt to various PVT angles, and has wider applicability. More versatile.
图3描绘了根据本发明另一示例性实施例的带隙电路300。带隙电路300包括带隙核心302和启动电路304。启动电路304具有与图2的启动电路204相同的结构。与图2相比,带隙电路300是高电压设计。电源线AVDD15偏置为1.5V。带隙核心302使用两个级联的(cascaded)运算放大器Op1和Op2。在一个实施例中,带隙核心302成功地产生带隙电压Vbg为不等于零的电压,例如为0.6V或者其他数值,本发明实施例不做具体限制。Figure 3 depicts a bandgap circuit 300 according to another exemplary embodiment of the present invention. Bandgap circuit 300 includes bandgap core 302 and enabling circuit 304 . The startup circuit 304 has the same structure as the startup circuit 204 of FIG. 2 . Compared to Figure 2, bandgap circuit 300 is a high voltage design. Power line AVDD15 is biased to 1.5V. Bandgap core 302 uses two cascaded operational amplifiers Op1 and Op2. In one embodiment, the bandgap core 302 successfully generates a bandgap voltage Vbg that is not equal to zero, such as 0.6V or other values, which is not specifically limited in the embodiment of the present invention.
第一运算放大器Op1的负输入端子“-”耦接至第一BJT Q1的发射极端子,以及第一运算放大器Op1的正输入端子“+”耦接至温度敏感因子消除电阻Rte的第一端。带隙核心302还具有第一电流MOS Mc1和第二电流MOS Mc2。第一电流MOS Mc1具有耦接到电源线AVDD15的源极端子和耦接到第一BJT Q1的发射极端子的漏极端子。第二电流MOS Mc2的源极端子耦接电源线AVDD15,第二电流MOS Mc2的漏极端子耦接温度敏感因子消除电阻Rte的第一端。第一电流MOS Mc1的栅极端子连接至第二电流MOS Mc2的栅极端子。第一运算放大器Op1的输出端子耦接第一电流MOS Mc1与第二电流MOS Mc2的栅极端子。温度敏感因子消除电阻Rte的第一端连接至第一运算放大器Op1的正输入端子“+”并且还连接至第二电流MOS Mc2的漏极。温度敏感因子消除电阻Rte的第二端连接至第二BJT Q2的发射极。The negative input terminal "-" of the first operational amplifier Op1 is coupled to the emitter terminal of the first BJT Q1, and the positive input terminal "+" of the first operational amplifier Op1 is coupled to the first terminal of the temperature sensitivity elimination resistor Rte . The bandgap core 302 also has a first current MOS Mc1 and a second current MOS Mc2. The first current MOS Mc1 has a source terminal coupled to the power supply line AVDD15 and a drain terminal coupled to the emitter terminal of the first BJT Q1. The source terminal of the second current MOS Mc2 is coupled to the power line AVDD15, and the drain terminal of the second current MOS Mc2 is coupled to the first end of the temperature sensitive factor elimination resistor Rte. The gate terminal of the first current MOS Mc1 is connected to the gate terminal of the second current MOS Mc2. The output terminal of the first operational amplifier Op1 is coupled to the gate terminals of the first current MOS Mc1 and the second current MOS Mc2. The first end of the temperature sensitivity elimination resistor Rte is connected to the positive input terminal "+" of the first operational amplifier Op1 and is also connected to the drain of the second current MOS Mc2. The second terminal of the temperature sensitivity elimination resistor Rte is connected to the emitter of the second BJT Q2.
第二运算放大器Op2具有耦接至第一BJT Ql的发射极端子的负输入端子“-”。第二运算放大器Op2的正输入端子“+”通过第四电阻R4接地。带隙核心302还具有第四电流MOSMc4和第五电流MOS Mc5。第四电流MOS Mc4具有耦接到电源线AVDD15的源极端子、耦接到第二运算放大器Op2的输出端子的栅极端子、以及通过第四电阻器R4耦接到地的漏极端子。第五电流MOS Mc5具有耦接到电源线AVDD15的源极端子、耦接到第四电流MOS Mc4的栅极端子的栅极端子、以及通过第三电阻器R3耦接到地的漏极端子。The second operational amplifier Op2 has a negative input terminal "-" coupled to the emitter terminal of the first BJT Q1. The positive input terminal "+" of the second operational amplifier Op2 is connected to ground through the fourth resistor R4. The bandgap core 302 also has a fourth current MOSMc4 and a fifth current MOSMc5. The fourth current MOS Mc4 has a source terminal coupled to the power supply line AVDD15, a gate terminal coupled to the output terminal of the second operational amplifier Op2, and a drain terminal coupled to the ground through the fourth resistor R4. The fifth current MOS Mc5 has a source terminal coupled to the power supply line AVDD15, a gate terminal coupled to the gate terminal of the fourth current MOS Mc4, and a drain terminal coupled to the ground through the third resistor R3.
对于这种高电压带隙核心302,所提出的启动电路304仍然适应带隙核心302的第一BJT Q1的BJT阈值。本发明上述实施例的方式可以使带隙电路具有的操作时间窗口更加宽裕,使所需要的带隙电压Vbg(例如为非零电压)更加稳定的产生,并且更加容易控制。本发明实施例的方式由于可以适用的时间窗口更加宽裕,并且适用的电源电压范围更加宽泛,因此可以具有自适应启动设计,并且带隙电路可以适应各种PVT角,具有更广泛的适用性,通用性更强。For such a high voltage bandgap core 302, the proposed startup circuit 304 still adapts to the BJT threshold of the first BJT Q1 of the bandgap core 302. The above-mentioned embodiments of the present invention can make the operation time window of the bandgap circuit more generous, so that the required bandgap voltage Vbg (for example, a non-zero voltage) can be generated more stably, and can be more easily controlled. The method of the embodiment of the present invention has a wider applicable time window and a wider applicable power supply voltage range, so it can have an adaptive startup design, and the bandgap circuit can adapt to various PVT angles, and has wider applicability. More versatile.
任何具有参考BJT Q0的启动电路都应当被认为在本发明的范围内。由所提出的启动电路驱动的带隙核心可以有许多变化。Any startup circuit with a reference to BJT Q0 should be considered within the scope of this invention. There can be many variations of the bandgap core driven by the proposed startup circuit.
本领域的技术人员将容易地观察到,在保持本发明教导的同时,可以做出许多该设备和方法的修改和改变。因此,上述公开内容应被解释为仅由所附权利要求书的界限和范围所限制。Those skilled in the art will readily observe that many modifications and variations of the apparatus and methods can be made while maintaining the teachings of the present invention. Accordingly, the foregoing disclosure should be construed as being limited only by the metes and bounds of the appended claims.
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