CN117348655A - Bandgap circuit with adaptive start-up design - Google Patents
Bandgap circuit with adaptive start-up design Download PDFInfo
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- CN117348655A CN117348655A CN202310797435.2A CN202310797435A CN117348655A CN 117348655 A CN117348655 A CN 117348655A CN 202310797435 A CN202310797435 A CN 202310797435A CN 117348655 A CN117348655 A CN 117348655A
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- G—PHYSICS
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- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
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Abstract
The invention discloses a band gap circuit with self-adaptive starting design, which comprises: a bandgap core using a pair of bipolar transistors to eliminate temperature sensitive factors, thereby generating a bandgap voltage independent of temperature variation; and a start-up circuit coupling an emitter terminal of a first bipolar transistor of the pair of bipolar transistors to a power supply line to start the bandgap core, wherein the start-up circuit includes a reference bipolar transistor providing a threshold voltage as a reference for disconnecting the power supply line from the emitter terminal of the first bipolar transistor. The mode of the invention can make the operation time window of the band gap circuit more wide, make the required band gap voltage more stably generated and be easier to control.
Description
Technical Field
The invention relates to the technical field of circuits, in particular to a band gap circuit with a self-adaptive starting design.
Background
In an integrated circuit (integrated circuit), a bandgap voltage (bandgap voltage) reference (reference) is required, which is a temperature independent (temperature independent) voltage reference (voltage reference). The bandgap circuit generates a constant voltage regardless of power supply variations, temperature variations, or circuit loading of the device.
The start-up of the bandgap core is an important topic in the art.
Disclosure of Invention
In view of the above, the present invention provides a bandgap circuit with adaptive start-up design to solve the above-mentioned problems.
According to a first aspect of the present invention, a bandgap circuit with an adaptive start-up design is disclosed, comprising:
a bandgap core using a pair of bipolar transistors to eliminate temperature sensitive factors, thereby generating a bandgap voltage independent of temperature variation; and
a start-up circuit coupling an emitter terminal of a first bipolar transistor of the pair of bipolar transistors to a power supply line to start up the bandgap core,
wherein the start-up circuit comprises a reference bipolar transistor providing a threshold voltage as a reference for disconnecting the power supply line from the emitter terminal of the first bipolar transistor.
Further, the reference bipolar transistor is in a diode-connected form, identical to the first bipolar transistor. The threshold voltage is smoothly generated and supplied to the comparator for more accurately determining whether the emitter terminal of the first bipolar transistor is disconnected or connected with the power line.
Further, the starting circuit further includes: a comparator having a positive input terminal receiving a sense voltage related to a sense current sensed from the bandgap core, a negative input terminal coupled to an emitter terminal of the reference bipolar transistor, and an output terminal outputting a control signal to connect or disconnect the emitter terminal of the first bipolar transistor to or from the power supply line. The use of comparators may make it more desirable to determine whether the emitter terminal of the first bipolar transistor is disconnected or connected to the power supply line.
Further, the starting circuit further includes: a start-up control MOS transistor has a gate terminal coupled to the output terminal of the comparator, a source terminal coupled to the power supply line, and a drain terminal coupled to the emitter terminal of the first bipolar transistor. This allows the control MOS transistor to be activated with the output control of the comparator, thereby determining whether the emitter terminal of the first bipolar transistor is disconnected from or connected to the power supply line.
Further, the starting circuit further includes: a first resistor coupling an emitter terminal of the reference bipolar transistor to the power line,
wherein a connection terminal between the first resistor and the reference bipolar transistor is coupled to a negative input terminal of the comparator. Thereby generating a threshold voltage.
Further, the starting circuit further includes: and a second resistor coupled between the positive input terminal of the comparator and ground, through which the sensing current flows. To generate a sensing voltage.
Further, the starting circuit further includes: a current mirror MOS mirroring the current of the bandgap core to generate the sensing current flowing through the second resistor. Thereby smoothly generating the sensing voltage.
Further, the starting circuit further includes: a first enable MOS coupled between the power line and the first resistor and controlled by an enable signal of the start circuit; and
and a second enabling MOS coupled between the power line and the source terminal of the start control MOS transistor and controlled by the enabling signal of the start circuit. Thereby controlling generation of the threshold voltage and the sensing voltage.
Further, the bandgap core further includes: a second bipolar transistor in the form of a diode connection and paired with the first bipolar transistor; and
a temperature-sensitive factor-eliminating resistor, a first terminal of the temperature-sensitive factor-eliminating resistor being biased according to a base-emitter voltage of the first bipolar transistor, and a second terminal of the temperature-sensitive factor-eliminating resistor being biased according to a base-emitter voltage of the second bipolar transistor.
Further, the bandgap core further includes:
a single operational amplifier;
a first voltage divider having a first voltage dividing resistor coupled between an emitter terminal of the first bipolar transistor and a negative input terminal of the single operational amplifier, and a second voltage dividing resistor coupled between the negative input terminal of the single operational amplifier and ground;
the second voltage divider is provided with a third voltage dividing resistor coupled between the first end of the temperature sensitive factor eliminating resistor and the positive input terminal of the single operational amplifier, and a fourth voltage dividing resistor coupled between the positive input terminal of the single operational amplifier and ground. So that the single op amp can be adapted to, for example, a low voltage power line design.
Further, the bandgap core further includes:
a first current MOS having a source terminal coupled to the power supply line, a drain terminal coupled to a connection terminal between the emitter terminal of the first bipolar transistor and the first voltage dividing resistor; and
a second current MOS having a source terminal coupled to the power line, a drain terminal coupled to the first end of the temperature-sensitive factor elimination resistor and the connection terminal of the third voltage dividing resistor;
wherein:
the gate terminal of the first current MOS is connected with the gate terminal of the second current MOS; and
the output terminal of the single operational amplifier is coupled to the gate terminal of the first current MOS and the gate terminal of the second current MOS.
Further, the bandgap core further includes:
a third current MOS having a source terminal coupled to the power line, a gate terminal coupled to the gate terminal of the first current MOS, and a gate terminal of the second current MOS; and
a third resistor for grounding the drain terminal of the third current MOS;
the connection terminal between the drain terminal of the third current MOS and the third resistor is coupled to the output terminal of the bandgap circuit. The design can smoothly generate the band gap voltage.
Further, the bias voltage of the power supply line is 1.2V. The invention is therefore suitable for low voltage designs.
Further, the bandgap core further includes:
a first operational amplifier having a negative input terminal coupled to the emitter terminal of the first bipolar transistor and a positive input terminal coupled to the first end of the temperature-sensitive factor-eliminating resistor.
Further, the bandgap core further includes:
a first current MOS having a source terminal coupled to the power supply line, a drain terminal coupled to the emitter terminal of the first bipolar transistor; and
a second current MOS having a source terminal coupled to the power line, a drain terminal coupled to the first end of the temperature-sensitive factor-eliminating resistor;
wherein:
the gate terminal of the first current MOS is connected with the gate terminal of the second current MOS;
the output terminal of the first operational amplifier is coupled to the gate terminal of the first current MOS and the gate terminal of the second current MOS.
Further, the bandgap core further includes:
a third current MOS having a source terminal coupled to the power line, a gate terminal coupled to the gate terminal of the first current MOS, and a gate terminal of the second current MOS; and
a third resistor for grounding the drain terminal of the third current MOS;
the connection terminal between the drain terminal of the third current MOS and the third resistor is coupled to the output terminal of the bandgap circuit. The design can smoothly generate the band gap voltage.
Further, the bandgap core further includes:
a second operational amplifier having a negative input terminal coupled to the emitter terminal of the first bipolar transistor;
a fourth resistor for grounding the positive input terminal of the second operational amplifier;
a fourth current MOS having a source terminal coupled to the power line, a gate terminal coupled to the output terminal of the second operational amplifier, and a drain terminal grounded through the fourth resistor; and
a fifth current MOS having a source terminal coupled to the power line, a gate terminal coupled to the gate terminal of the fourth current MOS, and a drain terminal grounded through the third resistor. The design of the first operational amplifier and the second operational amplifier may be adapted to, for example, a high voltage power supply line design.
Further, the bias voltage of the power supply line is 1.5V. The invention is therefore applicable to high voltage designs.
The band gap circuit with the self-adaptive starting design comprises: a bandgap core using a pair of bipolar transistors to eliminate temperature sensitive factors, thereby generating a bandgap voltage independent of temperature variation; and a start-up circuit coupling an emitter terminal of a first bipolar transistor of the pair of bipolar transistors to a power supply line to start the bandgap core, wherein the start-up circuit includes a reference bipolar transistor providing a threshold voltage as a reference for disconnecting the power supply line from the emitter terminal of the first bipolar transistor. The mode of the invention can make the operation time window of the band gap circuit more wide, make the required band gap voltage more stably generated and be easier to control.
Drawings
Fig. 1 is a block diagram depicting a bandgap circuit 100 in accordance with an exemplary embodiment of the invention;
FIG. 2 depicts a bandgap circuit 200 having a low voltage bandgap core (low-voltage bandgap core) 202 in accordance with an exemplary embodiment of the invention; and
fig. 3 depicts a bandgap circuit 300 having a high voltage bandgap core (high-voltage bandgap core) 302 in accordance with an exemplary embodiment of the invention.
Detailed Description
In the following detailed description of the embodiments of the present invention, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice them, and it is to be understood that other embodiments may be utilized and that mechanical, structural and procedural changes may be made without departing from the spirit and scope of the present invention. The invention relates to a method for manufacturing a semiconductor device. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of embodiments of the present invention is defined only by the appended claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. In the practice of the present invention, the dimensions and relative dimensions do not correspond to actual dimensions.
It will be understood that, although the terms "first," "second," "third," "primary," "secondary," etc. may be used herein to describe various components, elements, regions, layers and/or sections, these components, elements, regions, these layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first or primary component, region, layer or section discussed below could be termed a second or secondary component, region, layer or section without departing from the teachings of the present inventive concept.
Further, spatially relative terms such as "below," "under," "above," "over," and the like may be used herein for ease of description to describe one component or feature's relationship thereto. Another component or feature as shown. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a "layer" is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
The terms "about", "approximately" and "approximately" generally mean within a range of ±20% of a specified value, or ±10% of the specified value, or ±5% of the specified value, or ±3% of the specified value, or ±2% of the specified value, or ±1% of the specified value, or ±0.5% of the specified value. The prescribed value of the present invention is an approximation. When not specifically described, the stated values include the meaning of "about," approximately, "and" about. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular terms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concepts. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It will be understood that when an "element" or "layer" is referred to as being "on," "connected to," "coupled to" or "adjacent to" another element or layer, it can be directly on, connected to, coupled to or adjacent to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to," or "directly adjacent to" another element or layer, there are no intervening elements or layers present.
Note that: (i) The same features will be denoted by the same reference numerals throughout the figures and not necessarily described in detail in each of the figures in which they appear, and (ii) a series of figures may show different aspects of a single item, each of which is associated with various reference labels that may appear in the entire sequence or may appear only in selected figures of the sequence.
Fig. 1 is a block diagram depicting a bandgap circuit 100 according to an exemplary embodiment of the invention.
Bandgap circuit 100 includes a bandgap core 102 and a start-up circuit 104. Bandgap core 102 uses paired (paired) bipolar transistors (bipolar transistor, BJTs) to eliminate temperature-sensitive factors (factors) and thereby generate a bandgap voltage (bandgap voltage) Vbg independent of temperature variations. The start-up circuit 104 couples an emitter (emitter) terminal of a first BJT of a pair of BJTs of the bandgap core 102 to the power supply line to start up the bandgap core 102. In particular, the start-up circuit 104 includes a reference BJT that provides a threshold voltage (threshold voltage) as a reference (voltage) that disconnects the power line from the emitter terminal of the first BJT.
The threshold voltage of the reference BJT within the start-up circuit 104 may truly reflect the turn-on threshold (turn-on threshold) of the first BJT of the bandgap core 102. Thus, the start-up circuit 104 does not prematurely disconnect the coupling from the power supply line to the emitter terminal of the first BJT of the bandgap core 102. The emitter terminal of the first BJT of band gap core 102 remains coupled to the power supply line until truly conductive. The bandgap circuit 100 does not get trapped in dead lock regions. The bandgap circuit 100 shown in fig. 1 according to the embodiment of the present invention may be implemented by the bandgap circuit 200 shown in fig. 2 or by the bandgap circuit 300 shown in fig. 3.
In the conventional art, the start-up circuit uses the threshold voltage of the inverter as a reference (voltage) to disconnect the power supply line from the emitter terminal of the first BJT of the bandgap core. A conventional start-up circuit may prematurely disconnect the power supply line from the emitter terminal of the first BJT of the bandgap core. Conventional bandgap circuits may be trapped in dead-lock areas.
Fig. 2 depicts a bandgap circuit 200 according to an exemplary embodiment of the invention.
Bandgap circuit 200 includes a bandgap core 202 and a start-up circuit 204. Bandgap core 202 uses the paired BJTs Ql and Q2 to cancel the temperature-sensitive factor (e.g., by the voltage difference of temperature-sensitive factor cancellation resistor Rte) to produce bandgap voltage Vbg independent of temperature variation. The start-up circuit 204 couples the emitter terminal of the first BJT Q1 to the power supply line AVDD12 to start the bandgap core 202. The start-up circuit 204 includes a reference BJT Q0, the reference BJT Q0 providing a threshold voltage Vbe0 as a reference (voltage) for disconnecting the power line AVDD12 from the emitter terminal of the first BJT Q1. As shown, the reference BJT Q0 is in diode-connected form, just like the first BJT Q1. The base and collector of reference BJT Q0 are directly electrically connected and are both connected to ground; the base electrode and the collector electrode of the first BJT Q1 are directly and electrically connected, and are both connected to the ground; the base and collector of the second BJT Q2 are directly electrically connected and are both connected to ground.
The start-up circuit 204 also has a comparator Comp having a positive input terminal '+', which receives a sense voltage Vse related to the sense current Ise sensed from the bandgap core 202, a negative input terminal "-" coupled to the emitter terminal of the reference BJT Q0 to receive the base-emitter voltage Vbe0 of the reference BJT Q0, and an output terminal outputting a control signal CS to control whether the emitter terminal of the first BJT Q1 is connected to the power supply line AVDD12.
The start-up circuit 204 further includes a start-up control MOS (metal-oxide-semiconductor field-effect) transistor Msu, the start-up control MOS transistor Msu is PMOS, a gate terminal of the start-up control MOS transistor Msu is coupled to an output terminal of the comparator Comp and is controlled by the control signal CS, a source terminal of the start-up control MOS transistor Msu is coupled to the power supply line AVDD12 (e.g., by the enable MOS Me2 being coupled to the power supply line AVDD 12), and a drain terminal of the start-up control MOS transistor Msu is coupled to an emitter terminal of the first BJT Q1.
The start-up circuit 204 also has a first resistor R1, the first resistor R1 coupling the emitter terminal of the reference BJT Q0 to the power supply line AVDD12. The start-up circuit 204 further has a second resistor R2, and the second resistor R2 is coupled between the positive input terminal "+" of the comparator Comp and ground (ground), and the sense current Ise flows through the second resistor R2 to generate the sense voltage Vse. The start-up circuit 204 also has a current mirror MOS Mcm that mirrors the current of the bandgap core 202 to generate a sense current Ise that flows through the second resistor R2.
The start-up circuit 204 also has optional enable (enable) MOSs Me1 and Me2. The first enable MOS Me1 is coupled between the power line AVDD12 and the first resistor R1 and is controlled by an enable signal Enb of the start-up circuit 204. The second enable MOS Me2 is coupled between the power line AVDD12 and the source terminal of the start control MOS transistor Msu and is controlled by the enable signal Enb of the start circuit 204.
In such a circuit architecture, the enabled start-up circuit 204 consumes power to the bandgap core 202 until the bandgap core 202 actually starts up. When the sensed voltage Vse is greater than the base-emitter voltage (Vbe 0) of the BJT, this means that the first BJT Q1 within the bandgap core 202 is actually operating and the bandgap core 202 successfully generates the bandgap voltage Vbg. It is ensured that the start-up circuit 204 does not prematurely disconnect the power line AVDD12 from the emitter terminal of the first BJT Q1. In one embodiment, band gap core 202 successfully generates a voltage of band gap voltage Vbg that is not equal to zero, e.g., 0.6V or other values, and embodiments of the present invention are not particularly limited.
The low voltage design shown in fig. 2, where the power line AVDD12 is biased at 1.2V, the bandgap core 202 employs a single (single) Op-amp (operational amplifier) Op. The bandgap core 202 uses two voltage dividers (voltage divider) to shift the signal to an appropriate level (level) to input a single operational amplifier Op of a low voltage design. The first voltage divider has a first voltage dividing resistor Rd1 coupled between the emitter terminal of the first BJT Q1 and the negative input terminal "-" of the single operational amplifier Op and a second voltage dividing resistor Rd2 coupled between the negative input terminal "-" of the single operational amplifier Op and ground (ground). The second voltage divider has a third voltage dividing resistor Rd3 coupled between the first end (end) of the temperature sensitive factor eliminating resistor Rte and the positive input terminal "+" of the single operational amplifier Op, and a fourth voltage dividing resistor Rd4 coupled between the positive input terminal "+" of the single operational amplifier Op and ground.
The bandgap core 202 also has a first current MOS Mc1 and a second current MOS Mc2. The source terminal of the first current MOS Mc1 is coupled to the power supply line AVDD12, and the drain terminal of the first current MOS Mc1 is coupled to a connection terminal between the emitter terminal of the first BJT Q1 and the first voltage dividing resistor Rd 1. The source of the second current MOS Mc2 is coupled to the power line AVDD12, and the drain thereof is coupled to the connection terminal between the first end of the temperature-sensitive factor eliminating resistor Rte and the third voltage dividing resistor Rd 3. The gate terminal of the first current MOS Mc1 is connected to the gate terminal of the second current MOS Mc2. The output terminal of the single operational amplifier Op is coupled to the gate terminal of the first current MOS Mc1 and the gate terminal of the second current MOS Mc2. The first end of the temperature-sensitive factor eliminating resistor Rte is connected to the third voltage dividing resistor Rd3 and also to the drain of the second current MOS Mc2. The second terminal of the temperature-sensitive factor-eliminating resistor Rte is connected to the emitter of the second BJT Q2.
The bandgap core 202 also has a third current MOS Mc3 and a third resistor R3. The third current MOS Mc3 has a source terminal coupled to the power supply line AVDD12 and a gate terminal coupled to the gate terminals of the first current MOS Mc1 and the second current MOS Mc2. The third resistor R3 couples the drain terminal of the third current MOS Mc3 to ground. The connection terminal between the drain terminal of the third current MOS Mc3 and the third resistor R3 is coupled to the output terminal (Vbg) of the bandgap circuit 200.
When the bandgap core 202 is not yet turned on, the enabled start-up circuit 204 cannot sense any current (Ise is 0), and the sensed voltage Vse is lower than the base-emitter voltage Vbe0 of the reference BJT Q0, the comparator Comp outputs a low-level control signal CS to turn on the start-up control MOS transistor Msu, thereby forcing the power supply from the power line AVDD12 into the bandgap core 202. The voltage level at the negative input terminal "-" of the single operational amplifier Op rises, so that the current MOS Is pulled low and band gap core 202 begins to operate. The sense voltage Vse increases. When the sense voltage Vse is greater than the BJT threshold voltage (Vbe 0), it means that the emitter voltage of the first BJT Q1 is sufficiently large to turn on the first BJT Q1. The comparator Comp disconnects the start-up circuit 204 from the bandgap core 202. In contrast to conventional start-up circuits without reference to BJT Q0, start-up circuit 204 does not disconnect power line AVDD12 from bandgap core 202 until the emitter voltage of first BJT Q1 is indeed greater than the threshold voltage of the BJT and first BJT Q1 is on. Based on the reference BJT Q0, the start-up circuit 204 adapts to various PVT (Process, voltage, temperature) angles (corner). The mode of the embodiment of the invention can lead the band gap electricThe circuit has a more generous operating time window, which allows a more stable generation of the required bandgap voltage Vbg (e.g. a non-zero voltage) and is easier to control. The mode of the embodiment of the invention has wider applicable time window and wider applicable power supply voltage range, so the mode can have self-adaptive starting design, and the band gap circuit can adapt to various PVT angles, and has wider applicability and stronger universality.
Fig. 3 depicts a bandgap circuit 300 according to another exemplary embodiment of the invention. Bandgap circuit 300 includes a bandgap core 302 and a start-up circuit 304. The start-up circuit 304 has the same structure as the start-up circuit 204 of fig. 2. In contrast to fig. 2, bandgap circuit 300 is a high voltage design. The power line AVDD15 is biased at 1.5V. The bandgap core 302 uses two cascaded (clamped) operational amplifiers Op1 and Op2. In one embodiment, band gap core 302 successfully generates a voltage of band gap voltage Vbg that is not equal to zero, e.g., 0.6V or other values, and embodiments of the present invention are not particularly limited.
The negative input terminal "-" of the first operational amplifier Op1 is coupled to the emitter terminal of the first BJT Q1, and the positive input terminal "+" of the first operational amplifier Op1 is coupled to the first end of the temperature-sensitive factor eliminating resistor Rte. The bandgap core 302 also has a first current MOS Mc1 and a second current MOS Mc2. The first current MOS Mc1 has a source terminal coupled to the power supply line AVDD15 and a drain terminal coupled to the emitter terminal of the first BJT Q1. The source terminal of the second current MOS Mc2 is coupled to the power line AVDD15, and the drain terminal of the second current MOS Mc2 is coupled to the first end of the temperature-sensitive factor eliminating resistor Rte. The gate terminal of the first current MOS Mc1 is connected to the gate terminal of the second current MOS Mc2. The output terminal of the first operational amplifier Op1 is coupled to the gate terminals of the first current MOS Mc1 and the second current MOS Mc2. The first end of the temperature-sensitive factor eliminating resistor Rte is connected to the positive input terminal "+" of the first operational amplifier Op1 and is also connected to the drain of the second current MOS Mc2. The second terminal of the temperature-sensitive factor-eliminating resistor Rte is connected to the emitter of the second BJT Q2.
The second operational amplifier Op2 has a negative input terminal "-" coupled to the emitter terminal of the first BJT Ql. The positive input terminal "+" of the second operational amplifier Op2 is grounded through the fourth resistor R4. The bandgap core 302 also has a fourth current MOS Mc4 and a fifth current MOS Mc5. The fourth current MOS Mc4 has a source terminal coupled to the power supply line AVDD15, a gate terminal coupled to the output terminal of the second operational amplifier Op2, and a drain terminal coupled to ground through the fourth resistor R4. The fifth current MOS Mc5 has a source terminal coupled to the power supply line AVDD15, a gate terminal coupled to the gate terminal of the fourth current MOS Mc4, and a drain terminal coupled to ground through the third resistor R3.
For such a high voltage bandgap core 302, the proposed start-up circuit 304 still adapts to the BJT threshold of the first BJT Q1 of the bandgap core 302. The mode of the embodiment of the invention can make the operation time window of the band gap circuit more wide, make the required band gap voltage Vbg (for example, non-zero voltage) more stably generated and be easier to control. The mode of the embodiment of the invention has wider applicable time window and wider applicable power supply voltage range, so the mode can have self-adaptive starting design, and the band gap circuit can adapt to various PVT angles, and has wider applicability and stronger universality.
Any start-up circuit with a reference BJT Q0 should be considered within the scope of the present invention. The bandgap core driven by the proposed start-up circuit can be varied in many ways.
Those skilled in the art will readily observe that numerous modifications and alterations of the apparatus and method may be made while maintaining the teachings of the present invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims (18)
1. A bandgap circuit having an adaptive start-up design, comprising:
a bandgap core using a pair of bipolar transistors to eliminate temperature sensitive factors, thereby generating a bandgap voltage independent of temperature variation; and
a start-up circuit coupling an emitter terminal of a first bipolar transistor of the pair of bipolar transistors to a power supply line to start up the bandgap core,
wherein the start-up circuit comprises a reference bipolar transistor providing a threshold voltage as a reference for disconnecting the power supply line from the emitter terminal of the first bipolar transistor.
2. The bandgap circuit with adaptive start-up design of claim 1, wherein:
the reference bipolar transistor is in the form of a diode connection, identical to the first bipolar transistor.
3. The bandgap circuit with adaptive start-up design of claim 2, further comprising:
a comparator having a positive input terminal receiving a sense voltage related to a sense current sensed from the bandgap core, a negative input terminal coupled to an emitter terminal of the reference bipolar transistor, and an output terminal outputting a control signal to connect or disconnect the emitter terminal of the first bipolar transistor to or from the power supply line.
4. A bandgap circuit with adaptive start-up design as claimed in claim 3, further comprising:
a start-up control MOS transistor has a gate terminal coupled to the output terminal of the comparator, a source terminal coupled to the power supply line, and a drain terminal coupled to the emitter terminal of the first bipolar transistor.
5. The bandgap circuit with adaptive start-up design of claim 4, further comprising:
a first resistor coupling an emitter terminal of the reference bipolar transistor to the power line,
wherein a connection terminal between the first resistor and the reference bipolar transistor is coupled to a negative input terminal of the comparator.
6. The bandgap circuit with adaptive start-up design of claim 5, further comprising:
and a second resistor coupled between the positive input terminal of the comparator and ground, through which the sensing current flows.
7. The bandgap circuit with adaptive start-up design of claim 6, further comprising:
a current mirror MOS mirroring the current of the bandgap core to generate the sensing current flowing through the second resistor.
8. The bandgap circuit with adaptive start-up design of claim 7, further comprising:
a first enable MOS coupled between the power line and the first resistor and controlled by an enable signal of the start circuit; and
and a second enabling MOS coupled between the power line and the source terminal of the start control MOS transistor and controlled by the enabling signal of the start circuit.
9. The bandgap circuit with adaptive start-up design of claim 1, wherein said bandgap core further comprises:
a second bipolar transistor in the form of a diode connection and paired with the first bipolar transistor; and
a temperature-sensitive factor-eliminating resistor, a first terminal of the temperature-sensitive factor-eliminating resistor being biased according to a base-emitter voltage of the first bipolar transistor, and a second terminal of the temperature-sensitive factor-eliminating resistor being biased according to a base-emitter voltage of the second bipolar transistor.
10. The bandgap circuit with adaptive start-up design of claim 9, wherein said bandgap core further comprises:
a single operational amplifier;
a first voltage divider having a first voltage dividing resistor coupled between an emitter terminal of the first bipolar transistor and a negative input terminal of the single operational amplifier, and a second voltage dividing resistor coupled between the negative input terminal of the single operational amplifier and ground;
the second voltage divider is provided with a third voltage dividing resistor coupled between the first end of the temperature sensitive factor eliminating resistor and the positive input terminal of the single operational amplifier, and a fourth voltage dividing resistor coupled between the positive input terminal of the single operational amplifier and ground.
11. The bandgap circuit with adaptive start-up design of claim 10, wherein said bandgap core further comprises:
a first current MOS having a source terminal coupled to the power supply line, a drain terminal coupled to a connection terminal between the emitter terminal of the first bipolar transistor and the first voltage dividing resistor; and
a second current MOS having a source terminal coupled to the power line, a drain terminal coupled to the first end of the temperature-sensitive factor elimination resistor and the connection terminal of the third voltage dividing resistor;
wherein:
the gate terminal of the first current MOS is connected with the gate terminal of the second current MOS; and
the output terminal of the single operational amplifier is coupled to the gate terminal of the first current MOS and the gate terminal of the second current MOS.
12. The bandgap circuit with adaptive start-up design of claim 11, wherein said bandgap core further comprises:
a third current MOS having a source terminal coupled to the power line, a gate terminal coupled to the gate terminal of the first current MOS, and a gate terminal of the second current MOS; and
a third resistor for grounding the drain terminal of the third current MOS;
the connection terminal between the drain terminal of the third current MOS and the third resistor is coupled to the output terminal of the bandgap circuit.
13. The bandgap circuit with adaptive start-up design of claim 12, wherein said power supply line bias voltage is 1.2V.
14. The bandgap circuit with adaptive start-up design of claim 9, wherein said bandgap core further comprises:
a first operational amplifier having a negative input terminal coupled to the emitter terminal of the first bipolar transistor and a positive input terminal coupled to the first end of the temperature-sensitive factor-eliminating resistor.
15. The bandgap circuit with adaptive start-up design of claim 14, wherein said bandgap core further comprises:
a first current MOS having a source terminal coupled to the power supply line, a drain terminal coupled to the emitter terminal of the first bipolar transistor; and
a second current MOS having a source terminal coupled to the power line, a drain terminal coupled to the first end of the temperature-sensitive factor-eliminating resistor;
wherein:
the gate terminal of the first current MOS is connected with the gate terminal of the second current MOS;
the output terminal of the first operational amplifier is coupled to the gate terminal of the first current MOS and the gate terminal of the second current MOS.
16. The bandgap circuit with adaptive start-up design of claim 15, wherein said bandgap core further comprises:
a third current MOS having a source terminal coupled to the power line, a gate terminal coupled to the gate terminal of the first current MOS, and a gate terminal of the second current MOS; and
a third resistor for grounding the drain terminal of the third current MOS;
the connection terminal between the drain terminal of the third current MOS and the third resistor is coupled to the output terminal of the bandgap circuit.
17. The bandgap circuit with adaptive start-up design of claim 16, wherein said bandgap core further comprises:
a second operational amplifier having a negative input terminal coupled to the emitter terminal of the first bipolar transistor;
a fourth resistor for grounding the positive input terminal of the second operational amplifier;
a fourth current MOS having a source terminal coupled to the power line, a gate terminal coupled to the output terminal of the second operational amplifier, and a drain terminal grounded through the fourth resistor; and
a fifth current MOS having a source terminal coupled to the power line, a gate terminal coupled to the gate terminal of the fourth current MOS, and a drain terminal grounded through the third resistor.
18. The bandgap circuit with adaptive start-up design of claim 17, wherein said power supply line bias voltage is 1.5V.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US63/367,655 | 2022-07-05 | ||
| US18/318,866 US20240012440A1 (en) | 2022-07-05 | 2023-05-17 | Bandgap circuit with adaptive start-up design |
| US18/318,866 | 2023-05-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117348655A true CN117348655A (en) | 2024-01-05 |
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ID=89363859
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310797435.2A Pending CN117348655A (en) | 2022-07-05 | 2023-06-30 | Bandgap circuit with adaptive start-up design |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117348655A (en) |
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2023
- 2023-06-30 CN CN202310797435.2A patent/CN117348655A/en active Pending
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