CN117348655A - Bandgap circuit with adaptive startup design - Google Patents

Abstract

The invention discloses a bandgap circuit with an adaptive start-up design, which includes: a bandgap core, which uses a pair of bipolar transistors to eliminate temperature-sensitive factors, thereby generating a bandgap voltage that is independent of temperature changes; and a start-up circuit, which An emitter terminal of a first bipolar transistor in a pair of bipolar transistors is coupled to the power line to activate the bandgap core, wherein the activation circuit includes a reference bipolar transistor that provides a threshold voltage as a A reference for disconnecting the power line from the emitter terminal of the first bipolar transistor. The above-described method of the present invention can make the operation time window of the bandgap circuit more generous, generate the required bandgap voltage more stably, and make it easier to control.

Description

Bandgap circuit with adaptive startup design

Technical field

The present invention relates to the field of circuit technology, and in particular, to a bandgap circuit with adaptive startup design.

Background technique

In integrated circuits, a bandgap voltage reference is needed, which is a temperature independent voltage reference. Bandgap circuits produce a constant voltage regardless of changes in power supply, temperature changes, or circuit loading of the device.

The start-up of bandgap cores is an important issue in this field.

Contents of the invention

In view of this, the present invention provides a bandgap circuit with an adaptive startup design to solve the above problems.

According to a first aspect of the present invention, a bandgap circuit with adaptive startup design is disclosed, including:

a bandgap core, which uses pairs of bipolar transistors to eliminate temperature sensitivity factors, resulting in a bandgap voltage that is independent of temperature changes; and

activating a circuit that couples an emitter terminal of a first bipolar transistor of the pair of bipolar transistors to a power line to activate the bandgap core,

Wherein, the startup circuit includes a reference bipolar transistor that provides a threshold voltage as a reference for disconnecting the power line from the emitter terminal of the first bipolar transistor.

Further, the reference bipolar transistor is in a diode connection form, which is the same as the first bipolar transistor. The smoothly generated threshold voltage is provided to the comparator for more accurately determining whether the emitter terminal of the first bipolar transistor is disconnected or connected to the power line.

Further, the startup circuit further includes: a comparator having a positive input terminal receiving a sensing voltage related to the sensing current sensed from the bandgap core, and an emitter terminal coupled to the reference bipolar transistor. a negative input terminal, and an output terminal that outputs a control signal to connect the emitter terminal of the first bipolar transistor to the power line or to disconnect the emitter terminal of the first bipolar transistor from the power line. The use of a comparator can make it more consistent with design requirements to determine whether the emitter terminal of the first bipolar transistor is disconnected or connected to the power line.

Further, the startup circuit further includes: a startup control MOS transistor having a gate terminal coupled to the output terminal of the comparator, a source terminal coupled to the power line, and a first bipolar transistor. the emitter terminal and the drain terminal. In this way, the output of the comparator can be used to control the activation of the MOS transistor, thereby determining that the emitter terminal of the first bipolar transistor is disconnected or connected to the power line.

Further, the startup circuit also includes: a first resistor coupling the emitter terminal of the reference bipolar transistor to the power line,

The connection terminal between the first resistor and the reference bipolar transistor is coupled to the negative input terminal of the comparator. This creates a threshold voltage.

Further, the startup circuit further includes: a second resistor coupled between the positive input terminal of the comparator and ground, and the sensing current flows through the second resistor. to generate sensing voltage.

Further, the startup circuit further includes: a current mirror MOS that mirrors the current of the bandgap core to generate the sensing current flowing through the second resistor. Thereby the sensing voltage is generated smoothly.

Further, the startup circuit also includes: a first enable MOS, coupled between the power line and the first resistor, and controlled by the enable signal of the startup circuit; and

The second enabling MOS is coupled between the power line and the source terminal of the startup control MOS transistor, and is controlled by the enable signal of the startup circuit. Thereby controlling the generation of threshold voltage and sensing voltage.

Further, the band gap core also includes: a second bipolar transistor in the form of a diode connection and paired with the first bipolar transistor; and

a temperature sensitivity cancellation resistor having a first terminal biased according to the base-emitter voltage of the first bipolar transistor and a second terminal biased according to the second bipolar transistor base-emitter voltage bias of a transistor.

Further, the bandgap core also includes:

Single operational amplifier;

A first voltage divider having a first voltage dividing resistor coupled between the emitter terminal of the first bipolar transistor and the negative input terminal of the single operational amplifier, and a first voltage dividing resistor coupled between the negative input terminal of the single operational amplifier a second voltage dividing resistor between the terminals and ground;

The second voltage divider has a third voltage dividing resistor coupled between the first terminal of the temperature sensitivity elimination resistor and the positive input terminal of the single operational amplifier, and a third voltage dividing resistor coupled between the positive input terminal of the single operational amplifier. Fourth voltage divider resistor between terminals and ground. This allows the single op amp to be adapted to, for example, low voltage power line designs.

Further, the bandgap core also includes:

The first current MOS has a source terminal coupled to the power line, a drain terminal coupled to the connection terminal between the emitter terminal of the first bipolar transistor and the first voltage dividing resistor; and

The second current MOS has a source terminal coupled to the power line and a drain terminal coupled to the connection terminal of the first end of the temperature-sensitive factor elimination resistor and the third voltage dividing resistor;

in:

The gate terminal of the first current MOS is connected to the gate terminal of the second current MOS; and

The output terminal of the single operational amplifier is coupled to the gate terminal of the first current MOS and the gate terminal of the second current MOS.

Further, the bandgap core also includes:

The third current MOS has a source terminal coupled to the power line, a gate terminal coupled to the gate terminal of the first current MOS and a gate terminal of the second current MOS; and

The third resistor connects the drain terminal of the third current MOS to ground;

Wherein, the connection terminal between the drain terminal of the third current MOS and the third resistor is coupled to the output terminal of the bandgap circuit. The above design can successfully generate the band gap voltage.

Further, the bias voltage of the power line is 1.2V. The invention is therefore suitable for low voltage designs.

Further, the bandgap core also includes:

The first operational amplifier has a negative input terminal coupled to the emitter terminal of the first bipolar transistor, and a positive input terminal coupled to the first terminal of the temperature sensitivity elimination resistor.

Further, the bandgap core also includes:

A first current MOS having a source terminal coupled to the power line, a drain terminal coupled to the emitter terminal of the first bipolar transistor; and

The second current MOS has a source terminal coupled to the power line and a drain terminal coupled to the first end of the temperature-sensitive factor elimination resistor;

in:

The gate terminal of the first current MOS is connected to the gate terminal of the second current MOS;

The output terminal of the first operational amplifier is coupled to the gate terminal of the first current MOS and the gate terminal of the second current MOS.

Further, the bandgap core also includes:

The third current MOS has a source terminal coupled to the power line, a gate terminal coupled to the gate terminal of the first current MOS and a gate terminal of the second current MOS; and

The third resistor connects the drain terminal of the third current MOS to ground;

Wherein, the connection terminal between the drain terminal of the third current MOS and the third resistor is coupled to the output terminal of the bandgap circuit. The above design can successfully generate the band gap voltage.

Further, the bandgap core also includes:

a second operational amplifier having a negative input terminal coupled to the emitter terminal of the first bipolar transistor;

a fourth resistor to connect the positive input terminal of the second operational amplifier to ground;

The fourth current MOS has a source terminal coupled to the power line, a gate terminal coupled to the output terminal of the second operational amplifier, and a drain terminal connected to ground through the fourth resistor; and

The fifth current MOS has a source terminal coupled to the power line, a gate terminal coupled to the gate terminal of the fourth current MOS, and a drain terminal connected to ground through the third resistor. The design of the first operational amplifier and the second operational amplifier may be adapted to, for example, high voltage power line designs.

Further, the bias voltage of the power line is 1.5V. The invention is therefore suitable for high voltage designs.

The bandgap circuit with adaptive start-up design of the present invention includes: a bandgap core, which uses pairs of bipolar transistors to eliminate temperature-sensitive factors, thereby generating a bandgap voltage that is independent of temperature changes; and a start-up circuit that converts this into An emitter terminal of a first of the pair of bipolar transistors is coupled to the power line to activate the bandgap core, wherein the activation circuit includes a reference bipolar transistor that provides a threshold voltage as the The power line is a reference disconnected from the emitter terminal of the first bipolar transistor. The above-described method of the present invention can make the operation time window of the bandgap circuit more generous, generate the required bandgap voltage more stably, and make it easier to control.

Description of drawings

1 is a block diagram depicting a bandgap circuit 100 according to an exemplary embodiment of the present invention;

2 depicts a bandgap circuit 200 having a low-voltage bandgap core 202 in accordance with an exemplary embodiment of the present invention; and

Figure 3 depicts a bandgap circuit 300 with a high-voltage bandgap core 302 in accordance with an exemplary embodiment of the present invention.

Detailed ways

In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form a part hereof and which illustrate by way of illustration certain preferred embodiments in which the invention may be practiced. . These embodiments are described in sufficient detail to enable those skilled in the art to practice them, and it is to be understood that other embodiments may be utilized and mechanical, structural and structural changes may be made without departing from the spirit and scope of the invention. and procedural changes. this invention. Accordingly, the following detailed description is not to be construed as limiting, and the scope of embodiments of the invention is defined only by the appended claims. The drawings described are illustrative only and not restrictive. In the drawings, the dimensions of some elements may be exaggerated and not drawn to scale for illustrative purposes. In the practice of the invention, dimensions and relative dimensions do not correspond to actual dimensions.

It will be understood that, although the terms "first," "second," "third," "primary," "secondary," etc. may be used herein to describe various components, components, regions, layers and/or sections , but these components, components, regions, layers and/or portions shall not be limited by these terms. These terms are only used to distinguish one component, component, region, layer or section from another region, layer or section. Thus, a first or primary component, component, region, layer or section discussed below could be termed a secondary or secondary component, component, region, layer or section without departing from the teachings of the inventive concept.

In addition, for convenience of description, terms such as “below”, “under”, “below”, “above”, “between” may be used herein. Spatially relative terms such as "on" to describe the relationship of a component or feature to it. Another component or feature as shown in a figure. In addition to the orientation depicted in the figures, the spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a "layer" is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

The terms "about", "approximately" and "approximately" generally mean ±20% of the stated value, or ±10% of the stated value, or ±5% of the stated value, or ±3% of the stated value , or within the range of ±2% of the specified value, or ±1% of the specified value, or ±0.5% of the specified value. The values specified in this invention are approximate. When not specifically described, stated values include the meanings of "about," "approximately," and "approximately." The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular terms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the inventive concept. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It will be understood that when a "component" or "layer" is referred to as being "on," "connected to," "coupled to" or "adjacent" another component or layer, it can be directly on the other component or layer Intermediate components or layers may be present on, connected to, coupled to, or adjacent thereto. In contrast, when a component is referred to as being "directly on," "directly connected to," "directly coupled to" or "immediately adjacent" another component or layer, there are no intervening components or layers present.

Note: (i) like features will be designated by the same reference numerals throughout the Figures and will not necessarily be described in detail in every Figure in which they appear, and (ii) a series of Figures may show a single item Each aspect is associated with various reference labels that may appear throughout the sequence, or may appear only in selected plots of the sequence.

FIG. 1 is a block diagram depicting a bandgap circuit 100 according to an exemplary embodiment of the present invention.

The bandgap circuit 100 includes a bandgap core 102 and a start-up circuit 104 . The bandgap core 102 uses paired bipolar transistors (BJTs) to eliminate temperature sensitivity factors, thereby generating a bandgap voltage Vbg that is independent of temperature changes. Startup circuit 104 couples the emitter terminal of a first BJT in a pair of BJTs of bandgap core 102 to a power line to turn on bandgap core 102 . In particular, the startup circuit 104 includes a reference BJT that provides a threshold voltage as a reference (voltage) for disconnecting the power line from the emitter terminal of the first BJT.

The threshold voltage of the reference BJT within the startup circuit 104 may truly reflect the turn-on threshold of the first BJT of the bandgap core 102 . Therefore, the startup circuit 104 does not prematurely decouple the power line from the emitter terminal of the first BJT of the bandgap core 102 . The emitter terminal of the first BJT of bandgap core 102 remains coupled to the power line until true conduction. The bandgap circuit 100 will not fall into a deadlock region. The bandgap circuit 100 shown in FIG. 1 according to the embodiment of the present invention can be implemented by the bandgap circuit 200 shown in FIG. 2 , or can also be implemented by the bandgap circuit 300 shown in FIG. 3 .

In conventional technology, the startup circuit uses the threshold voltage of the inverter as a reference (voltage) to disconnect the power line from the emitter terminal of the first BJT of the bandgap core. A conventional startup circuit may prematurely disconnect the power line from the emitter terminal of the first BJT of the bandgap core. Traditional bandgap circuits can fall into deadlock regions.

Figure 2 depicts a bandgap circuit 200 according to an exemplary embodiment of the present invention.

Bandgap circuit 200 includes bandgap core 202 and enabling circuit 204 . The bandgap core 202 uses a pair of BJTs Q1 and Q2 to eliminate temperature sensitivity factors (eg, voltage difference cancellation by the temperature sensitivity factor elimination resistor Rte), thereby generating a bandgap voltage Vbg that is independent of temperature changes. Enablement circuit 204 couples the emitter terminal of first BJT Q1 to power line AVDD12 to enable bandgap core 202 . The startup circuit 204 includes a reference BJT Q0 that provides a threshold voltage Vbe0 as a reference (voltage) for disconnecting the power supply line AVDD12 from the emitter terminal of the first BJT Q1. As shown in the figure, the reference BJT Q0 is in diode-connected form, just like the first BJT Q1. The base and collector of the reference BJT Q0 are directly electrically connected, and both are connected to ground; the base and collector of the first BJT Q1 are directly electrically connected, and both are connected to ground; the base and collector of the second BJT Q2 The electrodes are directly electrically connected and are connected to ground.

Start-up circuit 204 also has a comparator Comp having a positive input terminal '+' that receives a sense voltage Vse related to sense current Ise sensed from bandgap core 202, an emitter terminal coupled to reference BJT Q0 to receive a negative input terminal "-" that refers to the base-emitter voltage Vbe0 of the BJT Q0, and output a control signal CS to control whether the emitter terminal of the first BJT Q1 is connected to the output terminal of the power line AVDD12.

The startup circuit 204 also includes a startup control MOS (metal-oxide-semiconductor field-effect) transistor Msu. The startup control MOS transistor Msu is PMOS. The gate terminal of the startup control MOS transistor Msu is coupled to the output terminal of the comparator Comp and is controlled. The signal CS controls, the source terminal of the start-up control MOS transistor Msu is coupled to the power line AVDD12 (for example, by enabling the MOS Me2 to be coupled to the power line AVDD12), and the drain terminal of the start-up control MOS transistor Msu is coupled to the first BJT Q1 emitter terminal.

Startup circuit 204 also has a first resistor R1 coupling the emitter terminal of reference BJT Q0 to power line AVDD12. The startup circuit 204 also has a second resistor R2. The two resistors R2 are coupled between the positive input terminal "+" of the comparator Comp and ground (ground). The sensing current Ise flows through the second resistor R2 to generate the sensing voltage Vse. . The startup circuit 204 also has a current mirror MOS Mcm that mirrors the current of the bandgap core 202 to generate a sensing current Ise flowing through the second resistor R2.

The startup circuit 204 also has optional enable MOS Me1 and Me2. The first enable MOS Me1 is coupled between the power line AVDD12 and the first resistor R1 and is controlled by the enable (or enable) signal Enb of the startup circuit 204 . The second enable MOS Me2 is coupled between the power line AVDD12 and the source terminal of the startup control MOS transistor Msu, and is controlled by the enable signal Enb of the startup circuit 204 .

In such a circuit architecture, the enabled startup circuit 204 consumes power from the bandgap core 202 until the bandgap core 202 actually starts. When the sensed voltage Vse is greater than the base-emitter voltage of the BJT (Vbe0), it means that the first BJT Q1 within the bandgap core 202 is actually working, and the bandgap core 202 successfully generates the bandgap voltage Vbg. Ensure that startup circuit 204 does not prematurely disconnect power line AVDD12 from the emitter terminal of first BJT Q1. In one embodiment, the bandgap core 202 successfully generates a bandgap voltage Vbg that is not equal to zero, such as 0.6V or other values, which is not specifically limited in this embodiment of the present invention.

The low-voltage design shown in Figure 2 has the power line AVDD12 biased at 1.2V, and the bandgap core 202 uses a single operational amplifier Op. The bandgap core 202 uses two voltage dividers to shift the signal to the appropriate level for input to a single operational amplifier Op of a low voltage design. The first voltage divider has a first voltage dividing resistor Rd1 coupled between the emitter terminal of the first BJT Q1 and the negative input terminal "-" of the single operational amplifier Op, and a first voltage dividing resistor Rd1 coupled between the negative input terminal of the single operational amplifier Op. The second voltage dividing resistor Rd2 between "-" and ground (ground). The second voltage divider has a third voltage dividing resistor Rd3 coupled between the first end (end) of the temperature sensitivity factor elimination resistor Rte and the positive input terminal "+" of the single operational amplifier Op, and is coupled to the single operational amplifier Op. The fourth voltage dividing resistor Rd4 between the positive input terminal "+" of the amplifier Op and ground.

The bandgap core 202 also has a first current MOS Mc1 and a second current MOS Mc2. The source terminal of the first current MOS Mc1 is coupled to the power line AVDD12, and the drain terminal of the first current MOS Mc1 is coupled to the connection terminal between the emitter terminal of the first BJT Q1 and the first voltage dividing resistor Rd1. The source of the second current MOS Mc2 is coupled to the power line AVDD12, and its drain is coupled to the connection terminal between the first end of the temperature-sensitive factor elimination resistor Rte and the third voltage dividing resistor Rd3. The gate terminal of the first current MOS Mc1 is connected to the gate terminal of the second current MOS Mc2. The output terminal of the single operational amplifier Op is coupled to the gate terminal of the first current MOS Mc1 and the gate terminal of the second current MOS Mc2. The first end of the temperature sensitivity factor elimination resistor Rte is connected to the third voltage dividing resistor Rd3 and is also connected to the drain of the second current MOS Mc2. The second terminal of the temperature sensitivity elimination resistor Rte is connected to the emitter of the second BJT Q2.

Bandgap core 202 also has a third current MOS Mc3 and a third resistor R3. The third current MOS Mc3 has a source terminal coupled to the power supply line AVDD12 and a gate terminal coupled to the gate terminals of the first and second current MOS Mc1 and MOS Mc2. The third resistor R3 couples the drain terminal of the third current MOS Mc3 to ground. The connection terminal between the drain terminal of the third current MOS Mc3 and the third resistor R3 is coupled to the output terminal (Vbg) of the bandgap circuit 200 .

When the bandgap core 202 is not yet conducting, the enabled start-up circuit 204 cannot sense any current (Ise is 0), and the sensed voltage Vse is lower than the base-emitter voltage Vbe0 of the reference BJT Q0, compare The device Comp outputs a low-level control signal CS to turn on a start-up control MOS transistor Msu, thereby forcing power from the power line AVDD12 into the bandgap core 202 . The voltage level at the negative input terminal "-" of the single operational amplifier Op increases, causing the current MOS The gate is pulled low and the bandgap core 202 begins to operate. The sensing voltage Vse increases. When the sensing voltage Vse is greater than the BJT threshold voltage (Vbe0), it means that the emitter voltage of the first BJT Q1 is large enough to turn on the first BJT Q1. Comparator Comp disconnects enable circuit 204 from bandgap core 202 . Compared with the traditional startup circuit without reference to BJT Q0, the startup circuit 204 will not disconnect the power line AVDD12 from the bandgap core until the emitter voltage of the first BJT Q1 is indeed greater than the threshold voltage of the BJT and the first BJT Q1 is turned on. 202 connection. Based on the reference BJT Q0, the startup circuit 204 adapts to various PVT (Process, Voltage, Temperature) corners. The above-mentioned embodiments of the present invention can make the operation time window of the bandgap circuit more generous, so that the required bandgap voltage Vbg (for example, a non-zero voltage) can be generated more stably, and can be more easily controlled. The method of the embodiment of the present invention has a wider applicable time window and a wider applicable power supply voltage range, so it can have an adaptive startup design, and the bandgap circuit can adapt to various PVT angles, and has wider applicability. More versatile.

Figure 3 depicts a bandgap circuit 300 according to another exemplary embodiment of the present invention. Bandgap circuit 300 includes bandgap core 302 and enabling circuit 304 . The startup circuit 304 has the same structure as the startup circuit 204 of FIG. 2 . Compared to Figure 2, bandgap circuit 300 is a high voltage design. Power line AVDD15 is biased to 1.5V. Bandgap core 302 uses two cascaded operational amplifiers Op1 and Op2. In one embodiment, the bandgap core 302 successfully generates a bandgap voltage Vbg that is not equal to zero, such as 0.6V or other values, which is not specifically limited in the embodiment of the present invention.

The negative input terminal "-" of the first operational amplifier Op1 is coupled to the emitter terminal of the first BJT Q1, and the positive input terminal "+" of the first operational amplifier Op1 is coupled to the first terminal of the temperature sensitivity elimination resistor Rte . The bandgap core 302 also has a first current MOS Mc1 and a second current MOS Mc2. The first current MOS Mc1 has a source terminal coupled to the power supply line AVDD15 and a drain terminal coupled to the emitter terminal of the first BJT Q1. The source terminal of the second current MOS Mc2 is coupled to the power line AVDD15, and the drain terminal of the second current MOS Mc2 is coupled to the first end of the temperature sensitive factor elimination resistor Rte. The gate terminal of the first current MOS Mc1 is connected to the gate terminal of the second current MOS Mc2. The output terminal of the first operational amplifier Op1 is coupled to the gate terminals of the first current MOS Mc1 and the second current MOS Mc2. The first end of the temperature sensitivity elimination resistor Rte is connected to the positive input terminal "+" of the first operational amplifier Op1 and is also connected to the drain of the second current MOS Mc2. The second terminal of the temperature sensitivity elimination resistor Rte is connected to the emitter of the second BJT Q2.

The second operational amplifier Op2 has a negative input terminal "-" coupled to the emitter terminal of the first BJT Q1. The positive input terminal "+" of the second operational amplifier Op2 is connected to ground through the fourth resistor R4. The bandgap core 302 also has a fourth current MOSMc4 and a fifth current MOSMc5. The fourth current MOS Mc4 has a source terminal coupled to the power supply line AVDD15, a gate terminal coupled to the output terminal of the second operational amplifier Op2, and a drain terminal coupled to the ground through the fourth resistor R4. The fifth current MOS Mc5 has a source terminal coupled to the power supply line AVDD15, a gate terminal coupled to the gate terminal of the fourth current MOS Mc4, and a drain terminal coupled to the ground through the third resistor R3.

For such a high voltage bandgap core 302, the proposed startup circuit 304 still adapts to the BJT threshold of the first BJT Q1 of the bandgap core 302. The above-mentioned embodiments of the present invention can make the operation time window of the bandgap circuit more generous, so that the required bandgap voltage Vbg (for example, a non-zero voltage) can be generated more stably, and can be more easily controlled. The method of the embodiment of the present invention has a wider applicable time window and a wider applicable power supply voltage range, so it can have an adaptive startup design, and the bandgap circuit can adapt to various PVT angles, and has wider applicability. More versatile.

Any startup circuit with a reference to BJT Q0 should be considered within the scope of this invention. There can be many variations of the bandgap core driven by the proposed startup circuit.

Those skilled in the art will readily observe that many modifications and variations of the apparatus and methods can be made while maintaining the teachings of the present invention. Accordingly, the foregoing disclosure should be construed as being limited only by the metes and bounds of the appended claims.

Claims (18)

1. A bandgap circuit having an adaptive start-up design, comprising:

a bandgap core using a pair of bipolar transistors to eliminate temperature sensitive factors, thereby generating a bandgap voltage independent of temperature variation; and

a start-up circuit coupling an emitter terminal of a first bipolar transistor of the pair of bipolar transistors to a power supply line to start up the bandgap core,

wherein the start-up circuit comprises a reference bipolar transistor providing a threshold voltage as a reference for disconnecting the power supply line from the emitter terminal of the first bipolar transistor.

2. The bandgap circuit with adaptive start-up design of claim 1, wherein:

the reference bipolar transistor is in the form of a diode connection, identical to the first bipolar transistor.

3. The bandgap circuit with adaptive start-up design of claim 2, further comprising:

a comparator having a positive input terminal receiving a sense voltage related to a sense current sensed from the bandgap core, a negative input terminal coupled to an emitter terminal of the reference bipolar transistor, and an output terminal outputting a control signal to connect or disconnect the emitter terminal of the first bipolar transistor to or from the power supply line.

4. A bandgap circuit with adaptive start-up design as claimed in claim 3, further comprising:

a start-up control MOS transistor has a gate terminal coupled to the output terminal of the comparator, a source terminal coupled to the power supply line, and a drain terminal coupled to the emitter terminal of the first bipolar transistor.

5. The bandgap circuit with adaptive start-up design of claim 4, further comprising:

a first resistor coupling an emitter terminal of the reference bipolar transistor to the power line,

wherein a connection terminal between the first resistor and the reference bipolar transistor is coupled to a negative input terminal of the comparator.

6. The bandgap circuit with adaptive start-up design of claim 5, further comprising:

and a second resistor coupled between the positive input terminal of the comparator and ground, through which the sensing current flows.

7. The bandgap circuit with adaptive start-up design of claim 6, further comprising:

a current mirror MOS mirroring the current of the bandgap core to generate the sensing current flowing through the second resistor.

8. The bandgap circuit with adaptive start-up design of claim 7, further comprising:

a first enable MOS coupled between the power line and the first resistor and controlled by an enable signal of the start circuit; and

and a second enabling MOS coupled between the power line and the source terminal of the start control MOS transistor and controlled by the enabling signal of the start circuit.

9. The bandgap circuit with adaptive start-up design of claim 1, wherein said bandgap core further comprises:

a second bipolar transistor in the form of a diode connection and paired with the first bipolar transistor; and

a temperature-sensitive factor-eliminating resistor, a first terminal of the temperature-sensitive factor-eliminating resistor being biased according to a base-emitter voltage of the first bipolar transistor, and a second terminal of the temperature-sensitive factor-eliminating resistor being biased according to a base-emitter voltage of the second bipolar transistor.

10. The bandgap circuit with adaptive start-up design of claim 9, wherein said bandgap core further comprises:

a single operational amplifier;

a first voltage divider having a first voltage dividing resistor coupled between an emitter terminal of the first bipolar transistor and a negative input terminal of the single operational amplifier, and a second voltage dividing resistor coupled between the negative input terminal of the single operational amplifier and ground;

the second voltage divider is provided with a third voltage dividing resistor coupled between the first end of the temperature sensitive factor eliminating resistor and the positive input terminal of the single operational amplifier, and a fourth voltage dividing resistor coupled between the positive input terminal of the single operational amplifier and ground.

11. The bandgap circuit with adaptive start-up design of claim 10, wherein said bandgap core further comprises:

a first current MOS having a source terminal coupled to the power supply line, a drain terminal coupled to a connection terminal between the emitter terminal of the first bipolar transistor and the first voltage dividing resistor; and

a second current MOS having a source terminal coupled to the power line, a drain terminal coupled to the first end of the temperature-sensitive factor elimination resistor and the connection terminal of the third voltage dividing resistor;

wherein:

the gate terminal of the first current MOS is connected with the gate terminal of the second current MOS; and

the output terminal of the single operational amplifier is coupled to the gate terminal of the first current MOS and the gate terminal of the second current MOS.

12. The bandgap circuit with adaptive start-up design of claim 11, wherein said bandgap core further comprises:

a third current MOS having a source terminal coupled to the power line, a gate terminal coupled to the gate terminal of the first current MOS, and a gate terminal of the second current MOS; and

a third resistor for grounding the drain terminal of the third current MOS;

the connection terminal between the drain terminal of the third current MOS and the third resistor is coupled to the output terminal of the bandgap circuit.

13. The bandgap circuit with adaptive start-up design of claim 12, wherein said power supply line bias voltage is 1.2V.

14. The bandgap circuit with adaptive start-up design of claim 9, wherein said bandgap core further comprises:

a first operational amplifier having a negative input terminal coupled to the emitter terminal of the first bipolar transistor and a positive input terminal coupled to the first end of the temperature-sensitive factor-eliminating resistor.

15. The bandgap circuit with adaptive start-up design of claim 14, wherein said bandgap core further comprises:

a first current MOS having a source terminal coupled to the power supply line, a drain terminal coupled to the emitter terminal of the first bipolar transistor; and

a second current MOS having a source terminal coupled to the power line, a drain terminal coupled to the first end of the temperature-sensitive factor-eliminating resistor;

wherein:

the gate terminal of the first current MOS is connected with the gate terminal of the second current MOS;

the output terminal of the first operational amplifier is coupled to the gate terminal of the first current MOS and the gate terminal of the second current MOS.

16. The bandgap circuit with adaptive start-up design of claim 15, wherein said bandgap core further comprises:

a third current MOS having a source terminal coupled to the power line, a gate terminal coupled to the gate terminal of the first current MOS, and a gate terminal of the second current MOS; and

a third resistor for grounding the drain terminal of the third current MOS;

the connection terminal between the drain terminal of the third current MOS and the third resistor is coupled to the output terminal of the bandgap circuit.

17. The bandgap circuit with adaptive start-up design of claim 16, wherein said bandgap core further comprises:

a second operational amplifier having a negative input terminal coupled to the emitter terminal of the first bipolar transistor;

a fourth resistor for grounding the positive input terminal of the second operational amplifier;

a fourth current MOS having a source terminal coupled to the power line, a gate terminal coupled to the output terminal of the second operational amplifier, and a drain terminal grounded through the fourth resistor; and

a fifth current MOS having a source terminal coupled to the power line, a gate terminal coupled to the gate terminal of the fourth current MOS, and a drain terminal grounded through the third resistor.

18. The bandgap circuit with adaptive start-up design of claim 17, wherein said power supply line bias voltage is 1.5V.