CN117348284A - Array substrate and embedded touch display panel - Google Patents
Array substrate and embedded touch display panel Download PDFInfo
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- CN117348284A CN117348284A CN202311277563.0A CN202311277563A CN117348284A CN 117348284 A CN117348284 A CN 117348284A CN 202311277563 A CN202311277563 A CN 202311277563A CN 117348284 A CN117348284 A CN 117348284A
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- 239000010409 thin film Substances 0.000 claims description 4
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- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/13338—Input devices, e.g. touch panels
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
- G02F1/133509—Filters, e.g. light shielding masks
- G02F1/133512—Light shielding layers, e.g. black matrix
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
- G02F1/133509—Filters, e.g. light shielding masks
- G02F1/133514—Colour filters
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0412—Digitisers structurally integrated in a display
Abstract
The invention discloses an array substrate and an embedded touch display panel, wherein a plurality of scanning lines, a plurality of data lines, a plurality of touch control wirings, a plurality of pixel units and a plurality of common electrode blocks are arranged on the array substrate, the extending direction of the touch control wirings is parallel to the extending direction of the data lines, each common electrode block is electrically connected with the corresponding touch control wiring, a touch control partition gap is arranged between every two adjacent common electrode blocks, the touch control partition gap comprises a longitudinal partition gap arranged between every two adjacent columns of pixel units and a transverse partition gap arranged between every two adjacent rows of pixel units, the touch control wirings adjacent to the longitudinal partition gap are positioned between every two adjacent columns of pixel units and correspond to the longitudinal partition gap, and the data lines adjacent to the longitudinal partition gap penetrate through one column of pixel units electrically connected with the pixel units. The method and the device ensure that the storage capacitance in all pixel units is the same, and the coupling capacitance between all data lines and the common electrode block is the same, so that the display image quality is improved.
Description
Technical Field
The present invention relates to the field of touch displays, and more particularly, to an array substrate and an embedded touch display panel.
Background
The liquid crystal display panel has the advantages of good image quality, small volume, light weight, low driving voltage, low power consumption, no radiation and relatively low manufacturing cost, and is dominant in the field of flat panel display. With rapid development of display technology, touch display panels have been widely accepted and used by people, such as smart phones and tablet computers. The touch display panel combines the touch panel and the liquid crystal display panel into a whole by adopting an embedded touch technology, and the function of the touch panel is embedded into the liquid crystal display panel, so that the liquid crystal display panel has the functions of displaying and sensing touch input.
According to the different arrangement modes of the touch sensing layer In the display panel, the touch display panel is divided into structures such as an externally-hung (Addon Mode), an embedded (In-cell) and an externally-embedded (On-cell). The embedded touch screen integrates the touch function in the display screen, so that the thickness of the whole display can be effectively reduced, the production process is simplified, the product is lighter and thinner, the production cost is lower, and the embedded touch screen is popular.
Currently, for in-cell touch screens, the touch screen structure is generally disposed directly on an array substrate, and some structural components for transmitting display signals are mainly multiplexed into touch electrodes in the array substrate, as shown in fig. 1 and 2, it is relatively common to multiplex a common electrode block 21 into touch electrodes, and then control the common electrode block 21 to transmit a common signal and a touch signal through a touch trace 3. Since the common electrode block 21 is multiplexed as a touch electrode, the common electrode block 21 needs to be divided into a plurality of blocks through the touch partition gap 211. In order to avoid forming a coupling capacitance between the touch trace 3 and the data line 2, the distance between the touch trace 3 and the data line 2 needs to be set wider, and the touch trace 3 is usually disposed in the opening area of the pixel unit SP in the prior art. Meanwhile, in order to avoid the difference in coupling capacitance between the different data lines 2 and the common electrode block 21, the vertical touch partition gap 211 is generally required to be disposed at the touch trace 3, and therefore, the vertical touch partition gap 211 is also required to be disposed at the opening area of the pixel unit SP. However, this causes a difference between the storage capacitance (Cst) at the touch partition gap 211 and the storage capacitance (Cst) in other areas, thereby affecting the display quality. In the prior art, the area of the pixel electrode 22 at the touch partition gap 211 is generally increased, for example, the pixel electrode 22 at the touch partition gap 211 is provided with a compensation electrode 221, so as to compensate the difference between the storage capacitance at the touch partition gap 211 and the storage capacitance of other areas. Although this can compensate for the difference in storage capacitance, the pixel electrode 22 is difficult to design, and the electric field strength of the pixel electrode 22 at the touch-control partition gap 211 is weak, so that the display quality is poor and is detected in the image quality display.
Disclosure of Invention
In order to overcome the defects and shortcomings in the prior art, the invention aims to provide an array substrate and an embedded touch display panel, so as to solve the problem that the display image quality of a touch partition gap is poor due to the partition position of a common electrode block and the touch wiring position in the prior art.
The aim of the invention is achieved by the following technical scheme:
the invention provides an array substrate, which is provided with a plurality of scanning lines, a plurality of data lines, a plurality of touch control wirings, a plurality of pixel units and a plurality of public electrode blocks, wherein the scanning lines and the data lines are mutually insulated and crossed, the extending direction of the touch control wirings is mutually parallel to the extending direction of the data lines, each public electrode block is electrically connected with the corresponding touch control wiring, a touch control partition gap is arranged between every two adjacent public electrode blocks, the touch control partition gap comprises a longitudinal partition gap arranged between every two adjacent columns of pixel units and a transverse partition gap arranged between every two adjacent rows of pixel units, the touch control wirings adjacent to the longitudinal partition gap are positioned between every two adjacent columns of pixel units and correspond to the longitudinal partition gap, and the data lines adjacent to the longitudinal partition gap penetrate through the pixel units electrically connected with the pixel units.
Further, all the touch control wires are arranged between two adjacent rows of the pixel units, and all the data wires penetrate through one row of the pixel units which are electrically connected with the data wires.
Further, the touch traces except for the adjacent longitudinal partition gaps respectively penetrate through the pixel units corresponding to one row, and the data lines except for the adjacent longitudinal partition gaps are arranged between two adjacent rows of the pixel units.
Further, the touch trace adjacent to the longitudinal partition gap is aligned with a centerline of the longitudinal partition gap.
Further, the data line passing through a row of the pixel units is aligned with a center line of a row of the pixel units.
Further, the touch trace and the data line are located at the same layer; or the touch control wiring and the data line are positioned on different layers.
Further, the touch trace at the longitudinal partition gap is an ineffective touch trace, and the ineffective touch trace and the common electrode block are mutually insulated.
Further, a pixel electrode is disposed in each pixel unit of the array substrate, and the pixel electrode is electrically connected with the corresponding scanning line and the corresponding data line through a thin film transistor.
The application also provides an embedded touch display panel, which comprises an array substrate, a color film substrate arranged opposite to the array substrate, and a liquid crystal layer arranged between the array substrate and the color film substrate, wherein the array substrate is the array substrate.
Further, a plurality of color resistance layers corresponding to the pixel units and black matrixes for mutually spacing the color resistance layers are arranged on the color film substrate, and the black matrixes are arranged between any two adjacent columns and two rows of the pixel units.
The invention has the beneficial effects that: the touch control wiring adjacent to the longitudinal partition gap is positioned between two adjacent columns of pixel units and corresponds to the longitudinal partition gap, and the data line adjacent to the longitudinal partition gap penetrates through one column of pixel units electrically connected with the pixel units, so that the storage capacitance in all the pixel units is guaranteed to be the same, the coupling capacitance between all the data lines and the common electrode block is also guaranteed to be the same, and the difference between the storage capacitance or the coupling capacitance of the common electrode block in the partition and other areas is avoided, so that the display image quality is improved.
Drawings
FIG. 1 is a schematic plan view of an array substrate according to the prior art;
FIG. 2 is a schematic diagram of an in-cell touch display device according to the prior art;
FIG. 3 is a schematic diagram illustrating transmittance simulation of an in-cell touch display device according to the prior art;
FIG. 4 is a schematic plan view of a touch electrode according to an embodiment of the invention;
FIG. 5 is a schematic plan view of an array substrate according to a first embodiment of the present invention;
FIG. 6 is a schematic diagram of an in-cell touch display device according to an embodiment of the invention;
FIG. 7 is a schematic diagram illustrating transmittance simulation of an in-cell touch display device according to an embodiment of the invention;
FIG. 8 is a graph showing the transmittance simulation of the in-cell touch display device according to the prior art and the first embodiment of the present invention;
FIG. 9 is a schematic plan view of an array substrate according to a second embodiment of the present invention;
fig. 10 is a schematic plan view of a touch electrode according to a third embodiment of the invention.
Detailed Description
In order to further describe the technical means and effects adopted for achieving the preset purpose of the invention, the following detailed description is given of specific implementation, structure, characteristics and effects of the array substrate and the embedded touch display panel according to the invention by combining the accompanying drawings and the preferred embodiment:
example one
Fig. 4 is a schematic plan view of a touch electrode in the first embodiment of the invention, fig. 5 is a schematic plan view of an array substrate in the first embodiment of the invention, and fig. 6 is a schematic plan view of an in-cell touch display device in the first embodiment of the invention. As shown in fig. 4 to 6, in an array substrate according to an embodiment of the invention, a plurality of scan lines 1, a plurality of data lines 2, a plurality of touch traces 3, a plurality of pixel units SP and a plurality of common electrode blocks 21 are disposed on an array substrate 20. The plurality of scan lines 1 and the plurality of data lines 2 are mutually insulated and crossed, the array substrate 20 is provided with a pixel electrode 22 in each pixel unit SP, and the pixel electrode 22 is electrically connected with the corresponding scan line 1 and data line 2 through the thin film transistor 4. The thin film transistor 4 includes a gate electrode, an active layer, a drain electrode, and a source electrode, wherein the gate electrode is located on the same layer as the scan line 1 and is electrically connected to the active layer, the gate electrode is isolated from the active layer by an insulating layer, the source electrode is electrically connected to the data line 2, and the drain electrode is electrically connected to the pixel electrode 22 by a contact hole.
The extending direction of the touch running lines 3 is parallel to the extending direction of the data lines 2, each common electrode block 21 is electrically connected with the corresponding touch running line 3, and a common signal and a touch signal are applied to the common electrode block 21 through the touch running line 3, so that the common electrode block 21 is multiplexed to serve as a touch electrode.
A touch partition gap 211 is disposed between two adjacent common electrode blocks 21, and the touch partition gap 211 includes a longitudinal partition gap 211a disposed between two adjacent rows of pixel units SP and a transverse partition gap 211b disposed between two adjacent columns of pixel units SP, i.e., the longitudinal partition gap 211a is parallel to the data line 2, and the transverse partition gap 211b is parallel to the scan line 1. The touch trace 3 adjacent to the longitudinal partition gap 211a is located between two adjacent rows of pixel units SP and corresponds to the longitudinal partition gap 211a, and the data line 2 adjacent to the longitudinal partition gap 211a penetrates through one row of pixel units SP electrically connected with the same, so that the storage capacitance in all the pixel units SP is ensured to be the same, the coupling capacitance between all the data lines 2 and the common electrode block 21 is also ensured to be the same, and the difference between the storage capacitance or the coupling capacitance of the partition of the common electrode block 21 and other areas is avoided, thereby improving the display image quality.
In this embodiment, the number of the touch traces 3 is the same as the number of the common electrode blocks 21, and each touch trace 3 is connected to one common electrode block 21, i.e. the touch trace 3 located at the longitudinal partition gap 211a is also connected to the common electrode block 21, so that the number of the touch traces 3 can be reduced to the greatest extent. Although the coupling capacitance between the touch trace 3 and the common electrode block 21 at the longitudinal partition gap 211a is different from the coupling capacitance between the touch trace 3 and the common electrode block 21 at other areas, the touch trace 3 is applied with a touch signal, and the touch signal has no gray level as many steps, so that the difference in coupling capacitance between the touch trace 3 and the common electrode block 21 has substantially no influence on the touch function.
As shown in fig. 5, in the present embodiment, all the touch traces 3 are disposed between two adjacent rows of pixel units SP, and all the data lines 2 penetrate through one row of pixel units SP electrically connected therewith, so that the circuit arrangement on the array substrate 20 is more regular, and the mask design is facilitated.
Further, the touch trace 3 adjacent to the longitudinal partition gap 211a is aligned with the center line of the longitudinal partition gap 211 a. The data line 2 passing through one column of the pixel units SP is aligned with the center line of one column of the pixel units SP. Therefore, the distance between the data line 2 and the touch control wiring 3 is maximized, and the formation of coupling capacitance between the touch control wiring 3 and the data line 2 is avoided.
In this embodiment, the touch trace 3 and the data line 2 are located on the same layer, so that a process can be reduced, and the manufacturing process can be simplified. Of course, the touch trace 3 and the data line 2 may also be located in different layers, i.e. the touch trace 3 and the data line 2 are each made of a metal layer, and the manufacturing process is slightly complicated, but this embodiment is not excluded.
In this embodiment, the common electrode block 21 and the pixel electrode 22 are located differently and are spaced apart from each other in an insulating manner. The common electrode block 21 may be located above or below the pixel electrode 22 (the common electrode block 21 is shown below the pixel electrode 22 in fig. 6). Preferably, the common electrode block 21 is a planar electrode disposed over the entire surface, and the pixel electrode 22 is a slit electrode having a plurality of electrode bars within each pixel unit SP to form a fringe field switching pattern (Fringe Field Switching, FFS).
The application further provides an embedded touch display panel, which comprises an array substrate 20, a color film substrate 10 opposite to the array substrate 20, and a liquid crystal layer 30 between the array substrate 20 and the color film substrate 10. The array substrate 20 is the array substrate 20 described above.
As shown in fig. 6, in the initial state, the positive liquid crystal molecules in the liquid crystal layer 30 are aligned parallel to the color film substrate 10 and the array substrate 20, and the positive liquid crystal molecules on the side close to the color film substrate 10 are antiparallel to the alignment direction of the positive liquid crystal molecules on the side close to the array substrate 20.
A plurality of color resist layers 12 corresponding to the pixel units SP and a Black Matrix (BM) 11 that separates the color resist layers 12 from each other are disposed on the color film substrate 10 on a side facing the liquid crystal layer 30, and the black matrix 11 is disposed between any two adjacent columns and rows of the pixel units SP. The color resist layer 12 includes red (R), green (G), and blue (B) color resist materials, and respectively corresponds to pixel units of red, green, and blue colors. The black matrix 11 is positioned between pixel units of three colors of red, green and blue such that adjacent pixel units are spaced apart from each other by the black matrix 11.
Further, an upper polarizer 41 is disposed on a side of the color film substrate 10 away from the liquid crystal layer 30, a lower polarizer 42 is disposed on a side of the array substrate 20 away from the liquid crystal layer 30, and a light transmission axis of the upper polarizer 41 is perpendicular to a light transmission axis of the lower polarizer 42.
The color film substrate 10 and the array substrate 20 may be made of transparent substrates such as glass, acrylic, and polycarbonate. The materials of the common electrode block 21 and the pixel electrode 22 may be transparent electrodes such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO).
Fig. 3 is a schematic diagram illustrating the transmittance simulation of an in-cell touch display device according to the prior art, fig. 7 is a schematic diagram illustrating the transmittance simulation of an in-cell touch display device according to an embodiment of the invention, and fig. 8 is a comparative diagram illustrating the transmittance simulation of an in-cell touch display device according to the prior art and an embodiment of the invention. As shown in fig. 3, 7 and 8, the transmittance at the touch trace 3 in the pixel unit SP corresponds to the transmittance at the data line 2 in the pixel unit SP in fig. 3 a, and the transmittance at the data line 2 in the pixel unit SP corresponds to the transmittance in fig. 7B; the dashed curve in fig. 8 shows the change of the transmittance with the driving voltage in the prior art, and the solid curve in fig. 8 shows the change of the transmittance with the driving voltage in the present application. Since the touch partition gap 211 does not have the common electrode block 21 in the prior art and the touch partition gap 211 is located in the pixel unit SP, the electric field strength of the pixel electrode 22 at the touch partition gap 211 is weak, and the liquid crystal molecules are not substantially deflected, so that the transmittance of the edge (at a in fig. 3 a) of the touch trace 3 in the pixel unit SP is reduced. In this application, the touch-control partition gap 211 is located between two adjacent rows of pixel units SP, so that the electric field between the pixel electrode 22 and the common electrode block 21 in each pixel unit SP is relatively uniform, and the liquid crystal molecules are deflected, so that the transmittance of the edge (at B in fig. 7) of the data line 2 in the pixel unit SP is not substantially affected. As can be seen from fig. 8, the penetration rate in the present application is improved compared with the prior art.
Example two
Fig. 9 is a schematic plan view of an array substrate according to a second embodiment of the invention. As shown in fig. 9, the array substrate and the in-cell touch display panel provided in the second embodiment of the present invention are substantially the same as those in the first embodiment (fig. 4 to 8), except that in the present embodiment:
the touch traces 3 except for the adjacent longitudinal partition gaps 211a respectively penetrate through a row of corresponding pixel units SP, and the data lines 2 except for the adjacent longitudinal partition gaps 211a are disposed between two adjacent rows of pixel units SP, i.e. the touch traces 3 except for the adjacent longitudinal partition gaps 211a and the data lines 2 are arranged in a conventional manner, although the regularity of the circuits on the array substrate 20 is reduced, but such an embodiment is not excluded.
Those skilled in the art will understand that the other structures and working principles of the present embodiment are the same as those of the first embodiment, and will not be described herein.
Example III
Fig. 10 is a schematic plan view of a touch electrode according to a third embodiment of the invention. As shown in fig. 10, the array substrate and the in-cell touch display panel according to the third embodiment of the present invention are substantially the same as those of the first embodiment (fig. 4 to 8) and the second embodiment (fig. 9), except that in the present embodiment:
the number of the touch traces 3 is greater than that of the common electrode blocks 21, the touch traces 3 at the longitudinal partition gaps 211a are invalid touch traces, and the invalid touch traces are mutually insulated from the common electrode blocks 21, i.e. the touch traces 3 at the longitudinal partition gaps 211a are not connected with the common electrode blocks 21. Since there is a difference in coupling capacitance between the touch trace 3 and the common electrode block 21 at the longitudinal partition gap 211a and the touch trace 3 and the common electrode block 21 at other areas, the touch trace 3 at the longitudinal partition gap 211a is set as an inactive touch trace, and the influence on the touch function can be completely avoided.
Those skilled in the art will understand that the other structures and working principles of the present embodiment are the same as those of the first and second embodiments, and will not be described herein.
In this document, terms such as up, down, left, right, front, rear, etc. are defined by the positions of the structures in the drawings and the positions of the structures with respect to each other, for the sake of clarity and convenience in expressing the technical solution. It should be understood that the use of such orientation terms should not limit the scope of the protection sought herein. It should also be understood that the terms "first" and "second," etc., as used herein, are used merely for distinguishing between names and not for limiting the number and order.
The present invention is not limited to the preferred embodiments, but is capable of modification and variation in detail, and other modifications and variations can be made by those skilled in the art without departing from the scope of the present invention.
Claims (10)
1. The array substrate is characterized in that a plurality of scanning lines (1), a plurality of data lines (2), a plurality of touch control partition gaps (211) are arranged on the array substrate (20), a plurality of pixel units (SP) and a plurality of common electrode blocks (21), the scanning lines (1) and the data lines (2) are mutually insulated and crossed, the extending direction of the touch control partition gaps (3) is mutually parallel to the extending direction of the data lines (2), each common electrode block (21) is electrically connected with the corresponding touch control partition line (3), a touch control partition gap (211) is arranged between every two adjacent common electrode blocks (21), each touch control partition gap (211) comprises a longitudinal partition gap (211 a) arranged between every two adjacent rows of pixel units (SP) and a transverse partition gap (211 b) arranged between every two adjacent rows of pixel units (SP), the touch control partition gap (3) is positioned between every two adjacent rows of pixel units (SP) and is electrically connected with the corresponding pixel units (211 a) in the longitudinal partition gap (211 a).
2. The array substrate according to claim 1, wherein all the touch traces (3) are disposed between two adjacent rows of the pixel units (SP), and all the data lines (2) penetrate through one row of the pixel units (SP) electrically connected with the same.
3. The array substrate according to claim 1, wherein the touch traces (3) except for the adjacent longitudinal partition gaps (211 a) respectively penetrate through a row of the corresponding pixel units (SP), and the data lines (2) except for the adjacent longitudinal partition gaps (211 a) are disposed between two adjacent rows of the pixel units (SP).
4. The array substrate according to claim 1, wherein the touch trace (3) adjacent to the longitudinal partition gap (211 a) is aligned with a center line of the longitudinal partition gap (211 a).
5. An array substrate according to claim 1, wherein the data lines (2) running through a row of the pixel cells (SP) are aligned with the center line of a row of the pixel cells (SP).
6. The array substrate according to claim 1, wherein the touch trace (3) and the data line (2) are located at the same layer; or the touch control wiring (3) and the data line (2) are positioned on different layers.
7. The array substrate according to claim 1, wherein the touch trace (3) located at the longitudinal partition gap (211 a) is an inactive touch trace, and the inactive touch trace is insulated from the common electrode block (21).
8. The array substrate according to any one of claims 1 to 7, wherein the array substrate (20) is provided with a pixel electrode (22) in each pixel unit (SP), and the pixel electrode (22) is electrically connected to the corresponding scan line (1) and data line (2) through a thin film transistor (4).
9. An embedded touch display panel, comprising an array substrate (20), a color film substrate (10) disposed opposite to the array substrate (20), and a liquid crystal layer (30) disposed between the array substrate (20) and the color film substrate (10), wherein the array substrate (20) is the array substrate (20) according to any one of claims 1-8.
10. The in-cell touch display panel according to claim 9, wherein the color film substrate (10) is provided with a plurality of color resists (12) corresponding to the pixel units (SP) and a black matrix (11) for spacing the color resists (12) from each other, and the black matrix (11) is disposed between any two adjacent columns and two rows of the pixel units (SP).
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311277563.0A CN117348284A (en) | 2023-09-28 | 2023-09-28 | Array substrate and embedded touch display panel |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311277563.0A CN117348284A (en) | 2023-09-28 | 2023-09-28 | Array substrate and embedded touch display panel |
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| CN117348284A true CN117348284A (en) | 2024-01-05 |
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| CN202311277563.0A Pending CN117348284A (en) | 2023-09-28 | 2023-09-28 | Array substrate and embedded touch display panel |
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| Country | Link |
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| CN (1) | CN117348284A (en) |
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