CN117337029A

CN117337029A - Semiconductor structure and forming method thereof

Info

Publication number: CN117337029A
Application number: CN202210728981.6A
Authority: CN
Inventors: 邵光速
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-06-24
Filing date: 2022-06-24
Publication date: 2024-01-02
Also published as: WO2023245759A1

Abstract

The embodiment of the disclosure discloses a semiconductor structure and a forming method thereof, wherein the semiconductor structure comprises: a substrate, and a device structure layer on the substrate; the device structure layer includes: an active layer, bit lines, word lines, contact plugs and a memory structure; the bit line is located above the substrate; the active layer is positioned above the bit line and parallel to the surface of the substrate; the contact plug connects the bit line with the first end of the active layer; the second end of the active layer is connected with the storage structure; the word line is located above the active layer channel region.

Description

Semiconductor structure and forming method thereof

Technical Field

The present disclosure relates to the field of integrated circuit fabrication, and more particularly, to a semiconductor structure and a method of forming the same.

Background

Memory devices are an important part of Integrated Circuits (ICs) and modern electronic devices. A memory device, such as a Dynamic Random Access Memory (DRAM) array, may include a plurality of memory cells, where the memory cells may include a selector, such as a transistor, to control access to the memory cells. A Thin Film Transistor (TFT) is a field effect transistor that includes a channel layer, a gate electrode, and source and drain electrodes on a supporting but non-conductive substrate. TFTs are different from conventional transistors, where the channel of the conventional transistor is typically within a substrate (such as a silicon substrate). By integrating the TFT in the back-end while leaving silicon substrate area for high speed transistors, the TFT has become an attractive option to drive moore's law. TFTs may be used as selectors for memory cells in memory devices (e.g., DRAM devices).

However, current designs and implementations of memory devices (e.g., DRAM devices) still face many challenges. For example, current DRAM device fabrication processes require high levels of memory density and further increases in memory density are difficult.

Disclosure of Invention

In view of the above, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same.

According to a first aspect of embodiments of the present disclosure, there is provided a semiconductor structure comprising:

a substrate, and a device structure layer on the substrate;

the device structure layer includes: an active layer, bit lines, word lines, contact plugs and a memory structure;

the bit line is located above the substrate;

the active layer is positioned above the bit line and parallel to the surface of the substrate;

the contact plug connects the bit line with the first end of the active layer;

the second end of the active layer is connected with the storage structure; the word line is located above the active layer channel region.

In some embodiments, the active layer includes one or more of an indium gallium zinc oxide film, an indium doped zinc oxide film, a zinc tin oxide film, and an yttrium doped zinc oxide film.

In some embodiments, the bit lines extend in a first direction and the word lines extend in a second direction; the first direction and the second direction are perpendicular to each other and are parallel to the surface of the substrate; the extending direction of the storage structure is perpendicular to the surface of the substrate.

In some embodiments, the second end of the active layer is connected to a middle region of the storage structure.

In some embodiments, the word line includes a metal layer and a metal barrier layer, the metal layer being located over the metal barrier layer.

In some embodiments, further comprising:

a first insulating layer on the substrate; the bit line is embedded in the upper surface of the first insulating layer;

a second insulating layer on the first insulating layer; the contact plug penetrates through the second insulating layer and is in contact with the bit line;

a third insulating layer on the second insulating layer; the active layer penetrates through the third insulating layer;

a dielectric layer between the third insulating layer and the word line;

an isolation layer located on the dielectric layer and the word line;

and the fourth insulating layer is positioned on the isolating layer.

In some embodiments, the memory structure extends through the fourth insulating layer, the isolation layer, the dielectric layer, the third insulating layer, and a portion of the second insulating layer.

In some embodiments, the memory structure includes a capacitor structure including a first metal layer, a dielectric layer, and a second metal layer disposed in sequence.

In some embodiments, the substrate includes a plurality of device structure layers stacked in sequence thereon.

According to a second aspect of embodiments of the present disclosure, there is provided a method for forming a semiconductor structure, including:

providing a substrate;

forming a bit line on the substrate;

forming a contact plug on the bit line;

forming an active layer on the contact plug, the active layer being parallel to a surface of the substrate; a first end of the active layer is electrically connected with the bit line through the contact plug;

forming a word line on the active layer;

and forming a storage structure, wherein the storage structure is connected with the second end of the active layer.

In some embodiments, the forming the bit line includes:

forming a first insulating layer on the substrate;

etching the first insulating layer to form a first groove extending along a first direction;

and filling conductive materials in the first grooves to form bit lines.

In some embodiments, the forming a contact plug includes:

forming a second insulating layer on the first insulating layer;

Etching the second insulating layer to form a first through hole penetrating through the second insulating layer;

and filling conductive materials in the first through holes to form contact plugs.

In some embodiments, the forming an active layer includes:

forming a third insulating layer on the second insulating layer;

etching the third insulating layer to form a second groove penetrating through the third insulating layer;

and filling semiconductor materials in the second grooves to form active layers.

In some embodiments, the forming the word line includes:

forming a dielectric layer on the third insulating layer;

forming word lines on the dielectric layer, wherein the word lines extend along a second direction; the first direction and the second direction are perpendicular to each other and are parallel to the surface of the substrate.

In some embodiments, the forming a memory structure includes:

forming isolation layers on the dielectric layer and the word lines;

forming a fourth insulating layer on the isolation layer;

etching the fourth insulating layer, the isolation layer, the dielectric layer, the third insulating layer and part of the second insulating layer to form a second through hole;

and forming a storage structure in the second through hole.

In some embodiments, the forming a memory structure within the second via includes:

And sequentially forming a first metal layer, a dielectric layer and a second metal layer in the second through hole along the radial inward direction of the storage structure.

In the embodiment of the disclosure, the active layer which is substantially parallel to the surface of the substrate is formed, so that the size of a single layer is larger, the storage density is improved, the multi-layer stacking of the semiconductor structure can be realized, meanwhile, the manufacturing scheme is simpler, and the process difficulty is reduced; in addition, the bit line in the embodiment of the disclosure is connected with the first end of the active layer through the contact plug, so that the distance between the bit line and the word line is longer, and parasitic capacitance can be reduced; meanwhile, the second end of the active layer is connected with the storage structure, so that landing pads are not needed, and the problem of poor contact is reduced.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the conventional technology, the drawings required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.

Fig. 1 is a schematic structural diagram of a semiconductor structure according to an embodiment of the disclosure;

Fig. 2 is a schematic structural diagram of a semiconductor structure according to another embodiment of the present disclosure;

fig. 3 is a flowchart illustrating a method for forming a semiconductor structure according to an embodiment of the disclosure;

fig. 4a to 4q are schematic structural views of a semiconductor structure provided in an embodiment of the present disclosure during formation;

fig. 5 a-5 d are top views of partial embodiments of device structure layers.

Reference numerals illustrate:

10-a substrate;

20-a device structure layer; 21-bit lines; 22-contact plugs; 23-an active layer; 24-word lines; 241-a metal barrier layer; 242-metal layers; 25-a storage structure; 251-a first metal layer; 252-a dielectric layer; 253—a second metal layer;

31-a first insulating layer; 32-a second insulating layer; 33-a third insulating layer; 34-a dielectric layer; 35-isolating layer; 36-a fourth insulating layer; 301-a first trench; 302-a first via; 303-a second trench; 304-second vias.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present disclosure.

Spatially relative terms, such as "under … …," "under … …," "below," "under … …," "above … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

For a thorough understanding of the present disclosure, detailed steps and detailed structures will be presented in the following description in order to illustrate the technical aspects of the present disclosure. Preferred embodiments of the present disclosure are described in detail below, however, the present disclosure may have other implementations in addition to these detailed descriptions.

Based on this, the disclosed embodiments provide a semiconductor structure. Fig. 1 is a schematic structural diagram of a semiconductor structure according to an embodiment of the disclosure.

Referring to fig. 1, the semiconductor structure includes:

a substrate 10 and a device structure layer 20 on the substrate 10;

the device structure layer 20 includes: an active layer 23, bit lines 21, word lines 24, contact plugs 22, and memory structures 25;

the bit line 21 is located above the substrate 10;

the active layer 23 is located above the bit line 21 and parallel to the surface of the substrate 10;

the contact plug 22 connects the bit line 21 and the first end of the active layer 23;

a second end of the active layer 23 is connected to the storage structure 25; the word line 24 is located above the channel region of the active layer 23.

In an embodiment, the substrate 10 may be a silicon substrate, a germanium substrate, a silicon carbide substrate, an SOI (silicon on insulator ) substrate, a GOI (germanium on insulator, germanium On Insulator) substrate, or the like, or may be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a group III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, or the like), or may be a stacked structure, such as Si/SiGe, or the like, or may be other epitaxial structure, such as SGOI (germanium on insulator, silicon) or the like.

In an embodiment, the material of the contact plug 22 is, for example, tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof.

In an embodiment, the material of the active layer may be an amorphous material, and in particular, the active layer 23 includes one or more of an indium gallium zinc oxide film (IGZO), an indium doped zinc oxide film (IZO), a zinc tin oxide film (ZTO), and an yttrium doped zinc oxide film (YZO).

In the embodiment of the disclosure, the amorphous material is adopted as the material of the active region, so that compared with the existing semiconductor structure adopting a curved channel structure, the size of a single layer is larger, the storage density is improved, the manufacturing scheme is simpler, and the process difficulty is reduced.

In one embodiment, as shown in FIG. 1, the bit line 21 extends in a first direction and the word line 24 extends in a second direction; the first direction and the second direction are perpendicular to each other and are both parallel to the surface of the substrate 10; the extension direction of the storage structures 25 is perpendicular to the surface of the substrate 10.

The material of the bit line 21 includes tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, or any combination thereof.

In an embodiment, the second end of the active layer 23 is connected to the middle region of the memory structure 25. The second end of the active layer is connected with the middle area of the storage structure, so that landing pads are not needed, the problem of poor contact is reduced, part of the storage structure can penetrate into the space where the contact plug is located, the three-dimensional stacking height is reduced, multi-layer stacking of the semiconductor structure can be realized, and the storage density of the semiconductor structure is improved.

In an embodiment, the word line includes a metal layer 242 and a metal barrier 241, the metal layer 242 being located over the metal barrier 241.

The material of the metal layer 242 includes tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, or any combination thereof. The material of the metal barrier 241 includes, but is not limited to, an oxide, such as silicon oxide.

In an embodiment, the first and second ends of the active layer 23 are formed as a drain electrode and a source electrode, respectively; the drain is electrically coupled to the bit line 21 through the contact plug 22; the source is electrically coupled to the memory structure 25. In another embodiment, the first and second ends of the active layer 23 are formed as a source and a drain, respectively; the source is electrically coupled to the bit line 21 through the contact plug 22; the drain is electrically coupled to the memory structure 25.

The source or drain is electrically coupled to the bit line through a contact plug extending in a direction perpendicular to the surface of the substrate, such that the contact plug provides a greater distance between the bit line and the word line, reducing parasitic capacitance.

In an embodiment, the semiconductor structure further comprises:

a first insulating layer 31 on the substrate 10; the bit line 21 is embedded in the upper surface of the first insulating layer 31;

a second insulating layer 32 on the first insulating layer 31; the contact plug 22 penetrates the second insulating layer 32 and contacts the bit line 21;

a third insulating layer 33 on the second insulating layer 32; the active layer 23 penetrates the third insulating layer 33;

A dielectric layer 34 between the third insulating layer 33 and the word line 24;

an isolation layer 35 on the dielectric layer 34 and the word line 24;

a fourth insulating layer 36 is disposed on the isolation layer 35.

Materials of the first insulating layer 31, the second insulating layer 32, the third insulating layer 33, the dielectric layer 34, the isolation layer 35, and the fourth insulating layer 36 include, but are not limited to, oxides, nitrides, metal oxides, oxynitrides, and the like; alternatively, a high-K dielectric material may be included. Specifically, the high-K dielectric material may include, but is not limited to, aluminum oxide (Al 2O 3), tantalum oxide (Ta 2O 3), titanium oxide (TiO 2), yttrium oxide (Y2O 3), zirconium oxide (ZrO 2), zirconium silicon oxide (ZrSixOy), hafnium oxide (HfO 2), hafnium silicon oxide (HfSixOy), hafnium silicon oxynitride (HfSiON), hafnium zirconate (HfZrO 4), lanthanum oxide (La 2O 3), lanthanum aluminum oxide (LaAlxOy), lanthanum hafnium oxide (LaHfxOy), hafnium aluminum oxide (HfAlxOy), and/or praseodymium oxide (Pr 2O 3), etc.

In one embodiment, the memory structure 25 extends through the fourth insulating layer 36, the isolation layer 35, the dielectric layer 34, the third insulating layer 33, and a portion of the second insulating layer 32.

The storage structure is extended into the second insulating layer, namely, the space where the contact plug is located, so that the three-dimensional stacking height is reduced, and the storage density of the semiconductor structure is improved.

In an embodiment, the memory structure includes a capacitor structure including a first metal layer 251, a dielectric layer 252, and a second metal layer 253 disposed in sequence.

The first metal layer 251 and the second metal layer 252 are insulated by the dielectric layer 252.

The materials of the first metal layer 251 and the second metal layer 253 include one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, such as titanium nitride (TiN).

The material of the dielectric layer 252 includes, but is not limited to, oxide, nitride, metal oxide, oxynitride, etc.; alternatively, the material of the dielectric layer 252 may include a high-K dielectric material. Specifically, the high-K dielectric material may include, but is not limited to, aluminum oxide (Al 2O 3), tantalum oxide (Ta 2O 3), titanium oxide (TiO 2), yttrium oxide (Y2O 3), zirconium oxide (ZrO 2), zirconium silicon oxide (ZrSixOy), hafnium oxide (HfO 2), hafnium silicon oxide (HfSixOy), hafnium silicon oxynitride (HfSiON), hafnium zirconate (HfZrO 4), lanthanum oxide (La 2O 3), lanthanum aluminum oxide (LaAlxOy), lanthanum hafnium oxide (LaHfxOy), hafnium aluminum oxide (HfAlxOy), and/or praseodymium oxide (Pr 2O 3), etc.

In one embodiment, as shown in fig. 2, the substrate 10 includes a plurality of device structure layers 20 stacked in sequence.

The embodiment of the disclosure further provides a method for forming a semiconductor structure, referring to fig. 3, and the method includes the following steps:

step 301: providing a substrate;

step 302: forming a bit line on the substrate;

step 303: forming a contact plug on the bit line;

step 304: forming an active layer on the contact plug, the active layer being parallel to a surface of the substrate; a first end of the active layer is electrically connected with the bit line through the contact plug;

step 305: forming a word line on the active layer;

step 306: and forming a storage structure, wherein the storage structure is connected with the second end of the active layer.

The method for forming the semiconductor structure provided in the embodiments of the present disclosure is further described in detail below with reference to specific embodiments.

Fig. 4a to 4q are schematic structural diagrams of a semiconductor structure provided in an embodiment of the present disclosure during a formation process. It should be noted that fig. 4a to 4q are schematic cross-sectional views of the semiconductor structure, and fig. 4a to 4q are top views of the semiconductor structure.

First, referring to fig. 4a, step 301 is performed to provide a substrate 10.

Next, referring to fig. 4a to 4c, step 302 is performed to form the bit line 21 on the substrate 10.

In one embodiment, the forming the bit line 21 includes:

forming a first insulating layer 31 on the substrate 10; etching the first insulating layer 31 to form a first trench 301 extending in a first direction; the first trench 301 is filled with a conductive material to form a bit line 21.

Specifically, referring first to fig. 4a, a first insulating layer 31 is formed on the substrate.

In practice, the first insulating layer 31 may be formed using one or more thin film deposition processes; in particular, the deposition process includes, but is not limited to, a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, an Atomic Layer Deposition (ALD) process, or a combination thereof.

Next, referring to fig. 4b, the first insulating layer 31 is etched to form a first trench 301 extending in a first direction.

Specifically, a mask layer may be grown on the upper surface of the first insulating layer 31, and then patterned to show a first trench pattern to be etched on the mask layer, and the mask layer may be patterned through a photolithography process. The mask layer may be a photoresist mask or a hard mask patterned based on a photolithographic mask; when the mask layer is a photoresist mask, the mask layer is patterned, in particular, by exposing, developing, and photoresist stripping. Next, a first trench 301 having a certain depth is etched in accordance with the first trench pattern to be etched.

Here, the first trench 301 may be formed using, for example, a wet or dry etching process.

Next, referring to fig. 4c, the first trench 301 is filled with a conductive material to form the bit line 21.

Next, referring to fig. 4d to 4f, step 303 is performed to form a contact plug 22 on the bit line 21.

In one embodiment, the forming the contact plug 22 includes:

forming a second insulating layer 32 on the first insulating layer 31; etching the second insulating layer 32 to form a first via 302 penetrating the second insulating layer 32; and filling conductive material in the first through hole 302 to form the contact plug 22.

Specifically, referring first to fig. 4d, a second insulating layer 32 is formed on the first insulating layer 31.

In practice, the second insulating layer 32 may be formed using one or more thin film deposition processes; in particular, the deposition process includes, but is not limited to, a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, an Atomic Layer Deposition (ALD) process, or a combination thereof.

Next, referring to fig. 4e, the second insulating layer 32 is etched, and a first via 302 is formed through the second insulating layer 32.

Specifically, a mask layer may be grown on the upper surface of the second insulating layer 32, and then patterned to show the first via pattern to be etched on the mask layer, which may be patterned through a photolithography process. The mask layer may be a photoresist mask or a hard mask patterned based on a photolithographic mask; when the mask layer is a photoresist mask, the mask layer is patterned, in particular, by exposing, developing, and photoresist stripping. A first via 302 is then etched through the second insulating layer 32 in accordance with the first via pattern to be etched.

Here, the first via 302 may be formed using, for example, a wet or dry etching process.

Next, referring to fig. 4f, the first via 302 is filled with a conductive material to form the contact plug 22.

The material of the contact plug 22 is, for example, tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof.

Next, referring to fig. 4g to 4i, step 304 is performed to form an active layer 23 on the contact plug 22, the active layer 23 being parallel to the surface of the substrate 10; the first end of the active layer 23 is electrically connected to the bit line 21 through the contact plug 22.

In an embodiment, the forming the active layer 23 includes:

forming a third insulating layer 33 on the second insulating layer 32; etching the third insulating layer 33 to form a second trench 303 penetrating the third insulating layer 33; the second trench 303 is filled with a semiconductor material to form the active layer 23.

Specifically, referring first to fig. 4g, a third insulating layer 33 is formed on the second insulating layer 32.

In practice, the third insulating layer 33 may be formed using one or more thin film deposition processes; in particular, the deposition process includes, but is not limited to, a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, an Atomic Layer Deposition (ALD) process, or a combination thereof.

Next, referring to fig. 4h, the third insulating layer 33 is etched, and a second trench 303 penetrating the third insulating layer 33 is formed.

Specifically, a mask layer may be grown on the upper surface of the third insulating layer 33, and then patterned to show the second trench pattern to be etched on the mask layer, which may be patterned through a photolithography process. The mask layer may be a photoresist mask or a hard mask patterned based on a photolithographic mask; when the mask layer is a photoresist mask, the mask layer is patterned, in particular, by exposing, developing, and photoresist stripping. Next, a second trench 303 is etched through the third insulating layer 33 according to the second trench pattern to be etched.

Here, the second trench 303 may be formed using, for example, a wet or dry etching process.

In some embodiments, as shown in fig. 4h (2), the second grooves 303 are aligned along both the first direction and the second direction; in other embodiments, as shown in fig. 4h (3), the second grooves 303 are staggered.

It should be noted that, in either the embodiment shown in fig. 4h (2) or the embodiment shown in fig. 3, the contact plug 22 is located at one end of the second trench 303.

Next, referring to fig. 4i, the second trench 303 is filled with a semiconductor material to form the active layer 23.

In some embodiments, as shown in (2) of fig. 4i, since the second trenches are disposed in alignment in both the first direction and the second direction, the active layer 23 is formed in alignment in both the first direction and the second direction. In other embodiments, as shown in fig. 4i (3), the second trenches are staggered, so that the active layers are also staggered.

The material of the active layer may be an amorphous material, and in particular, the active layer 23 includes one or more of an indium gallium zinc oxide film (IGZO), an indium doped zinc oxide film (IZO), a zinc tin oxide film (ZTO), and an yttrium doped zinc oxide film (YZO).

Next, referring to fig. 4j to 4k, step 305 is performed to form the word line 24 on the active layer 23.

In one embodiment, the forming of the word line 24 includes:

Forming a dielectric layer 34 on the third insulating layer 33; forming a word line 24 on the dielectric layer 34, the word line 24 extending in a second direction; the first direction and the second direction are perpendicular to each other and are all parallel to the surface of the substrate 10.

Specifically, referring first to fig. 4j, a dielectric layer 34 is formed on the third insulating layer 33.

In practice, the dielectric layer 34 may be formed using one or more thin film deposition processes; in particular, the deposition process includes, but is not limited to, a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, an Atomic Layer Deposition (ALD) process, or a combination thereof.

Next, referring to fig. 4k, a word line 24 is formed on the dielectric layer 34, the word line 24 extending in a second direction; the first direction and the second direction are perpendicular to each other and are all parallel to the surface of the substrate 10.

Specifically, the forming the word line 24 on the dielectric layer 34 includes: a metal barrier 241 is formed on the dielectric layer 34, and a metal layer 242 is formed on the metal barrier 241.

Next, referring to fig. 4l to 4q, step 306 is performed to form a memory structure 25, where the memory structure 25 is connected to the second terminal of the active layer 23.

In an embodiment, the active layer 23 is formed as a drain electrode and a source electrode at a first end and a second end, respectively; the drain is electrically coupled to the bit line 21 through the contact plug 22; the source is electrically coupled to the memory structure 25. In another embodiment, the first and second ends of the active layer 23 are formed as a source and a drain, respectively; the source is electrically coupled to the bit line 21 through the contact plug 22; the drain is electrically coupled to the memory structure 25.

In one embodiment, the forming the storage structure 25 includes:

forming an isolation layer 35 on the dielectric layer 34 and the word line 24; forming a fourth insulating layer 36 on the isolation layer 35; etching the fourth insulating layer 36, the isolation layer 35, the dielectric layer 34, the third insulating layer 33, and a part of the second insulating layer 32 to form a second via 304; a memory structure 25 is formed within the second via 304.

Specifically, referring first to fig. 4l, an isolation layer 35 is formed over the dielectric layer 34 and the word line 24.

In practice, the isolation layer 35 may be formed using one or more thin film deposition processes; in particular, the deposition process includes, but is not limited to, a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, an Atomic Layer Deposition (ALD) process, or a combination thereof.

Next, referring to fig. 4m, a fourth insulating layer 36 is formed on the isolation layer 35.

In practice, the fourth insulating layer 36 may be formed using one or more thin film deposition processes; in particular, the deposition process includes, but is not limited to, a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, an Atomic Layer Deposition (ALD) process, or a combination thereof.

In an embodiment, the materials of the first insulating layer 31, the second insulating layer 32, the third insulating layer 33, the dielectric layer 34, the isolation layer 35 and the fourth insulating layer 36 include, but are not limited to, oxides, nitrides, metal oxides, oxynitrides, and the like; alternatively, a high-K dielectric material may be included. Specifically, the high-K dielectric material may include, but is not limited to, aluminum oxide (Al 2O 3), tantalum oxide (Ta 2O 3), titanium oxide (TiO 2), yttrium oxide (Y2O 3), zirconium oxide (ZrO 2), zirconium silicon oxide (ZrSixOy), hafnium oxide (HfO 2), hafnium silicon oxide (HfSixOy), hafnium silicon oxynitride (HfSiON), hafnium zirconate (HfZrO 4), lanthanum oxide (La 2O 3), lanthanum aluminum oxide (LaAlxOy), lanthanum hafnium oxide (LaHfxOy), hafnium aluminum oxide (HfAlxOy), and/or praseodymium oxide (Pr 2O 3), etc.

Next, referring to fig. 4n, the fourth insulating layer 36, the isolation layer 35, the dielectric layer 34, the third insulating layer 33, and a portion of the second insulating layer 32 are etched to form a second via 304.

Specifically, a mask layer may be grown on the upper surface of the fourth insulating layer 36, and then patterned to show a second via pattern to be etched on the mask layer, which may be patterned through a photolithography process. The mask layer may be a photoresist mask or a hard mask patterned based on a photolithographic mask; when the mask layer is a photoresist mask, the mask layer is patterned, in particular, by exposing, developing, and photoresist stripping. A second via 304 having a depth is then etched in accordance with the second via pattern to be etched.

Here, the second via 304 may be formed using, for example, a wet or dry etching process.

In one embodiment, there are two cases of the positional relationship between the second via 304 for forming the memory structure and the active layer 23. Wherein, in some embodiments, as shown in fig. 4n (2), the orthographic projection of the second through hole 304 for forming the memory structure on the substrate plane is completely located in the orthographic projection of the active layer 23 on the substrate plane, and then the contact manner is a fully-enclosed contact; in other embodiments, as shown in fig. 4n (3), the orthographic projection of the second via 304 for forming the memory structure on the substrate plane is located in the orthographic projection of the active layer 23 on the substrate plane, and the contact manner is a semi-surrounding contact.

Next, referring to fig. 4o to 4q, a memory structure 25 is formed in the second via 304.

In the embodiment of the disclosure, the storage structure is extended into the second insulating layer, namely, the space where the contact plug is located, so that the three-dimensional stacking height is reduced, and the storage density of the semiconductor structure is improved.

In an embodiment, the forming the storage structure 25 in the second through hole 304 includes: a first metal layer 251, a dielectric layer 252, and a second metal layer 253 are sequentially formed within the second via hole 304 in a radially inward direction of the memory structure 25.

Specifically, as shown in fig. 4o, a first metal layer 251 is formed on the sidewall and the bottom of the second via 304.

Next, as shown in fig. 4p, a dielectric layer 252 is formed on the sidewall and bottom of the first metal layer 251, and the dielectric layer 252 also completely covers the fourth insulating layer 36.

Next, as shown in fig. 4q, a second metal layer 252 is formed on the surface of the dielectric layer 252, the second metal layer completely filling the second via 304 and covering a portion of the dielectric layer 252 on the fourth insulating layer 36.

Fig. 5a to 5d are top views of a portion of embodiments of the device structure layer, and it should be explained that fig. 5a to 5d only show the positional relationship of the contact plug, the active layer, the word line and the memory structure in the direction parallel to the plane of the substrate, and the positional relationship of the contact plug, the active layer, the word line and the memory structure in the direction perpendicular to the substrate is not required.

In some embodiments, as shown in fig. 5a, the active layer 23 is aligned along the first direction and the second direction, one end of the active layer 23 is connected to the contact plug 22, the other end of the active layer 23 is connected to the memory structure 25, and the word line 24 is located above the active layer 23 between the contact plug 22 and the memory structure 25, that is, above the channel region of the active layer 23. In the embodiment shown in fig. 5a, one word line is formed over one active layer.

In other embodiments, as shown in fig. 5b, the active layers 23 are staggered, and one end of the active layer 23 is connected to the contact plug 22, the other end of the active layer 23 is connected to the storage structure 25, and the word line 24 is located above the active layer 23 between the contact plug 22 and the storage structure 25, i.e. above the channel region of the active layer 23. In the embodiment shown in fig. 5b, one word line is formed over one active layer.

In other embodiments, as shown in fig. 5c, the active layer 23 is aligned along the first direction and the second direction, and both ends of the active layer 23 are connected to the storage structure 25, the middle area of the active layer 23 is connected to the contact plug 22, and the word line 24 is located above the active layer 23 between the contact plug 22 and the storage structure 25, that is, above the channel area of the active layer 23. In the embodiment shown in fig. 5c, two word lines are formed over one active layer.

In other embodiments, as shown in fig. 5d, the active layers 23 are staggered, and both ends of the active layers 23 are connected to the storage structures 25, the middle area of the active layers 23 is connected to the contact plugs 22, and the word lines 24 are located above the active layers 23 between the contact plugs 22 and the storage structures 25, i.e. above the channel area of the active layers 23. In the embodiment shown in fig. 5d, two word lines are formed over one active layer.

The foregoing description of the preferred embodiments of the present disclosure is not intended to limit the scope of the present disclosure, but is intended to cover any modifications, equivalents, and improvements within the spirit and principles of the present disclosure.

Claims

1. A semiconductor structure, comprising:

a substrate, and a device structure layer on the substrate;

the bit line is located above the substrate;

the contact plug connects the bit line with the first end of the active layer;

2. The semiconductor structure of claim 1, wherein,

the active layer includes one or more of an indium gallium zinc oxide film, an indium doped zinc oxide film, a zinc tin oxide film, and an yttrium doped zinc oxide film.

3. The semiconductor structure of claim 1, wherein,

the bit line extends along a first direction, and the word line extends along a second direction; the first direction and the second direction are perpendicular to each other and are parallel to the surface of the substrate; the extending direction of the storage structure is perpendicular to the surface of the substrate.

4. The semiconductor structure of claim 1, wherein,

The second end of the active layer is connected to the middle region of the memory structure.

5. The semiconductor structure of claim 1, wherein,

the word line includes a metal layer and a metal barrier layer, the metal layer being located over the metal barrier layer.

6. The semiconductor structure of claim 1, further comprising:

a dielectric layer between the third insulating layer and the word line;

an isolation layer located on the dielectric layer and the word line;

and the fourth insulating layer is positioned on the isolating layer.

7. The semiconductor structure of claim 6, wherein,

the storage structure penetrates through the fourth insulating layer, the isolation layer, the dielectric layer, the third insulating layer and part of the second insulating layer.

8. The semiconductor structure of claim 1, wherein,

The memory structure includes a capacitor structure including a first metal layer, a dielectric layer, and a second metal layer disposed in sequence.

9. The semiconductor structure of claim 1, wherein,

the substrate comprises a plurality of device structure layers which are sequentially stacked.

10. A method of forming a semiconductor structure, comprising:

providing a substrate;

forming a bit line on the substrate;

forming a contact plug on the bit line;

forming a word line on the active layer;

11. The method of claim 10, wherein the step of determining the position of the first electrode is performed,

12. The method of claim 10, wherein the step of determining the position of the first electrode is performed,

the forming a bit line includes:

forming a first insulating layer on the substrate;

and filling conductive materials in the first grooves to form bit lines.

13. The method of claim 12, wherein the step of determining the position of the probe is performed,

the forming of the contact plug includes:

forming a second insulating layer on the first insulating layer;

14. The method of claim 13, wherein the step of determining the position of the probe is performed,

the forming an active layer includes:

forming a third insulating layer on the second insulating layer;

15. The method of claim 14, wherein the step of providing the first information comprises,

the forming a word line includes:

forming a dielectric layer on the third insulating layer;

16. The method of claim 15, wherein the step of determining the position of the probe is performed,

The forming a memory structure includes:

forming isolation layers on the dielectric layer and the word lines;

forming a fourth insulating layer on the isolation layer;

and forming a storage structure in the second through hole.

17. The method of claim 16, wherein the step of determining the position of the probe comprises,

the forming a storage structure in the second through hole comprises the following steps: