CN117334693A - Semiconductor preparation method, semiconductor structure and chip - Google Patents

Semiconductor preparation method, semiconductor structure and chip Download PDF

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Publication number
CN117334693A
CN117334693A CN202311319773.1A CN202311319773A CN117334693A CN 117334693 A CN117334693 A CN 117334693A CN 202311319773 A CN202311319773 A CN 202311319773A CN 117334693 A CN117334693 A CN 117334693A
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transistor
epitaxial structure
layer
bdi
substrate
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CN117334693B (en
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吴恒
张磊
黎明
王润声
黄如
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Peking University
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Peking University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The application provides a semiconductor preparation method, a semiconductor structure and a chip. The method comprises the following steps: forming a first transistor and a second transistor on a first substrate, wherein a BDI layer is formed between the first transistor and the second transistor and the first substrate; rewinding the wafer with the first substrate; removing the first substrate to expose the BDI layer; removing a part corresponding to the first transistor in the BDI layer to expose a first epitaxial structure of the first transistor, wherein the first epitaxial structure forms a source electrode and/or a drain electrode of the first transistor; a second epitaxial structure is formed over the first epitaxial structure, wherein the first epitaxial structure and the second epitaxial structure form an electrostatic discharge path. By the scheme, the ESD protection can be provided for the GAA transistor with the BDI layer.

Description

Semiconductor preparation method, semiconductor structure and chip
Technical Field
The present application relates to the field of semiconductor technology, and in particular, to a semiconductor fabrication method, a semiconductor structure, and a chip.
Background
A Gate-All-Around NanoSheet (GAA NA) structured field effect transistor (Field Effect Transistor, FET), otherwise known as GAA-FET, is capable of carrying larger currents and maintaining smaller dimensions. GAA transistors have evolved on the basis of fin field effect transistors. Fin field effect transistors are also known as finfets. The GAA transistor reduces the supply voltage and enhances the current driving capability compared to the fin field effect transistor, thereby further improving the performance. In particular, GAA-FETs have better electrostatic properties than FinFETs.
The use of GAA transistors in large scale, even very large scale, integrated circuits may cause severe bottom parasitic channel leakage. To address this problem, a bottom dielectric isolation (Bottom Dielectric Isolation, BDI) layer is provided under the source, drain, gate, etc. regions of the GAA transistor.
In everyday use, electrostatic discharge (Electro Static Discharge, ESD) tends to interfere with the normal operation of a semiconductor device and even damage the semiconductor device. In general, a diode having a substrate as a current drain path may be prepared to achieve electrostatic protection.
However, since the BDI layer is disposed between the GAA transistor and the underlying substrate, the underlying substrate cannot serve as a bleed-off path for the electrostatic discharge current. How to protect the GAA transistor with BDI layer from ESD is a problem to be solved.
Disclosure of Invention
The present application relates to a semiconductor fabrication method, semiconductor structure and chip to provide ESD protection for GAA transistors with BDI layers.
In a first aspect, the present application provides a semiconductor fabrication method. The method comprises the following steps: forming a first transistor and a second transistor on a first substrate, wherein a BDI layer is formed between the first transistor and the second transistor and the first substrate; rewinding the wafer with the first substrate; removing the first substrate to expose the BDI layer; removing a part corresponding to the first transistor in the BDI layer to expose a first epitaxial structure of the first transistor, wherein the first epitaxial structure forms a source electrode and/or a drain electrode of the first transistor; a second epitaxial structure is formed over the first epitaxial structure, wherein the first epitaxial structure and the second epitaxial structure form an electrostatic discharge path.
In some possible embodiments, removing the portion of the BDI layer corresponding to the first transistor to expose the first epitaxial structure of the first transistor may include: forming a positive photoresist on a portion of the BDI layer corresponding to the second transistor; and etching the BDI layer to remove the part, corresponding to the first transistor, of the BDI layer.
In some possible embodiments, the first epitaxial structure may be a P-type epitaxial structure and the second epitaxial structure may be an N-type epitaxial structure.
In some possible embodiments, the first epitaxial structure may be an N-type epitaxial structure and the second epitaxial structure may be a P-type epitaxial structure.
In some possible embodiments, after forming the second epitaxial structure on the first epitaxial structure, the method may further include: an isolation layer is formed over the first transistor and the second transistor, wherein the BDI layer is located between the second transistor and the isolation layer and the second epitaxial structure passes through the isolation layer and contacts the first epitaxial structure of the first transistor.
In a second aspect, the present application provides a semiconductor structure. The semiconductor structure includes a second substrate, a first transistor, a second transistor, a BDI layer, and a second epitaxial structure. The first transistor and the second transistor are flip-chip arranged on the second substrate. The BDI layer is disposed on the second transistor. The second epitaxial structure is disposed on the first epitaxial structure of the first transistor. The first epitaxial structure constitutes a source and/or a drain of the first transistor. The first epitaxial structure and the second epitaxial structure form an electrostatic discharge path.
In some possible embodiments, the first epitaxial structure may be a P-type epitaxial structure and the second epitaxial structure may be an N-type epitaxial structure.
In some possible embodiments, the first epitaxial structure may be an N-type epitaxial structure and the second epitaxial structure may be a P-type epitaxial structure.
In some possible embodiments, the first epitaxial structure and the second epitaxial structure are stacked in a vertical direction.
In a third aspect, the present application provides a chip. The chip comprises a semiconductor structure as described in the second aspect.
By the scheme of the application, the semiconductor structure comprises a first transistor and a second transistor. The first epitaxial structure of the first transistor can form an electrostatic discharge path with the second epitaxial structure in a region corresponding to the first transistor, the path being capable of bleeding off ESD current, thereby providing ESD protection for the semiconductor structure.
In addition, the first epitaxial structure and the second epitaxial structure in the semiconductor structure are stacked. Therefore, the conducting channel of the diode formed by the first epitaxial structure and the second epitaxial structure extends along the vertical direction, so that a smaller area is occupied, and the occupied area of the semiconductor structure is reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
Fig. 1 is a schematic layout of a semiconductor structure provided in an embodiment of the present application.
Fig. 2 is a cross-sectional view of a first embodiment of a semiconductor structure provided in an embodiment of the present application.
Fig. 3 is a cross-sectional view of a second embodiment of a semiconductor structure provided in an embodiment of the present application.
Fig. 4 is a flow chart of a semiconductor manufacturing method provided in an embodiment of the present application.
Fig. 5A to 5I are schematic views of respective steps of a semiconductor manufacturing method provided in an embodiment of the present application.
Reference numerals illustrate:
g: a gate; NS: a nanosheet; 100: a first transistor; 101: a first epitaxial structure; 102: a metal; 110: a first laminated structure; 111: a Si layer; 112: a SiGe layer; 200: a second transistor; 201: a third epitaxial structure; 202: a metal; 210: a second laminated structure; s1: a first substrate; s2: a second substrate; 3: a BDI layer; 4: a second epitaxial structure; 5: an isolation layer; 6: a metal; 7: an oxide layer; 8: a sacrificial layer; 9: a metal gate; 10: a nitride layer; 11: an oxide layer; 12: positive photoresist.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same reference numerals in different drawings may refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application.
First, the embodiment of the application provides a semiconductor structure. Fig. 1 is a schematic layout of a semiconductor structure provided in an embodiment of the present application. As shown in fig. 1, the semiconductor structure includes a first transistor 100 and a second transistor 200.
The first transistor 100 is used for ESD protection. The first transistor 100 may be referred to as an ESD transistor or an ESD device. The region where the first transistor 100 is located is shown by the dashed box identified by 100 in the figure. The first transistor 100 includes a gate structure G and a nano-sheet (NS).
The second transistor 200 is used to perform normal transistor functions, e.g., switching, amplifying, etc. The region where the second transistor 200 is located is shown by the dashed box identified in figure 200. The second transistor 200 includes a gate structure G and a nano-sheet NS.
In an embodiment, the first transistor 100 and/or the second transistor 200 may be GAA transistors. For example, the first transistor 100 and/or the second transistor 200 may be nanoflake field effect transistors. For example, the first transistor 100 and/or the second transistor 200 may be nanowire field effect transistors. Of course, the first transistor 100 and/or the second transistor 200 may be other types of transistors, which are not specifically limited in the embodiments of the present application.
In the semiconductor structure, the number of the first transistors 100 may be one or more, and the number of the second transistors 200 may be one or more. In an embodiment, the number of first transistors 200 may be much greater than the number of first transistors 100. For example, the number of first transistors 200 may be an order of magnitude greater than the number of first transistors 100. In an embodiment, the size of the first transistor 200 may be larger than the size of the first transistor 100. For example, the area occupied by the first transistor 200 may be much larger than the area occupied by the first transistor 100.
The first transistor 100 may implement electrostatic discharge in case that a preset condition is satisfied. In one embodiment, the preset condition may be related to a supply voltage (e.g., VDD). In an example, the first transistor 100 may implement electrostatic discharge in the case where the voltage applied across the first transistor 100 exceeds a power supply voltage of 1.1 times or 1.2 times.
Fig. 2 is a cross-sectional view of a first embodiment of a semiconductor structure provided in an embodiment of the present application. The cross-sectional view for the first transistor 100 is taken along the A1-A1 'direction and the B1-B1' direction, respectively. The cross-sectional views for the second transistor 200 are taken along the A2-A2 'direction and the B2-B2' direction, respectively.
As shown in fig. 2, the semiconductor structure of the embodiment of the present application may include a second substrate S2, a first transistor 100, a second transistor 200, a BDI layer 3, and a second epitaxial structure 4.
The second substrate S2 is used to carry the first transistor 100 and the second transistor 200. In an embodiment, the second substrate S2 may be a carrier substrate. For example, the second substrate S2 may be a carrier wafer (carrier wafer) used in the fabrication of semiconductor structures.
The first transistor 100 and the second transistor 200 are flip-chip arranged on the second substrate S2. It will be appreciated that the term "flip-chip" in embodiments of the present application refers to a transistor being arranged upside down. Specifically, as shown in fig. 2, the metal 102 of the first transistor 100 forms a metal contact with the first epitaxial structure 101 under the transistor 100. Meanwhile, the metal 202 of the second transistor 200 forms a metal contact with the third epitaxial structure 201 under the transistor 200.
The BDI layer 3 is disposed on the second transistor 200. In one embodiment, the BDI layer 3 may be made of a low dielectric (low-K) material. For example, BDI layer 3 may be SiO 2 Or a dielectric film made of other materials.
In an embodiment, the first epitaxial structure 101 and the second epitaxial structure 4 may be stacked in a vertical direction. Specifically, the second epitaxial structure 4 is disposed on the first epitaxial structure 101 of the first transistor 100. The first epitaxial structure 101 constitutes the source and/or drain of the first transistor 100. The first epitaxial structure 101 and the second epitaxial structure 4 constitute an electrostatic discharge path. The first epitaxial structure 101 is an N-type epitaxial structure. The second epitaxial structure 4 is a P-type epitaxial structure. A PN junction is formed between the first epitaxial structure 101 and the second epitaxial structure 4. When reverse breakdown (e.g., zener breakdown) of the PN junction occurs due to static electricity, ESD current may flow from the first epitaxial structure 101 to the second epitaxial structure 4.
In an embodiment, the semiconductor structure may further comprise an isolation layer 5. The isolation layer 5 is disposed on the BDI layer 3 of the first transistor 100, the second transistor 200. The second epitaxial structure 4 passes through the isolation layer 5 and is in contact with the first epitaxial structure 101 of the first transistor 100. In one example, the metal 6 is disposed within the isolation layer 5 and in contact with the second epitaxial structure 4 and through the oxide layer 7. In an example, the upper surface of the second epitaxial structure 4 may be flush with the upper surface of the spacer layer 5 and in contact with the metal 6. At this time, the metal 6 may not protrude into the isolation layer 5. As such, metal 6 may draw ESD current from first transistor 100.
Fig. 3 is a cross-sectional view of a second embodiment of a semiconductor structure provided in an embodiment of the present application. The cross-sectional view for the first transistor 100 is taken along the A1-A1 'direction and the B1-B1' direction, respectively. The cross-sectional views for the second transistor 200 are taken along the A2-A2 'direction and the B2-B2' direction, respectively. The semiconductor structure in fig. 3 is substantially the same as the semiconductor structure in fig. 2. In the semiconductor structure of fig. 3, the first epitaxial structure 101 is a P-type epitaxial structure and the second epitaxial structure 4 is an N-type epitaxial structure, as compared to the semiconductor structure of fig. 2. A PN junction is formed between the first epitaxial structure 101 and the second epitaxial structure 4. Under the effect of this PN junction, ESD current can flow from the second epitaxial structure 4 to the first epitaxial structure 101.
In the embodiment of the application, the semiconductor structure can be applied to semiconductor devices such as memories, processors and the like. In particular, the semiconductor structure described above may be used to implement a chip. In other words, the semiconductor structure of embodiments of the present application may be included in a packaged chip.
The embodiment of the application also provides a semiconductor preparation method. The method is used for preparing the semiconductor structure in the embodiment of the application. Fig. 4 is a flow chart of a semiconductor manufacturing method provided in an embodiment of the present application. As shown in fig. 4, the semiconductor manufacturing method of the embodiment of the present application includes steps S410 to S450.
In step S410, a first transistor and a second transistor are formed on a first substrate.
In this step, a first substrate may be provided, and a first transistor and a second transistor may be formed over the first substrate.
In one embodiment, the first substrate may be made of various materials. For example, the first substrate may be a silicon substrate, a germanium substrate. At this time, the first substrate may be a substrate formed of a silicon wafer, a germanium wafer, or the like. For another example, the first substrate may be a silicon-on-insulator (SOI) substrate. In this case, the first substrate may be a substrate obtained by processing a silicon wafer.
In an embodiment, the first transistor and the second transistor formed over the first substrate may be different in size, number, position, and the like. For example, the size of the first transistor may be larger than the size of the second transistor. For example, the number of first transistors may be less than the number of second transistors. For example, the first transistor may be located adjacent to or remote from the second transistor.
In one placeIn an embodiment, the first transistor and the second transistor are formed with a BDI layer. More specifically, a BDI layer is formed between the first transistor and the second transistor and the first substrate. The BDI layer is a dielectric layer and separates the first transistor and the second transistor from the substrate. In one embodiment, the BDI layer may be formed of, for example, siO 2 Such as a low dielectric material.
In step S420, the wafer on which the first substrate is located is rewound.
In this step, the wafer on which the first transistor and the second transistor are formed is rewound to achieve that the first substrate is inverted in the up-down direction (or referred to as the vertical direction). The first transistor and the second transistor are flip-chip arranged via the rewinding. The rewound wafer may be carried on a carrier wafer. The carrier wafer constitutes a second substrate. As such, the first transistor and the second transistor are flip-chip arranged on the second substrate.
Obviously, after step S420 is completed, the first substrate, the first transistor and the second transistor, and the second substrate are sequentially stacked in order from top to bottom. Thus, the first substrate is positioned above the first transistor and the second transistor to continue the subsequent preparation process.
In step S430, the first substrate is removed.
In this step, the first substrate is removed to expose the BDI layer. Specifically, portions of the BDI layer on both the first transistor and the second transistor are exposed.
In an embodiment, the first substrate may be removed by mechanical or chemical means. For example, the first substrate may be removed by mechanical polishing. For example, the first substrate may be removed by chemical-mechanical planarization (CMP).
In step S440, a portion of the BDI layer corresponding to the first transistor is removed.
In this step, the portion of the BDI layer corresponding to the first transistor is removed, and the portion of the BDI layer corresponding to the second transistor is reserved.
In an embodiment, step S440 may be implemented by using a photolithography process.
In one embodiment, the photolithography process may use positive photoresist. Correspondingly, step S440 may include: forming a positive photoresist on a portion of the BDI layer corresponding to the second transistor; and etching the BDI layer to remove the part, corresponding to the first transistor, of the BDI layer. Specifically, a positive photoresist is coated on the BDI layer of the semiconductor structure. Thereafter, the positive photoresist is exposed to light using a mask to pattern the positive photoresist. The portion of the positive photoresist corresponding to the first transistor is not exposed and the portion corresponding to the second transistor is exposed. The exposed portions of the positive photoresist remain and the unexposed portions are removed. The patterned positive photoresist exposes portions of the BDI layer corresponding to the first transistors and covers portions corresponding to the second transistors. Next, the BDI layer is etched. The portion of the BDI layer corresponding to the first transistor is etched. The portion of the BDI layer corresponding to the second transistor is not etched due to the protection of the positive photoresist. In this way, only the portion of the BDI layer corresponding to the first transistor is removed.
In one embodiment, the photolithography process may use a negative photoresist. Correspondingly, step S440 may include: forming a negative photoresist on a portion of the BDI layer corresponding to the first transistor; and etching the BDI layer to remove the part, corresponding to the first transistor, of the BDI layer. Specifically, a negative photoresist is coated on the BDI layer of the semiconductor structure. Thereafter, the negative photoresist is exposed to light using a mask (mask) to pattern the negative photoresist. The portion of the negative photoresist corresponding to the first transistor is exposed and the portion corresponding to the second transistor is not exposed. The exposed portions of the negative photoresist are removed and the unexposed portions remain. The patterned negative photoresist exposes portions of the BDI layer corresponding to the first transistor and portions corresponding to the second transistor. Next, the BDI layer is etched. The portion of the BDI layer corresponding to the first transistor is etched. The portion of the BDI layer corresponding to the second transistor is not etched due to the protection of the negative photoresist. In this way, only the portion of the BDI layer corresponding to the first transistor is removed.
After removing the portion of the BDI layer corresponding to the first transistor, the first epitaxial structure of the first transistor is exposed. In an embodiment, the first epitaxial structure may constitute a source and/or a drain within the first transistor.
In step S450, a second epitaxial structure is formed on the first epitaxial structure.
In this step, the material used to form the second epitaxial structure and the material used to form the first epitaxial structure may have opposite conductivity types. Here, the conductivity type refers to conductivity with electrons or conductivity with holes. Then the conductivity type is N-type or P-type, respectively. In one embodiment, the first epitaxial structure and the second epitaxial structure are N-type and P-type, respectively. In one embodiment, the first epitaxial structure and the second epitaxial structure are P-type and N-type, respectively. A PN junction is formed from the first epitaxial structure and the second epitaxial structure. The direction of current flow in the PN junction may be from bottom to top, or from top to bottom.
In an embodiment, the semiconductor manufacturing method further includes: an isolation layer is formed over the first transistor and the second transistor. In this step, an isolation layer is formed over the semiconductor structure. The isolation layer is used for isolating the semiconductor structure from the surrounding environment. In embodiments of the present application, "isolation" may include, but is not limited to, physical isolation, electrical isolation, chemical isolation.
In an embodiment, a metal contact may also be formed on the second epitaxial structure of the first transistor for extracting ESD current before performing step S450. The metal used to form the metal contact with the second epitaxial structure may be tungsten, copper, silver, or the like.
Hereinafter, a method for manufacturing the semiconductor structure in the embodiment of the present application is described in detail.
Fig. 5A to 5G are schematic views of respective steps of a semiconductor manufacturing method provided in an embodiment of the present application. Various steps of the fabrication method shown in fig. 5A to 5G may be used to fabricate the semiconductor structure shown in fig. 2.
In a first step, a first stacked structure 110 and a second stacked structure 210 are formed on a substrate S1 (i.e., a first substrate) (see fig. 5A).
In one embodiment, the substrate S1 may be implemented by a silicon wafer. In one embodiment, the substrate S1 may be implemented as SOI. In one embodiment, the substrate S1 may be implemented by a Ge wafer.
In this step, a layer of SiGe is formed as the sacrificial layer 8 on the substrate S1. A first laminated structure 110 and a second laminated structure 210 are formed on the sacrificial layer 8. The first and second stacked structures 110 and 210 each include a plurality of Si layers 111 and a plurality of SiGe layers 112. The plurality of SiGe layers 112 and the plurality of Si layers 111 are staggered in the vertical direction. Adjacent two Si layers 111 are separated by a SiGe layer 112.
In an embodiment, the sacrificial layer 8 may be different from the SiGe layers of the first and second stacked structures 110 and 210 in the concentration of SiGe. For example, the concentration of SiGe in the sacrificial layer 8 may be greater than or equal to 70%, such as about 70%. The concentration of SiGe in the SiGe layers of the first and second stacked structures 110 and 210 may be about 30%. It should be noted that "concentration" in the embodiments of the present application may be a weight ratio.
In the second step, the first transistor 100 and the second transistor 200 are formed based on the first stacked structure 110 and the second stacked structure 210, respectively (see fig. 5B), and the nitride layer 10 and the oxide layer 11 are formed (see fig. 5C).
Specifically, the processing is performed in common based on the first laminated structure 110 and the second laminated structure 210. A gate structure and a source drain structure 101 are formed. Metal replacement gates (replacement metal gate, RMG) are performed to form metal gates 9. The middle-of-line (MOL) and back-end-of-line (BEOL) processes are performed. A nitride layer 10 and an oxide layer 11 are formed.
In one embodiment, the metal gate 9 may be made of a high-K material.
The nitride layer 10 and the oxide layer 11 each serve as a dielectric layer. In one embodiment, the nitride layer 10 may be made of SiCN. In one embodiment, the thickness of nitride layer 10 may be about 50 nanometers. In one embodiment, the oxide layer may be made of SiO 2 Is prepared. In one embodiment, the thickness of the oxide layer 11 may beIs about 150 nanometers.
In this step, the sacrifice layer 8 is removed, and the BDI layer 3 is formed at the position of the sacrifice layer 8. In an embodiment, the BDI layer 3 may be made of a low K material.
In a third step, the wafer is rewound (see fig. 5D).
In this step, the wafer on which the substrate S1 is located is rewound and carried on a carrier wafer by wafer bonding. The carrier wafer constitutes a substrate S2 (i.e., a second substrate).
In the fourth step, the substrate S1 is removed (see fig. 5E).
In this step, wafer thinning may be performed to remove the substrate S1 over the first transistor 100 and the second transistor 200.
In one embodiment, wafer thinning may be achieved mechanically. For example, the substrate S1 may be removed by cutting, grinding, or the like. In one embodiment, wafer thinning may be achieved by mechanochemical means. For example, the substrate S1 may be removed by CMP.
In the fifth step, the positive photoresist 12 is formed on the second transistor 200 (see fig. 5F), the BDI layer 3 is removed and the positive photoresist 12 is removed (see fig. 5G).
Specifically, the coated positive photoresist 12 is formed on the BDI layer 3 corresponding to the first transistor 100 and the second transistor 200. The portion of the positive photoresist 12 above the second transistor 200 is exposed to light using a mask so that the portion of the positive photoresist 12 above the second transistor 200 is hardened. Thereafter, the positive photoresist 12 is dissolved. The portions of the positive photoresist 12 other than the hardened portion above the second transistor 200 are dissolved, including the portions of the positive photoresist 12 above the first transistor 100. To this end, the positive photoresist 12 is patterned.
In one embodiment, a layer of photoresist may also be formed between the positive photoresist 12 and the BDI layer 3. Photoresist may be used to eliminate standing wave effects.
After the positive photoresist 12 is patterned, the BDI layer 3 may be etched under the effect of the positive photoresist 12. In an embodiment, the BDI layer 3 may be etched by dry etching or wet etching, thereby etching away the portion of the BDI layer 3 on the first transistor 100. Next, the positive photoresist 12 on the second transistor 200 may be removed.
In a sixth step, a second epitaxial structure 4 is formed (see fig. 5H).
After the fifth step is completed, the first epitaxial structure 101 of the first transistor 100 is exposed. The first epitaxial structure 101 is an N-type epitaxial structure. Next, in a sixth step, the formation of the second epitaxial structure 4 on the first epitaxial structure 101 is removed. The second epitaxial structure 4 is a P-type epitaxial structure.
In an embodiment, the second epitaxial structure 4 may be formed by epitaxial growth.
In the seventh step, an isolation layer 5 is formed over the first transistor 100 and the second transistor 200 (see fig. 5I).
In this step, a metal 6 is further formed on the second epitaxial structure 4, and an isolation layer 5 is formed on the first transistor 100 and the second transistor 200. The isolation layer 5 may be made of nitride. The isolation layer 5 may cover the first transistor 100. The second epitaxial structure 4 and the metal 6 together pass through the isolation layer 5. The second epitaxial structure 4 and the metal 6 form a metal contact in the isolation layer 5. The metal 6 leads out the second epitaxial structure 4. Furthermore, the isolation layer 6 may cover the BDI layer 3 on the second transistor 200.
Thereafter, an oxide layer 7 may be formed on the isolation layer 5. The metal 6 may pass through the oxide layer 7.
The semiconductor structure obtained by the manufacturing method shown in the present exemplary embodiment includes the first transistor 100 and the second transistor 200. The first epitaxial structure 101 of the first transistor 100 forms a PN junction with the corresponding second epitaxial structure 4. The PN junction, when used as an ESD path, may have a direction of ESD current flowing from the first epitaxial structure 101 to the second epitaxial structure 4. A BDI layer 3 is disposed over the second transistor 200. Thus, the first transistor 100 having ESD effect and the second transistor 200 having BDI layer 3 can be simultaneously fabricated on the same wafer.
It is appreciated that in an embodiment, the first epitaxial structure 101 of the first transistor 100 may be a P-type epitaxial structure. The second epitaxial structure 4 may be an N-type epitaxial structure. The first epitaxial structure 101 and the second epitaxial structure 4 may form a PN junction. The PN junction, when used as an ESD path, may have a direction of ESD current flowing from the second epitaxial structure 4 to the first epitaxial structure 101.
In the description of the present application, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present application. In this application, the schematic representations of the above terms are not necessarily for the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the various embodiments or examples described herein, as well as the features of the various embodiments or examples, may be combined by those skilled in the art without contradiction.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations can be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims (10)

1. A method of manufacturing a semiconductor, comprising:
forming a first transistor and a second transistor on a first substrate, wherein a bottom dielectric isolation BDI layer is formed between the first transistor and the first substrate and between the second transistor and the first substrate;
rewinding the wafer where the first substrate is located;
removing the first substrate to expose the BDI layer;
removing a part of the BDI layer corresponding to the first transistor to expose a first epitaxial structure of the first transistor, wherein the first epitaxial structure forms a source electrode and/or a drain electrode of the first transistor;
a second epitaxial structure is formed over the first epitaxial structure, wherein the first epitaxial structure and the second epitaxial structure form an electrostatic discharge path.
2. The method of claim 1, wherein the removing the portion of the BDI layer corresponding to the first transistor to expose the first epitaxial structure of the first transistor comprises:
forming a positive photoresist on a portion of the BDI layer corresponding to the second transistor;
and etching the BDI layer to remove the part, corresponding to the first transistor, of the BDI layer.
3. The method of claim 1, wherein the first epitaxial structure is a P-type epitaxial structure and the second epitaxial structure is an N-type epitaxial structure.
4. The method of claim 1, wherein the first epitaxial structure is an N-type epitaxial structure and the second epitaxial structure is a P-type epitaxial structure.
5. The method of any of claims 1-4, wherein after the forming a second epitaxial structure on the first epitaxial structure, the method further comprises:
an isolation layer is formed over the first transistor and the second transistor, wherein the BDI layer is located between the second transistor and the isolation layer, and the second epitaxial structure passes through the isolation layer and contacts the first epitaxial structure of the first transistor.
6. A semiconductor structure, comprising:
a second substrate;
a first transistor and a second transistor flip-chip arranged on the second substrate;
a BDI layer disposed on the second transistor;
and the second epitaxial structure is arranged on the first epitaxial structure of the first transistor, wherein the first epitaxial structure forms a source electrode and/or a drain electrode of the first transistor, and the first epitaxial structure and the second epitaxial structure form an electrostatic discharge path.
7. The semiconductor structure of claim 6, wherein the first epitaxial structure is a P-type epitaxial structure and the second epitaxial structure is an N-type epitaxial structure.
8. The semiconductor structure of claim 6, wherein the first epitaxial structure is an N-type epitaxial structure and the second epitaxial structure is a P-type epitaxial structure.
9. The semiconductor structure of any one of claims 6-8, wherein the first epitaxial structure and the second epitaxial structure are stacked in a vertical direction.
10. A chip, characterized in that it comprises a semiconductor structure according to any of claims 6 to 9.
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