CN117334668A - Semiconductor structure and preparation method thereof - Google Patents

Semiconductor structure and preparation method thereof Download PDF

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Publication number
CN117334668A
CN117334668A CN202210680638.9A CN202210680638A CN117334668A CN 117334668 A CN117334668 A CN 117334668A CN 202210680638 A CN202210680638 A CN 202210680638A CN 117334668 A CN117334668 A CN 117334668A
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China
Prior art keywords
layer
semiconductor substrate
conductive connection
forming
semiconductor
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CN202210680638.9A
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Chinese (zh)
Inventor
林超
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202210680638.9A priority Critical patent/CN117334668A/en
Priority to US17/945,113 priority patent/US20230013735A1/en
Publication of CN117334668A publication Critical patent/CN117334668A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present disclosure relates to a semiconductor structure and a method of fabricating the same. The semiconductor structure is provided with an array area and a peripheral area, and comprises: a semiconductor substrate; a memory array structure located over the semiconductor substrate of the array region; a peripheral circuit structure located over the semiconductor substrate of the peripheral region; and the conductive connection structure is positioned in the semiconductor substrate and electrically connects the storage array structure and the peripheral circuit structure. The embodiment of the disclosure can effectively improve the performance of the memory device.

Description

Semiconductor structure and preparation method thereof
Technical Field
The disclosure relates to the technical field of semiconductors, and in particular relates to a semiconductor structure and a preparation method thereof.
Background
Semiconductor memory devices generally include an array region and a peripheral region. The array area is provided with a storage array structure, and the peripheral area is provided with a peripheral circuit structure. The peripheral circuit structure may control individual memory cells in the memory array structure.
In the current memory device, after the memory array structure is formed, a dielectric layer is etched downwards from above the memory array structure to form a contact hole structure, and then a conductive layer is formed above the contact hole structure to connect the relevant contact hole structure, so as to electrically connect the memory array structure and the peripheral circuit structure.
But such a connection may affect device performance in some cases. For example, for a three-dimensional memory device, since it has a multi-layered stacked structure, a contact hole structure is caused to be long, and thus a large RC delay may be generated.
Disclosure of Invention
Based on the above, the embodiment of the disclosure provides a semiconductor structure and a preparation method thereof.
A semiconductor structure having an array region and a peripheral region, comprising:
a semiconductor substrate;
a memory array structure located over the semiconductor substrate of the array region;
a peripheral circuit structure located over the semiconductor substrate of the peripheral region;
and the conductive connection structure is positioned in the semiconductor substrate and electrically connects the storage array structure and the peripheral circuit structure.
In one embodiment, the memory array structure includes memory cells arranged in a multi-layer stack.
In one embodiment, the semiconductor substrate is provided with a trench, and the conductive connection structure is located in the trench.
In one embodiment, the trench is located between the array region and the peripheral region.
In one embodiment, an isolation protection layer is further disposed between the conductive connection structure and the trench.
In one embodiment, the isolation protection layer includes a first oxide layer, a second oxide layer, and a nitride layer, the first oxide layer is located on the surface of the trench, and the nitride layer is located between the first oxide layer and the second oxide layer.
In one embodiment, the first oxide layer extends from within the trench to the upper surface of the semiconductor substrate in the peripheral region.
In one embodiment, a filling layer is further disposed in the trench, and the filling layer is located on the surface of the conductive connection structure and fills the trench.
In one embodiment, the semiconductor structure further comprises:
a connecting line structure electrically connecting the peripheral circuit structure and the conductive connection structure;
and a bit line electrically connecting the conductive connection structure with the transistor source region or drain region of the memory cell of each layer.
A method of fabricating a semiconductor structure, the semiconductor structure comprising an array region and a peripheral region, the method comprising:
providing a semiconductor substrate;
forming a conductive connection structure in the semiconductor substrate;
forming a peripheral circuit structure over the semiconductor substrate of the peripheral region and electrically connecting the peripheral circuit structure with the conductive connection structure;
a memory array structure is formed over the semiconductor substrate of the array region and electrically connected to the conductive connection structure.
In one embodiment, the memory array structure includes memory cells arranged in a multi-layer stack.
In one embodiment, the forming a conductive connection structure in the semiconductor substrate includes:
forming a groove in the semiconductor substrate;
and forming the conductive connection structure in the groove.
In one embodiment, the trench is located between the array region and the peripheral region.
In one embodiment, before the forming of the conductive connection structure in the trench, the method further includes:
and forming an isolation protection layer on the surface of the groove.
In one embodiment, the forming the isolation protection layer on the surface of the trench includes:
forming an isolation protection material layer on the surface of the groove and the upper surface of the semiconductor substrate, wherein the isolation protection material layer comprises a first oxide layer, a nitride layer and a second oxide layer which are sequentially formed, and the second oxide layer fills the groove;
performing chemical mechanical polishing on the isolation protection material layer, wherein the chemical mechanical polishing stops on the first oxide layer;
and carrying out patterning treatment on the second oxide layer after chemical mechanical polishing.
In one embodiment, after the forming the conductive connection structure in the trench, the method further includes:
and forming a filling layer in the groove.
In one embodiment, the forming a peripheral circuit structure over the semiconductor substrate of the peripheral region, and electrically connecting the peripheral circuit structure with the conductive connection structure comprises:
forming a peripheral circuit structure over the semiconductor substrate of the peripheral region;
forming a first dielectric layer in the peripheral region and the array region, wherein the first dielectric layer covers the peripheral circuit structure;
forming a first interconnection hole and a second interconnection hole in the first dielectric layer, wherein the first interconnection hole is communicated with the peripheral circuit structure, and the second interconnection hole is communicated with the conductive connection structure;
and forming a connecting wire structure on the first dielectric layer, wherein the connecting wire structure is electrically connected with the peripheral circuit structure and the conductive connecting structure through the first interconnection hole and the second interconnection hole.
In one of the embodiments of the present invention,
after the connecting line structure is formed on the first dielectric layer, the method further comprises:
forming a second dielectric layer on the upper surface of the first dielectric layer and the upper surface of the connecting wire structure;
patterning the first dielectric layer and the second dielectric layer to expose the semiconductor substrate of the array region;
forming a memory array structure over the semiconductor substrate of the array region and electrically connecting the memory array structure with the conductive connection structure, comprising:
forming a memory array structure over the exposed semiconductor substrate of the array region;
forming a third dielectric layer on the storage array structure and the second dielectric layer;
forming a bit line hole penetrating through the third dielectric layer, the second dielectric layer and the first dielectric layer, wherein the bit line hole is communicated with the conductive connection structure and a transistor source region or a transistor drain region of each layer of the memory unit;
and forming a bit line in the bit line hole.
According to the semiconductor structure and the preparation method thereof, the conductive connection structure is formed in the semiconductor substrate, so that the contact hole structure formed by punching above the memory array structure is avoided, and the device performance is effectively ensured. When the memory array structure has a three-dimensional structure, since the conductive connection structure is located within the semiconductor substrate, it is unnecessary to form a contact hole structure having a long height by being limited by the multi-layered stack structure of the memory array structure. At this time, the resistance between the memory array structure and the peripheral circuit structure can be effectively reduced, thereby effectively improving the RC delay phenomenon.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present disclosure, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to the drawings without inventive effort to those of ordinary skill in the art.
FIG. 1 is a flow chart of a method for fabricating a semiconductor structure according to one embodiment;
fig. 2 to 15 are schematic structural views of a semiconductor structure according to an embodiment in a process of manufacturing the semiconductor structure;
fig. 16 is a schematic structural diagram of a semiconductor structure provided in an embodiment.
Reference numerals illustrate:
100-semiconductor substrate, 100 a-trench, 200-conductive connection structure, 300-peripheral circuit structure, 400-memory array structure, 500-isolation protection layer, 510-first oxide layer, 520-nitride layer, 530-second oxide layer, 600-fill layer, 710-first dielectric layer, 710 a-first interconnect hole, 710 b-second interconnect hole, 720-second dielectric layer, 730-third dielectric layer, 800-connection line structure, 810-conductive plug, 820-connection conductive layer, 900-bit line, 900 a-bit line hole, 10-second patterned photoresist layer, 20-third patterned photoresist layer, 30-fourth patterned photoresist layer.
Detailed Description
In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the following embodiments, "connection" is understood to mean "electrical connection" or the like if there is an electrical signal between objects to be connected.
In one embodiment, referring to fig. 1, a method for fabricating a semiconductor structure is provided. Referring to fig. 16, the semiconductor structure includes an array region and a peripheral region. The preparation method of the semiconductor structure comprises the following steps:
step S200, providing a semiconductor substrate 100;
step S400, please refer to fig. 6, forming a conductive connection structure 200 in the semiconductor substrate 100;
step S600, please refer to fig. 10, forming a peripheral circuit structure 300 over the semiconductor substrate 100 in the peripheral region, and electrically connecting the peripheral circuit structure 300 with the conductive connection structure 200;
in step S800, referring to fig. 16, a memory array structure 400 is formed over the semiconductor substrate 100 in the array region, and the memory array structure 400 is electrically connected to the conductive connection structure 200.
In step S200, the material of the semiconductor substrate 100 may include, but is not limited to, silicon, germanium, silicon germanium, gallium nitride, gallium arsenide, indium gallium arsenide, silicon carbide, and the like.
In step S400, the material of the conductive connection structure 200 may include, but is not limited to, metal (e.g., tungsten, molybdenum), metal nitride (e.g., titanium nitride), metal silicide (e.g., cobalt silicide), etc. And the conductive connection structure 200 may have a single-layer structure or a multi-layer structure.
Referring to fig. 6, the conductive connection structure 200 is formed in the semiconductor substrate 100, i.e., the conductive connection structure 200 is embedded in the semiconductor substrate 100.
In step S600, the peripheral circuit structure 300 may be formed through a plurality of process steps. In fig. 7-16, the specific structure of the peripheral circuit structure 300 is not shown for clarity of illustration.
The peripheral circuit structure 300 may include a logic circuit formed of a metal layer. Logic circuitry may control the memory array. Also, the peripheral circuit structure 300 may further include a peripheral dielectric layer. The peripheral dielectric layer can be insulated and isolated at the part where the circuit is not formed, and can cover the peripheral circuit structure so as to protect the peripheral circuit structure. In particular, the peripheral dielectric layer may include a plurality of dielectric layers formed by a plurality of process steps.
The peripheral circuit structure 300 is electrically connected with the conductive connection structure 200. Specifically, the conductive connection structure 200 may be electrically connected to a logic circuit formed by a metal layer of the peripheral circuit structure 300. The electrical connection may be direct connection or may be through other conductive structures, which is not limited herein.
In step S800, the memory array structure 400 may be formed by processing through a plurality of related process steps.
As an example, referring to fig. 13 through 16, the memory array structure 400 may have a three-dimensional structure, which may include a plurality of memory cells arranged in a stack. The memory cell includes a transistor 410 and a memory element 420. The transistors may include, for example, fully-enclosed Gate (GAA) transistors, thereby improving device integration. The memory element may comprise, for example, a capacitor.
It should be noted that the memory array structure 400 is not limited to the memory array structure 400 having a three-dimensional structure, and may have a two-dimensional structure, for example. The transistor is not limited to the GAA transistor, and for example, the gate thereof may be in contact with only one side of the semiconductor layer. The storage element is also not limited to being a capacitor, for example it may also be a magnetic tunnel junction.
The memory array structure 400 and the conductive connection structure 200 may be electrically connected by a bit line or a word line. The bit line or word line and the like may be directly connected to the conductive connection structure 20 or may be electrically connected to the conductive connection structure 200 through other conductive structures, which is not limited thereto.
In the present embodiment, by forming the conductive connection structure 200 in the semiconductor substrate 100, the formation of the contact hole structure by punching from above the memory array structure 400 is avoided, thereby effectively ensuring the device performance. When the memory array structure 400 has a three-dimensional structure, since the conductive connection structure 200 is located within the semiconductor substrate 100, it is not necessary to form a contact hole structure having a long height by being limited by the multi-layered stacked structure of the memory array structure 400. At this time, the resistance between the memory array structure and the peripheral circuit structure can be effectively reduced, thereby effectively improving the RC delay phenomenon.
In one embodiment, step S400 includes:
step S410, please refer to fig. 2, forming a trench 100a in the semiconductor substrate 100;
in step S420, referring to fig. 6, a conductive connection structure 200 is formed in the trench 100a.
In step S410, a first patterned photoresist layer may be formed on the semiconductor substrate 100 through a photolithography process, and an opening region of the first patterned photoresist layer defines a position of the trench 100a. The original semiconductor substrate 100 may then be etched based on the first patterned photoresist layer, thereby forming the trench 100a, and then the first patterned photoresist layer may be removed. The etching may be a dry etching, so that the size and shape of the trench 100a may be well controlled. Of course, wet etching may be performed, without limitation.
The depth of the groove 100a may be set according to practical requirements, for example, it may be set to be greater than
Meanwhile, as an example, a plurality of trenches 100a arranged in parallel may be provided in the semiconductor substrate 100. The number of trenches 100a may be the same as the number of bit lines connecting the memory array structure 400.
In step S420, the conductive connection structure 200 may be formed in the trench 100a by chemical vapor deposition or the like.
Referring to fig. 6, when a plurality of trenches 100a are disposed in the semiconductor substrate 100, a conductive connection structure 200 is formed in each trench, so that a plurality of conductive connection structures 200 can be formed in parallel.
In the present embodiment, by forming the trench 100a in the semiconductor substrate 100a, the conductive connection structure 200 is formed in the trench 100a, thereby effectively realizing embedding of the conductive connection structure 200 in the semiconductor substrate 100.
Of course, in some embodiments, the conductive connection structure 200 may also extend from within the trench 100a to above a portion of the semiconductor substrate outside the trench.
In one embodiment, the trench 100a is located between the array region and the peripheral region, so that the conductive connection structure 200 may be electrically connected to the peripheral circuit structure 300 and the memory array structure 400 at opposite ends thereof, respectively, so that the resistance between the peripheral circuit structure 300 and the memory array structure 400 may be minimized.
Of course, in other embodiments, the trench 100a may be disposed relatively close to both the array region and the peripheral region, but is not located between the array region and the peripheral region, which is not limited thereto.
In one embodiment, before step S400, further includes:
in step S300, an isolation protection layer is formed on the surface of the trench 100a.
The formation of the isolation protection layer can effectively insulate the conductive connection structure 200 in the trench 100a from the semiconductor substrate 100, thereby effectively preventing leakage between the conductive connection structure 200 and the semiconductor substrate 100.
Meanwhile, when a plurality of trenches 100a are provided, the conductive connection structures 200 in the respective trenches 100a can be effectively insulated and isolated, thereby preventing leakage or coupling between the conductive connection structures 200 in the respective trenches 100a, and further preventing mutual interference of signals between the conductive connection structures 200 in the respective trenches 100a.
In one embodiment, step S300 includes:
step S310, forming an isolation protection material layer on the surface of the trench 100a and the upper surface of the semiconductor substrate 100, wherein the isolation protection material layer comprises a first oxide layer 510, a nitride layer 520 and a second oxide layer 530 sequentially formed, and the second oxide layer 530 fills the trench 100a;
step S320, please refer to fig. 3, performing chemical mechanical polishing on the isolation protection material layer, wherein the chemical mechanical polishing stops on the first oxide layer 510;
in step S330, referring to fig. 4 and fig. 5, the second oxide layer 530 after the cmp is patterned.
In step S310, the first oxide layer 510 and the second oxide layer 530 may be, for example, silicon dioxide. Nitride layer 520 may be, for example, silicon nitride.
The first oxide layer 510 may be formed by thermally oxidizing the surface of the trench 100a and the upper surface of the semiconductor substrate 100 by thermal oxidation. Then, a nitride layer 520 is deposited on the surface of the first oxide layer 510 by atomic layer deposition. Then, a second oxide layer 530 is deposited on the surface of the nitride layer 520 by high density plasma enhanced chemical vapor deposition (HDP-CVD).
After depositing the second oxide layer 530, the trench 100a may be filled.
In step S320, referring to fig. 3, the chemical mechanical polishing is stopped on the first oxide layer 510, so that the remaining first oxide layer 510 exists on the surface of the trench 100a and the upper surface of the semiconductor substrate 100 at the same time, so that the upper surface of the semiconductor substrate 100 can be protected during the subsequent processing. Of course, in some embodiments, the first oxide layer 510 on the upper surface of the semiconductor substrate 100 outside the trench 100a may also be removed.
In step S330, referring to fig. 4, a second patterned photoresist layer 10 may be first formed on the surface of the structure formed after the cmp. The second patterned photoresist layer 10 covers edge portions of the second oxide layer 530 and exposes middle portions of the second oxide layer 530. Then, referring to fig. 5, based on the second patterned photoresist layer 10, a portion of the second oxide layer 530 is etched away, so that the trench 100a may have a space for forming the conductive connection structure 200. The remaining second oxide layer 530 covers the surface of the nitride layer 520, and may have a thickness of 10nm to 30nm. Thereafter, the second patterned photoresist layer 10 is removed.
Thereafter, referring to fig. 6, in step S400, the conductive connection structure 200 may be formed on the surface of the second oxide layer 530 by Atomic Layer Deposition (ALD) or the like. Specifically, a conductive connection material layer may be first deposited and then subjected to a chemical mechanical polishing process, which stops on the first oxide layer 510, and the remaining conductive connection material layer constitutes the conductive connection structure 200. At this time, the upper surface of the conductive connection structure 200 may be flush with the upper surface of the first oxide layer 510.
The isolation formed in this embodiment includes a first oxide layer 510, a nitride layer 520, and a second oxide layer 530. The first oxide layer 510, the nitride layer 520 and the second oxide layer 530 form an ONO multi-layer composite structure having characteristics of high relative dielectric constant, high breakdown voltage, low leakage, etc., thereby effectively improving the reliability of the device.
Of course, in other embodiments, the isolation protection layer may also be a single-layer insulating structure, which is not limited herein.
In one embodiment, after step S400, the trench 100a may not be filled.
At this time, after step S400, further includes:
in step S500, referring to fig. 6, a filling layer 600 is formed in the trench 100a.
The trench 100a may be well filled by high density plasma enhanced chemical vapor deposition (HDP-CVD) or the like, thereby forming the filling layer 600.
The fill layer 600 may include, but is not limited to, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and the like.
Specifically, the filling material layer can be deposited on the surface of the structure formed before by means of HDP-CVD. Then, a chemical mechanical polishing process is performed, and the chemical mechanical polishing is stopped on the conductive connection structure 200 formed in the trench 100a, and the remaining filling material layer constitutes the filling layer 600. At this time, the upper surfaces of the filling layer 600, the conductive connection structure 200 and the first oxide layer 510 are flush.
At this time, the conductive connection structure 200 in the trench 100a is in a "U" shape, so that the material cost of the conductive connection structure 200 can be effectively saved. The thickness of the conductive connection structure 200 can be set according to the actual resistance requirement, and the larger the thickness is, the smaller the resistance value is.
Of course, in some embodiments, in step S400, the trench 100a may also be filled by the conductive connection structure 200, and the conductive connection structure 200 may have a smaller resistance.
In one embodiment, step S600 includes:
in step S610, referring to fig. 7, a peripheral circuit structure 300 is formed over the semiconductor substrate 100a in the peripheral region;
in step S620, referring to fig. 7, a first dielectric layer 710 is formed in the peripheral region and the array region, and the first dielectric layer 710 covers the peripheral circuit structure 300;
in step S630, referring to fig. 8, a first interconnect hole 710a and a second interconnect hole 710b are formed in the first dielectric layer 710, the first interconnect hole 710a is connected to the peripheral circuit structure 300, and the second interconnect hole 710b is connected to the conductive connection structure 200;
in step S640, referring to fig. 9 and fig. 10, a connection line structure 800 is formed on the first dielectric layer 710, and the connection line structure 800 electrically connects the peripheral circuit structure 300 and the conductive connection structure 200 through the first interconnection hole 710a and the second interconnection hole 710b.
In step S610, referring to fig. 7, as described above, the peripheral circuit structure 300 may include a logic circuit (not shown) formed by a peripheral dielectric layer and a metal layer. The peripheral dielectric layer and the logic circuit may be formed by a plurality of process steps, and the process steps forming the two may have intersections.
In step S620, referring to fig. 7, a first dielectric material layer covering the peripheral circuit structure 300 may be formed first. And then carrying out planarization treatment on the first dielectric material layer. For example, the first dielectric layer 710 may be formed by performing a planarization process on the first dielectric material layer through chemical mechanical polishing.
The material of the first dielectric layer 710 may include, but is not limited to, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, etc.
In step S630, referring to fig. 8, a first interconnection hole 710a and a second interconnection hole 710b may be formed in the first dielectric layer 710 through photolithography and etching processes. The first interconnect hole 710a is in particular connected to the circuitry of the peripheral circuit structure 300. And the second interconnection hole 710b may communicate to a portion of the conductive connection structure 200 near the peripheral region.
In step S640, referring to fig. 9, a conductive material (e.g., metal) may be first deposited to form conductive plugs 810 in the first and second interconnect holes 710a and 710b. Then, referring to fig. 10, a connection conductive layer 820 is formed on the first dielectric layer 710 to cover the first interconnect hole 710a and the second interconnect hole 710b, thereby forming a connection line structure 800. At this time, the connection line structure 800 includes the connection conductive layer 820 and the conductive plugs 810 within the first and second interconnection holes 710a and 710b. The materials of conductive plugs 810, connecting conductive layers 820, and conductive connection structure 200 may be the same or different.
Alternatively, the conductive material filling the first and second interconnect holes 710a and 710b and extending beyond the first and second interconnect holes 710a and 710b may be initially deposited, and then patterned to form the connection line structure 800 of the integrated structure.
In the present embodiment, by providing the connection line structure 800, the peripheral circuit structure 300 can be electrically connected to the conductive connection structure 200.
In one embodiment, after step S640, the method further includes:
in step S710, referring to fig. 10, a second dielectric layer 720 is formed on the upper surface of the first dielectric layer 710 and the upper surface of the connection line structure 800;
in step S720, referring to fig. 11 and 12, the first dielectric layer 710 and the second dielectric layer 720 are patterned to expose the semiconductor substrate 100 in the array region;
in step S710, referring to fig. 10, the material of the second dielectric layer 720 may include, but is not limited to, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, etc. The second dielectric layer 720 may be the same or different from the first dielectric layer 710, and is not limited in this regard.
The formation of the second dielectric layer 720 may effectively protect the conductive connection structure 200 and the peripheral circuit structure 300 during the subsequent formation of the memory array structure 400.
In step S720, referring to fig. 11, a third patterned photoresist layer 20 may be first formed on the second dielectric layer 720. Then, referring to fig. 12, based on the third patterned photoresist layer 20, the portions of the first dielectric layer 710 and the second dielectric layer 720 located in the array region are removed, thereby exposing the semiconductor substrate 100 in the array region. It will be appreciated that at this time, if the surface of the semiconductor substrate 100 has the first oxide layer 510, a portion thereof in the array region is also removed, and the final first oxide layer 510 extends from within the trench to the upper surface of the semiconductor substrate 100 in the peripheral region. The third patterned photoresist layer 20 is then removed.
The semiconductor substrate 100 exposing the array region may perform formation of the memory array structure 400. Specifically, step S800 may include:
in step S810, referring to fig. 13, a memory array structure is formed over the exposed semiconductor substrate 100 in the array region;
in step S820, referring to fig. 14, a third dielectric layer 730 is formed on the memory array structure 400 and the second dielectric layer 720;
in step S830, referring to fig. 15, a bit line hole 900a is formed through the third dielectric layer 730, the second dielectric layer 720 and the first dielectric layer 710, and the bit line hole 900a is communicated with the conductive connection structure 200 and the transistor source region or drain region of each layer of memory cell;
in step S840, referring to fig. 16, a bit line 900 is formed in the bit line hole 900a.
In step S810, referring to fig. 13, the memory array structure 400 may be formed through a plurality of process steps. The memory array structure 400 may include a plurality of memory cells arranged in a stack. The memory cell includes a transistor 410 and a memory element 420. The transistor may include a lateral all-around gate transistor, and the transistor may include a semiconductor layer 411, a gate 412, and a gate dielectric layer 413, both ends of the semiconductor layer 410 forming a source region and a drain region, respectively. One of the source region and the drain region is positioned on one side of the array region close to the peripheral region, and the other is positioned on one side of the array region far away from the peripheral region. The gate 412 of the transistor surrounds a portion between the source region and the drain region of the semiconductor layer 411. A gate dielectric layer is located between the gate 412 and the semiconductor layer 411.
In step S820, referring to fig. 14, the material of the third dielectric layer 730 may include, but is not limited to, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, etc. The materials of the third dielectric layer 730, the second dielectric layer 720 and the first dielectric layer 710 may be the same or different, which is not limited herein.
The third dielectric layer 730 may effectively protect the memory array structure 400.
In step S830, referring to fig. 15, a fourth patterned photoresist layer 30 may be first formed on the third dielectric layer 730. Then, based on the fourth patterned photoresist layer 30, the third dielectric layer 730, the second dielectric layer 720, and the first dielectric layer 710 are etched, thereby forming bit line holes 900a. The fourth patterned photoresist layer 30 is then removed.
In step S840, referring to fig. 16, a bit line material layer may be first deposited and then subjected to chemical mechanical polishing. The cmp stops on the third dielectric layer 730, thereby removing the bit line material layer over the third dielectric layer 730, and the bit line material layer remaining in the bit line hole 900a constitutes the bit line 900.
At this time, since the bit line hole 900a is connected to the conductive connection structure 200 and the transistor source or drain region of each layer of memory cells, the bit line 900 in the bit line hole 900a may be in contact with the conductive connection structure 200 and the transistor source or drain region of each layer of memory cells, thereby electrically connecting the conductive connection structure 200 with the memory array structure.
In this embodiment, the first dielectric layer 710 and the second dielectric layer 720 of the array region are removed, so that the height of the memory array structure 400 can be effectively reduced, and the height of the bit line connecting the memory array structure 400 and the conductive connection structure 200 is reduced. At this time, the bit line impedance can be further reduced.
Of course, in other embodiments, the first dielectric layer 710 and/or the second dielectric layer 720 of the array region may not be removed, which is not limited herein.
It should be understood that in the foregoing embodiments and the drawings, the conductive connection structure 200 is formed in the trench 100a as an example. However, in other embodiments, the conductive connection structure 200 may be formed in the semiconductor substrate 100a by other methods, which is not limited herein. For example, the semiconductor substrate 100a may be heavily doped by means of ion implantation, thereby forming the conductive connection structure 200 formed within the semiconductor substrate 100a. The conductive connection structure 200 may be formed on the upper surface layer of the semiconductor substrate 100a, or may be entirely formed inside the semiconductor substrate 100a so as to be surrounded by it. At this time, the periphery of the conductive connection structure 200 may also be treated by different processes (for example, by ion implantation of oxygen ions and related heat treatment) to form an isolation protection layer.
It should be understood that, although the steps in the flowchart of fig. 1 are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in fig. 1 may include a plurality of steps or stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily sequential, but may be performed in rotation or alternatively with at least a portion of the steps or stages in other steps or other steps.
In one embodiment, referring to fig. 16, a semiconductor structure is further provided, which has an array region and a peripheral region. The semiconductor structure includes a semiconductor substrate 100, a memory array structure 400, a peripheral circuit structure 300, and a conductive connection structure 200.
The memory array structure 400 is located over the semiconductor substrate 100 of the array region;
the peripheral circuit structure 300 is located over the semiconductor substrate 100 in the peripheral region;
the conductive connection structure 200 is located in the semiconductor substrate 100 and electrically connects the memory array structure 400 and the peripheral circuit structure 300.
In one embodiment, a memory array structure includes memory cells arranged in a multi-layer stack.
In one embodiment, the semiconductor substrate is provided with a trench 100a, and the conductive connection structure 200 is located within the trench 100a.
In one embodiment, the trench 100a is located between the array region and the peripheral region.
In one embodiment, an isolation protection layer 500 is further disposed between the conductive connection structure 200 and the trench 100a.
In one embodiment, the isolation protection layer 500 includes a first oxide layer 510, a second oxide layer 530, and a nitride layer 520, where the first oxide layer 510 is located on the trench surface, and the nitride layer 520 is located between the first oxide layer 510 and the second oxide layer 530.
In one embodiment, the first oxide layer 510 extends from within the trench to the upper surface of the semiconductor substrate 100 in the peripheral region.
In one embodiment, a filling layer 600 is further disposed in the trench 100a, and the filling layer 600 is located on the surface of the conductive connection structure 200 and fills the trench 100a.
In one embodiment, the semiconductor structure further includes a connection line structure 800 and a bit line 900. The connection line structure 800 electrically connects the peripheral circuit structure 300 and the conductive connection structure 200. Bit line 900 electrically connects conductive connection structure 200 with transistor source or drain regions of memory cells of each layer.
For specific limitations of the semiconductor structure, reference may be made to the above limitation of the method for preparing the semiconductor structure, and no further description is given here.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present disclosure, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that variations and modifications can be made by those skilled in the art without departing from the spirit of the disclosure, which are within the scope of the disclosure. Accordingly, the scope of protection of the present disclosure should be determined by the following claims.

Claims (18)

1. A semiconductor structure having an array region and a peripheral region, comprising:
a semiconductor substrate;
a memory array structure located over the semiconductor substrate of the array region;
a peripheral circuit structure located over the semiconductor substrate of the peripheral region;
and the conductive connection structure is positioned in the semiconductor substrate and electrically connects the storage array structure and the peripheral circuit structure.
2. The semiconductor structure of claim 1, wherein the memory array structure comprises memory cells arranged in a multi-layer stack.
3. A semiconductor structure according to claim 1 or 2, characterized in that the semiconductor substrate is provided with a trench, the conductive connection structure being located in the trench.
4. The semiconductor structure of claim 3, wherein the trench is located between the array region and the peripheral region.
5. The semiconductor structure of claim 3, wherein an isolation protection layer is further disposed between the conductive connection structure and the trench.
6. The semiconductor structure of claim 5, wherein the isolation protection layer comprises a first oxide layer, a second oxide layer, and a nitride layer, the first oxide layer being located on the trench surface, the nitride layer being located between the first oxide layer and the second oxide layer.
7. The semiconductor structure of claim 6, wherein the first oxide layer extends from within the trench to an upper surface of the semiconductor substrate of the peripheral region.
8. The semiconductor structure of claim 3, wherein a filling layer is further disposed in the trench, the filling layer being located on a surface of the conductive connection structure and filling the trench.
9. The semiconductor structure of claim 2, wherein the semiconductor structure further comprises:
a connecting line structure electrically connecting the peripheral circuit structure and the conductive connection structure;
and a bit line electrically connecting the conductive connection structure with the transistor source region or drain region of the memory cell of each layer.
10. A method of fabricating a semiconductor structure, the semiconductor structure comprising an array region and a peripheral region, the method comprising:
providing a semiconductor substrate;
forming a conductive connection structure in the semiconductor substrate;
forming a peripheral circuit structure over the semiconductor substrate of the peripheral region and electrically connecting the peripheral circuit structure with the conductive connection structure;
a memory array structure is formed over the semiconductor substrate of the array region and electrically connected to the conductive connection structure.
11. The method of claim 10, wherein the memory array structure comprises a plurality of stacked memory cells.
12. The method of manufacturing a semiconductor structure according to claim 10 or 11, wherein forming a conductive connection structure in the semiconductor substrate comprises:
forming a groove in the semiconductor substrate;
and forming the conductive connection structure in the groove.
13. The method of claim 12, wherein the trench is located between the array region and the peripheral region.
14. The method of fabricating a semiconductor structure according to claim 12, wherein prior to forming the conductive connection structure within the trench, further comprising:
and forming an isolation protection layer on the surface of the groove.
15. The method of claim 14, wherein forming an isolation protection layer on the trench surface comprises:
forming an isolation protection material layer on the surface of the groove and the upper surface of the semiconductor substrate, wherein the isolation protection material layer comprises a first oxide layer, a nitride layer and a second oxide layer which are sequentially formed, and the second oxide layer fills the groove;
performing chemical mechanical polishing on the isolation protection material layer, wherein the chemical mechanical polishing stops on the first oxide layer;
and carrying out patterning treatment on the second oxide layer after chemical mechanical polishing.
16. The method of fabricating a semiconductor structure according to claim 15, wherein after forming the conductive connection structure in the trench, further comprising:
and forming a filling layer in the groove.
17. The method of claim 11, wherein forming a peripheral circuit structure over the semiconductor substrate in the peripheral region, and electrically connecting the peripheral circuit structure to the conductive connection structure comprises:
forming a peripheral circuit structure over the semiconductor substrate of the peripheral region;
forming a first dielectric layer in the peripheral region and the array region, wherein the first dielectric layer covers the peripheral circuit structure;
forming a first interconnection hole and a second interconnection hole in the first dielectric layer, wherein the first interconnection hole is communicated with the peripheral circuit structure, and the second interconnection hole is communicated with the conductive connection structure;
and forming a connecting wire structure on the first dielectric layer, wherein the connecting wire structure is electrically connected with the peripheral circuit structure and the conductive connecting structure through the first interconnection hole and the second interconnection hole.
18. The method of fabricating a semiconductor structure as recited in claim 17, wherein,
after the connecting line structure is formed on the first dielectric layer, the method further comprises:
forming a second dielectric layer on the upper surface of the first dielectric layer and the upper surface of the connecting wire structure;
patterning the first dielectric layer and the second dielectric layer to expose the semiconductor substrate of the array region;
forming a memory array structure over the semiconductor substrate of the array region and electrically connecting the memory array structure with the conductive connection structure, comprising:
forming a memory array structure over the exposed semiconductor substrate of the array region;
forming a third dielectric layer on the storage array structure and the second dielectric layer;
forming bit line holes penetrating through the third dielectric layer, the second dielectric layer and the first dielectric layer, wherein the bit line holes are communicated with the conductive connection structure and transistor source regions or drain regions of the memory cells of each layer;
and forming a bit line in the bit line hole.
CN202210680638.9A 2022-06-16 2022-06-16 Semiconductor structure and preparation method thereof Pending CN117334668A (en)

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