CN117322894B - Electroencephalogram acquisition analog front-end circuit adopting dual-channel multiplexing technology - Google Patents
Electroencephalogram acquisition analog front-end circuit adopting dual-channel multiplexing technology Download PDFInfo
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Abstract
The invention discloses an electroencephalogram acquisition analog front-end circuit adopting a dual-channel multiplexing technology, which relates to a logic circuit technology and comprises a buffer, a channel multiplexing circuit, a transconductance amplifier circuit, a transimpedance amplifier circuit, a multiplexing demodulation circuit, a program-controlled gain amplifier and an active low-pass filter which are sequentially connected. The invention can inhibit motion artifact and noise generated by electrode tissue impedance, and can perform program-controlled gain adjustment at the same time, thereby avoiding distortion or attenuation of an input signal after amplification; and the power consumption of the electrode chip is effectively reduced on the premise of not reducing the number of front-end channels.
Description
Technical Field
The invention relates to the technical field of logic circuits, in particular to an electroencephalogram acquisition analog front-end circuit adopting a dual-channel multiplexing technology.
Background
Active electrode chips of multichannel Analog Front End (AFE) have been widely accepted for their role in brain research and in the field of neurological diseases, particularly in the diagnosis of epilepsy, brain tumors, etc. The analog front end is a main structure of the signal acquisition electrode chip, and the function of the analog front end is to amplify, filter and digitize the acquired biological signals and then transmit the signals to a Digital Signal Processor (DSP) for further signal processing.
The existing analog front-end circuit can reduce the power consumption by reducing the number of channels, but can reduce the rate of signal acquisition, and is not preferable when applied to an electrode chip for acquiring the electroencephalogram signals; meanwhile, the amplifier in the existing analog front-end circuit can inhibit signal attenuation, but noise is introduced into the amplifier, so that the input impedance of the amplifier needs to be improved, and certain power consumption is correspondingly increased.
Disclosure of Invention
The invention provides an electroencephalogram acquisition analog front-end circuit adopting a dual-channel multiplexing technology, which solves the problems that noise and larger power consumption are caused by signal attenuation inhibition of the existing analog front-end circuit.
The invention discloses an electroencephalogram acquisition analog front-end circuit adopting a dual-channel multiplexing technology, which comprises the following components in sequence:
a buffer: for enhancing the intensity of the brain electrical signals and maintaining the integrity of the signals;
channel multiplexing circuit: multiplexing of the two channels is achieved, so that the two channels commonly use a subsequent transconductance amplifier and a trans-impedance amplifier, and power consumption and layout area of the front end are reduced;
transconductance amplifier circuit: for reducing noise and improving the anti-interference capability of the input signal, converting the voltage signal into a more stable current signal;
transimpedance amplifier circuit: the circuit is used for converting the current signal into a voltage signal, and simultaneously maintaining the bandwidth performance of the circuit and removing motion artifacts;
a multiplexing demodulation circuit: demodulation of the input signal is realized, and the multiplexing signal is restored to the input signal of the first channel and the input signal of the second channel;
program controlled gain amplifier: for achieving a controllable gain adjustment;
an active low pass filter: the method is used for filtering out higher harmonics and noise in the signals to obtain complete and clear bioelectric signals.
Preferably, the channel multiplexing circuit comprises a channel I and a channel II, each channel comprises two differential input circuits, each differential input circuit is composed of two switches in parallel, the switches are complementary switches of the CMOS tube, and each switch is composed of a PMOS tube and a drain electrode and a source electrode of the NOMS tube which are connected.
Preferably, the transconductance amplifier circuit includes an RC low-pass filter, two NMOS tubes, eight PMOS tubes and two capacitors, the RC low-pass filter is connected to the gates of the PMOS tube P1 and the PMOS tube P2, the sources of the NMOS tube N1 and the NMOS tube N2 are grounded, the drain of the NMOS tube N1 is connected to the drain of the PMOS tube P1 and the gate of the PMOS tube P7, the drain of the NMOS tube N2 is connected to the drain of the PMOS tube P2 and the gate of the PMOS tube P8, the source of the PMOS tube P1 is connected to the PMOS tube P3, the PMOS tube P5 and the PMOS tube P7 in sequence, the source of the PMOS tube P2 is connected to the PMOS tube P4, the PMOS tube P6 and the PMOS tube P8 in sequence, the gates of the PMOS tube P3 are connected between the drain of the PMOS tube P5 and the source of the PMOS tube P7, the gate of the PMOS tube P4 is connected between the drain of the PMOS tube P6 and the drain of the PMOS tube P8, the drain of the PMOS tube P8 and the drain of the PMOS tube P8 are connected to the drain of the PMOS tube P1 and the capacitor C2 is connected to one end of the capacitor of the PMOS tube P2 and the capacitor is connected to the drain of the other capacitor P2.
Preferably, the RC low-pass filter is formed by connecting a capacitor C and two equivalent resistors R in parallel, and the equivalent resistors R are formed by connecting two PMOS tube gates and drains.
Preferably, the transimpedance amplifier circuit includes two amplifiers, four NMOS tubes and four PMOS tubes, differential input ends of the two amplifiers are connected with sources of the PMOS tube P11 and the PMOS tube P12 and drains of the PMOS tube P9 and the PMOS tube P10, the other ends are connected with reference voltages, output ends of the two amplifiers are respectively connected with gates of the PMOS tube P11 and the PMOS tube P12, sources of the PMOS tube P9 and the PMOS tube P10 are connected, the NMOS tube N3, the NMOS tube N4, the NMOS tube N5 and the NMOS tube N6 form a two-branch common-source common-gate structure, sources of the NMOS tube N3 and the NMOS tube N4 are grounded, drains of the NMOS tube N5 are connected with drains of the PMOS tube P11, and drains of the NMOS tube N6 are connected with drains of the PMOS tube P12.
Preferably, the programmable gain amplifier comprises an amplifier and two feedback loops, each feedback loop comprises a resistor R1 and a resistor R2, the resistor R2 is composed of a programmable resistor array, and the programmable resistor array comprises a switch composed of a PMOS tube and a drain electrode and a source electrode of a NOMS tube.
Preferably, the active low-pass filter includes a fully differential operational amplifier OPA1 and a fully differential operational amplifier OPA2, two input ends of the fully differential operational amplifier OPA1 are connected with a resistor R3, a resistor R4 is connected between the input end of the fully differential operational amplifier OPA1 and the output end of the fully differential operational amplifier OPA2, a resistor R5 is connected between the output end of the fully differential operational amplifier OPA1 and the input end of the fully differential operational amplifier OPA2, a capacitor C3 is connected between the input end and the output end of the fully differential operational amplifier OPA1, and a resistor R6 and a capacitor C4 which are connected in parallel are connected between the input end and the output end of the fully differential operational amplifier OPA 2.
The invention has the beneficial effects that:
(1) Motion artifact and noise generated by electrode tissue impedance are restrained, program-controlled gain adjustment can be performed at the same time, and distortion or attenuation of an input signal after amplification is avoided.
(2) The power consumption of the electrode chip is effectively reduced on the premise of not reducing the number of front-end channels.
Drawings
FIG. 1 shows an electroencephalogram acquisition analog front end structure adopting a dual-channel multiplexing technology according to an embodiment of the invention;
fig. 2 is a schematic diagram of a dual-channel multiplexing circuit according to an embodiment of the invention;
FIG. 3 is a schematic diagram of a transconductance amplifier circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a transimpedance amplifier circuit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a programmable gain amplifier and a switch resistor array according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of an active low pass filter circuit according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of open loop gain and phase margin of a transconductance amplifier according to an embodiment of the present invention;
fig. 8 is a diagram illustrating an open loop gain and a phase margin of a transimpedance amplifier according to an embodiment of the present invention.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail below with reference to the accompanying drawings and examples.
The application discloses brain electricity acquisition analog front-end circuit adopting a double-channel multiplexing technology, as shown in fig. 1, comprising the following components:
a buffer: for enhancing the intensity of the brain electrical signals and maintaining the integrity of the signals;
channel multiplexing circuit: multiplexing of the two channels is achieved, so that the two channels commonly use a subsequent transconductance amplifier and a trans-impedance amplifier, and power consumption and layout area of the front end are reduced;
transconductance amplifier circuit: for reducing noise and improving the anti-interference capability of the input signal, converting the voltage signal into a more stable current signal;
transimpedance amplifier circuit: the circuit is used for converting the current signal into a voltage signal, and simultaneously maintaining the bandwidth performance of the circuit and removing motion artifacts;
a multiplexing demodulation circuit: demodulation of the input signal is realized, and the multiplexing signal is restored to the input signal of the first channel and the input signal of the second channel;
program controlled gain amplifier: for achieving a controllable gain adjustment;
an active low pass filter: the method is used for filtering out higher harmonics and noise in the signals to obtain complete and clear bioelectric signals.
In one embodiment, the input end of the buffer is connected with the differential input signal, and the output end of the buffer is connected with the input end of the channel multiplexing circuit; the brain electrical signals are collected by the active electrode and input into the buffer as input signals; the buffer consists of two stages of CMOS inverters, and each inverter consists of a PMOS tube and an NMOS tube which are connected with each other by a grid and a drain. The buffer is used for enhancing the intensity of the brain electrical signal and maintaining the integrity of the signal, amplifying the brain electrical signal to the signal which is identical to the input signal, enhancing the driving capability of the signal, and simultaneously, the input buffer can filter a part of noise, thereby reducing the overall power consumption.
As shown in fig. 2, in one embodiment, the channel multiplexing circuit includes a first channel and a second channel, each channel includes two differential input circuits, each differential input circuit is formed by connecting two switches in parallel, the differential input signals of the first channel and the second channel are controlled by the switches, and the clock control signals control the opening and closing of the switches. The two channels are controlled to be opened in opposite logic, namely when the clock signal added to the first channel is high level, the first channel is input to the next stage circuit as an input signal for processing, at the moment, the clock signal of the second channel is low level, the second channel is cut off, and the clock signal is a square wave pulse signal, so that the two-channel multiplexing of the front end is realized.
The switch is a CMOS tube complementary switch, the CMOS complementary switch utilizes complementary characteristics, no threshold loss exists when high and low levels are transmitted, the noise margin is larger than that of a single MOS tube switch, the logic swing is large, the anti-interference capability is strong, and the static power consumption is lower. The CMOS complementary switch circuit structure is formed by connecting a PMOS tube with the drain electrode and the source electrode of a NOMS tube. Input signals are input from a common drain end of the MOS tube and output from a common source end of the MOS tube. A set of opposite clock signals are applied to the gates of the PMOS and NMOS respectively to control the switch to be turned on, and when clk is high, clkn is low, the switch is turned off, otherwise the switch is turned on.
As shown in fig. 3, in one embodiment, the transconductance amplifier has a high input impedance, which can effectively reduce noise and improve the anti-interference capability of an input signal, and an RC low-pass filter is integrated at an input end to suppress dc offset and filter out clutter of different frequencies; the transconductance amplifier is a voltage-controlled current source, can convert a voltage signal into a more stable current signal, and works in a saturation region, and has a current formula as follows:
wherein,is channel mobility>Is the gate capacitance per unit area, W is the gate width, L is the gate length, +.>Is the gate-source voltage, ">Is threshold voltage, +.>Is the drain-source current.
The fully differential structure for the transconductance amplifier circuit can effectively inhibit common-mode interference, provides higher input voltage swing and higher input impedance, and can inhibit environmental noise. The transconductance amplifier circuit comprises an RC low-pass filter, two NMOS tubes, eight PMOS tubes and two capacitors. The RC low-pass filter is used for inhibiting direct current offset and filtering high-frequency signals, one end of the RC low-pass filter is connected with the differential input signals, and the other end of the RC low-pass filter is connected with the grid electrodes of the PMOS tube P1 and the PMOS tube P2. Because of the amplification principle of the amplifier, weak offset of an input signal can be converted into larger error of an output end, and circuit failure can be caused; DC offset is eliminated by DC feedback technique. The resistance of the equivalent resistor R is 10kΩ, the resistance of the capacitor C is 10uF, and the principle of the RC low-pass filter for realizing filtering is as follows:
wherein,is the cut-off frequency of the RC low-pass filter, R is the equivalent resistance value of the RC low-pass filter, and C is the equivalent capacitance of the RC low-pass filter.
The RC low-pass filter is composed of a capacitor C and two equivalent resistors R which are connected in parallel, and in order to ensure the ultra-low-pass level, the equivalent resistors of the low-pass filter use active resistors, the active resistors are connected with drain ends and grid ends of two PMOS tubes, and the grid electrodes of the PMOS tubes are connected with the source ends. Because the MOS tube has internal resistance, the MOS tube shows the characteristic of linear resistance after the circuit works stably, and the bias current of the PMOS tube is basically 0, so that the MOS tube shows extremely large output resistance; because of the equivalent large resistance of the RC low-pass filter, the capacitor can realize a low-pass stage which is small enough, and the sub-Hz cutoff frequency is realized by using an external capacitor with 10 mu F, so that the problems of chip layout area and the discomfort caused by overlarge capacitor can be effectively reduced.
The drain electrode of the NMOS tube N1 is connected with the drain electrode of the PMOS tube P1 and the grid electrode of the PMOS tube P7, the drain electrode of the NMOS tube N2 is connected with the drain electrode of the PMOS tube P2 and the grid electrode of the PMOS tube P8, the source electrode of the PMOS tube P1 is sequentially connected with the PMOS tube P3, the PMOS tube P5 and the PMOS tube P7, the source electrode of the PMOS tube P2 is sequentially connected with the PMOS tube P4, the PMOS tube P6 and the PMOS tube P8, the source electrodes of the PMOS tube P3, the PMOS tube P4, the PMOS tube P5 and the PMOS tube P6 are sequentially connected, the grid electrode of the PMOS tube P3 is connected between the drain electrode of the PMOS tube P5 and the source electrode of the PMOS tube P7, the grid electrode of the PMOS tube P4 is connected between the drain electrode of the PMOS tube P6 and the source electrode of the PMOS tube P8, the PMOS tube P3 and the PMOS tube P4 serve as current sources, the bias is provided for a branch where the PMOS tube P3 and the grid electrode of the PMOS tube P4 are connected, the PMOS tube P5 and the PMOS tube P7, the PMOS tube P6 and the PMOS tube P8 are sequentially connected, the output branch where the PMOS tube P8 receives the PMOS tube P6 and the PMOS tube P8, and the output signal is more stable in the output region, and the voltage of the PMOS tube P4 is saturated in the power region, and the output region is stable; the drains of the PMOS tube P7 and the PMOS tube P8 are grounded, one end of the capacitor C1 is connected with the drain of the NMOS tube N1 and the grid of the PMOS tube P7, one end of the capacitor C2 is connected with the drain of the NMOS tube N2 and the grid of the PMOS tube P8, the other ends of the capacitor C1 and the capacitor C2 are grounded, and the capacitor C1 and the capacitor C2 are feed-through capacitors.
A first bias voltage is connected between the gates of the NMOS tube N1 and the NMOS tube N2, and provides bias for the NMOS tube N1 and the NMOS tube N2, so that the tubes work in a saturation region, and the NMOS tube N1 and the NMOS tube N2 serve as current source loads to provide gain for the circuit; the grid electrode of the PMOS tube P5 and the grid electrode of the PMOS tube P6 are connected with a second bias voltage, and bias is provided for the PMOS tube P5 and the PMOS tube P6, so that the PMOS tube P5 and the PMOS tube P6 work in a saturation region.
The amplifier gain can be expressed as:
；
wherein the method comprises the steps ofIs the total gain of the amplifier, +.>Is the gain of the branch where the NMOS tube N1 and the PMOS tube P1, the NMOS tube N2 and the PMOS tube P2 are located, and is ∈>Is the gain of the branch circuit where the PMOS tube P5 and the PMOS tube P7, the PMOS tube P6 and the PMOS tube P8 are positioned, and is->Is the transconductance of MOS tube->Is the equivalent resistance of the MOS tube.
As shown in fig. 4, in one embodiment, the transimpedance amplifier circuit includes two amplifiers, four NMOS transistors and four PMOS transistors, one ends of differential input ends of the two amplifiers are connected to sources of the PMOS transistors P11 and P12 and drains of the PMOS transistors P9 and P10, the other ends are connected to reference voltages, output ends of the two amplifiers are connected to gates of the PMOS transistors P11 and P12, and sources of the PMOS transistors P9 and P10 are connected. The amplifier adopts a single-ended output five-tube amplifier and is used for improving the gain and the anti-interference capability of the transimpedance amplifier.
NMOS tube N3, NMOS tube N4, NMOS tube N5 and NMOS tube N6 form a two-branch common-source common-gate structure to form a constant current source for providing bias for the circuit; the source electrodes of the NMOS tube N3 and the NMOS tube N4 are grounded, the drain electrode of the NMOS tube N5 is connected with the drain electrode of the PMOS tube P11, the drain electrode of the NMOS tube N6 is connected with the drain electrode of the PMOS tube P12, a third bias voltage is connected between the grid electrode of the NMOS tube N5 and the grid electrode of the NMOS tube N6, a bias voltage is provided for the NMOS tube N5 and the NMOS tube N6, a fourth bias voltage is connected between the grid electrode of the NMOS tube N3 and the grid electrode of the NMOS tube N4, and a bias voltage is provided for the NMOS tube N3 and the NMOS tube N4, so that the NMOS tube N3 and the NMOS tube N4 work in a saturation region.
The transimpedance amplifier is suitable for a low-voltage working environment, and meanwhile, the bandwidth performance of the circuit is maintained, and the transimpedance amplifier is used as a conversion circuit between current and voltage; the transimpedance amplifier has low output impedance, can effectively remove the influence of motion artifact on the system, and can receive the current signal transmitted by the front-stage transimpedance amplifier and convert the current signal into a voltage signal to be transmitted to the next-stage circuit. The transconductance amplifier of the embodiment is a PMOS telescopic type common-gate differential amplifier with an NMOS common-source common-gate load, and has a gain enhancing structure for increasing the input impedance of the amplifier and increasing the gain of the amplifier.
The PMOS transistor P9 and the PMOS transistor P10 receive the signal of the previous-stage transconductance amplifier, and convert the current mirrored to the transimpedance amplifier into an output voltage under the load effect after passing through the PMOS transistor P11 and the PMOS transistor P12 due to the effect of the bias voltage, and the output impedance is as follows under the condition of considering the body effect:
wherein,is the body effect transconductance of the MOS tube.
The amplifier gain is:
with classical values, the voltage gain is approximately equal to:
in one embodiment, the multiplexing demodulation circuit is opposite to the channel multiplexing circuit in structure, and the functions realized are opposite, and the multiplexing signal is restored to the signal of the first channel and the signal of the second channel through the multiplexing circuit;
as shown in fig. 5, the programmable gain amplifier includes an amplifier and two feedback loops, each feedback loop includes two resistors R1 and R2, and the resistor R2 can change the resistance value through a control signal, so as to realize the effect of controllable gain, and compared with the resistance value of the adjusting resistor R1, the resistor R2 can be changed without causing uncertain front-stage load, and no additional pre-buffer stage is needed for circuit isolation.
Compared with an open loop circuit, the program-controlled gain amplifier adopts a controllable gain of closed loop resistance negative feedback, and the closed loop structure is provided with a feedback loop besides an amplifying circuit, so that better linearity can be presented. The feedback loop adopts resistance negative feedback, and compared with capacitance negative feedback, the resistance negative feedback can effectively avoid the influence caused by noise. The feedback branch of the program controlled gain amplifier is provided with two feedback resistors, and under the condition of adopting an ideal operational amplifier, the gain of the circuit is as follows:
the program control gain function of the program control gain amplifier is realized by changing the resistance value of a resistor R2, and the program control gain amplifier consists of a ten-bit programmable resistor array, wherein a switch is the same as a path selection switch of a double-channel multiplexing circuit, and consists of an NMOS tube, a PMOS tube drain electrode and a source electrode which are connected. The four switches control four resistors with different resistance values, the switch S1 corresponds to 100kΩ, the switch S2 corresponds to 200kΩ, the switch S3 corresponds to 300kΩ, and the switch S4 corresponds to 400kΩ. When the control voltage is at a high level, the switch is turned on; when the control voltage is low, the switch is opened. The resistance is not zero when the actual switch is on, and is limited when the switch is off, the influence of on-resistance on the programmable gain amplifier is reduced by adjusting the width-to-length ratio of the tube in the transmission gate, so that the on-resistance can be reduced, and the value can be kept in a larger input voltage range. The four switches enter an open state or a closed state according to the change of a control signal, ten different resistance values can be generated by the resistor array, the change of 100k omega to 1M omega can be realized by the resistor of the switch array module, the 100k omega is stepped, the amplifier has the performance of program-controlled gain, and the rough change (step 5 dB) of the gain from 5dB to 45dB can be realized.
As shown in fig. 6, in one embodiment, the active low-pass filter adopts a second order Tomas-I structure, and includes a fully differential operational amplifier OPA1 and a fully differential operational amplifier OPA2, wherein two input ends of the fully differential operational amplifier OPA1 are connected with a resistor R3, a resistor R4 is connected between the input end of the fully differential operational amplifier OPA1 and the output end of the fully differential operational amplifier OPA2, a resistor R5 is connected between the output end of the fully differential operational amplifier OPA1 and the input end of the fully differential operational amplifier OPA2, a capacitor C3 is connected between the input end and the output end of the fully differential operational amplifier OPA1, and a resistor R6 and a capacitor C4 which are connected in parallel are connected between the input end and the output end of the fully differential operational amplifier OPA 2.
The transfer function of the active low-pass filter is:
cut-off frequency of active low-pass filterThe method comprises the following steps:
the active low-pass filter of the embodiment is of a second-order Tomas-I type structure, and can be used for filtering out high-order harmonic waves and noise in signals processed by a front-stage transconductance amplifier, a transimpedance amplifier and a program-controlled gain amplifier to obtain complete and clear bioelectric signals.
In a specific embodiment, the design simulation test verifies that as shown in fig. 7, the design adopts a central core international 180nm process, the working temperature is set at 27 ℃, and the process angle is selected from TT process angles; the power supply voltage is 1.8V, the input common mode level is 0.9V, and the bias current is 1uA; the simulation result of the transconductance amplifier has open loop gain of more than 80dB and phase margin of about 61 deg. As shown in fig. 8, the open loop gain of the transimpedance amplifier simulation result is about 35dB, and the corresponding phase is about 90deg when the gain is reduced to 0 dB; the transconductance amplifier has high gain, and the phase margin is above 60deg, namely the transconductance amplifier has enough stability; because the transimpedance amplifier has different realization functions, the requirement on gain is not high, the phase margin is more than 60deg, the transimpedance amplifier still has enough stability, and self-oscillation can not be generated by the transimpedance amplifier and the transimpedance amplifier, so that the design requirement is met.
The foregoing shows and describes the basic principles and features of the present invention, as well as the advantages of the present invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that the above embodiments and descriptions are merely illustrative of the principles of the present invention, and various changes and modifications may be made without departing from the spirit and scope of the invention, which is defined in the appended claims. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (4)
1. An electroencephalogram acquisition analog front-end circuit adopting a dual-channel multiplexing technology is characterized by comprising the following components in sequence:
a buffer: for enhancing the intensity of the brain electrical signals and maintaining the integrity of the signals;
channel multiplexing circuit: multiplexing of the two channels is achieved, so that the two channels commonly use a subsequent transconductance amplifier and a trans-impedance amplifier, and power consumption and layout area of the front end are reduced;
transconductance amplifier circuit: for reducing noise and improving the anti-interference capability of the input signal, converting the voltage signal into a more stable current signal;
transimpedance amplifier circuit: the circuit is used for converting the current signal into a voltage signal, and simultaneously maintaining the bandwidth performance of the circuit and removing motion artifacts;
a multiplexing demodulation circuit: demodulation of the input signal is realized, and the multiplexing signal is restored to the input signal of the first channel and the input signal of the second channel;
program controlled gain amplifier: for achieving a controllable gain adjustment;
an active low pass filter: the method is used for filtering out higher harmonics and noise in the signals to obtain complete and clear bioelectric signals;
the channel multiplexing circuit comprises a channel I and a channel II, each channel comprises two differential input circuits, each differential input circuit is formed by connecting two switches in parallel, the switches are complementary switches of a CMOS (complementary metal oxide semiconductor) tube and are formed by connecting a PMOS tube with the drain electrode and the source electrode of a NOMS tube;
the transconductance amplifier circuit comprises an RC low-pass filter, two NMOS pipes, eight PMOS pipes and two capacitors, wherein the RC low-pass filter is connected with the grid electrodes of the PMOS pipes P1 and P2, the grid electrodes of the NMOS pipes N1 and N2 are grounded, the drain electrode of the NMOS pipe N1 is connected with the drain electrode of the PMOS pipe P1 and the grid electrode of the PMOS pipe P7, the drain electrode of the NMOS pipe N2 is connected with the drain electrode of the PMOS pipe P2 and the grid electrode of the PMOS pipe P8, the source electrode of the PMOS pipe P1 is sequentially connected with the PMOS pipe P3, the PMOS pipe P5 and the P7, the source electrode of the PMOS pipe P2 is sequentially connected with the PMOS pipe P4, the PMOS pipe P6 and the P8, the grid electrodes of the PMOS pipe P3 are connected between the drain electrode of the PMOS pipe P5 and the source electrode of the PMOS pipe P7, the grid electrode of the PMOS pipe P4 is connected between the drain electrode of the PMOS pipe P6 and the NMOS pipe P8, the drain electrode of the PMOS pipe P7 is connected with the drain electrode of the PMOS pipe P1 and the grid electrode of the PMOS pipe P2, and the capacitor C1 is connected with one end of the capacitor C2 and one end of the capacitor C2 is connected with the drain electrode of the PMOS pipe P2;
the transimpedance amplifier circuit comprises two amplifiers, four NMOS tubes and four PMOS tubes, wherein one end of differential input ends of the two amplifiers is connected with sources of the PMOS tubes P11 and P12 and drains of the PMOS tubes P9 and P10, the other end of the differential input ends is connected with a reference voltage, output ends of the two amplifiers are respectively connected with gates of the PMOS tubes P11 and P12, sources of the PMOS tubes P9 and P10 are connected, the NMOS tubes N3, N4, N5 and N6 form a two-branch common-source common-gate structure, sources of the NMOS tubes N3 and N4 are grounded, drains of the NMOS tubes N5 are connected with drains of the PMOS tubes P11, and drains of the NMOS tubes N6 are connected with drains of the PMOS tubes P12.
2. The brain electricity acquisition analog front-end circuit adopting the dual-channel multiplexing technology according to claim 1, wherein the RC low-pass filter is composed of a capacitor C and two equivalent resistors R in parallel, and the equivalent resistors R are composed of two PMOS tube gates and drains which are connected.
3. The brain wave acquisition analog front-end circuit adopting the dual-channel multiplexing technology according to claim 2, wherein the program-controlled gain amplifier comprises an amplifier and two feedback loops, each feedback loop comprises a resistor R1 and a resistor R2, the resistor R2 is composed of a programmable resistor array, and the programmable resistor array comprises a switch composed of a PMOS tube and a drain electrode and a source electrode of a NOMS tube.
4. The brain electricity acquisition analog front-end circuit adopting the dual-channel multiplexing technology according to claim 3, wherein the active low-pass filter comprises a fully differential operational amplifier OPA1 and a fully differential operational amplifier OPA2, two input ends of the fully differential operational amplifier OPA1 are connected with a resistor R3, a resistor R4 is connected between the input end of the fully differential operational amplifier OPA1 and the output end of the fully differential operational amplifier OPA2, a resistor R5 is connected between the output end of the fully differential operational amplifier OPA1 and the input end of the fully differential operational amplifier OPA2, a capacitor C3 is connected between the input end and the output end of the fully differential operational amplifier OPA1, and a resistor R6 and a capacitor C4 which are connected in parallel are connected between the input end and the output end of the fully differential operational amplifier OPA 2.
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Effective date of registration: 20240911 Address after: High tech Zone Chengdu city Sichuan province 610000 Gaopeng Road No. 8 Patentee after: CHENGDU SHENGLI DEKE TECHNOLOGY CO.,LTD. Country or region after: China Address before: 610225 24 section 1 Xuefu Road, Southwest Airport Economic Development Zone, Chengdu, Sichuan Patentee before: CHENGDU University OF INFORMATION TECHNOLOGY Country or region before: China |