CN117320540A - Semiconductor structure and manufacturing method thereof - Google Patents

Semiconductor structure and manufacturing method thereof Download PDF

Info

Publication number
CN117320540A
CN117320540A CN202311143147.1A CN202311143147A CN117320540A CN 117320540 A CN117320540 A CN 117320540A CN 202311143147 A CN202311143147 A CN 202311143147A CN 117320540 A CN117320540 A CN 117320540A
Authority
CN
China
Prior art keywords
layer
conductor plate
dielectric
dielectric layer
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202311143147.1A
Other languages
Chinese (zh)
Inventor
余立中
蔡欣宏
侯承浩
沈香谷
黄镇球
陈殿豪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US18/188,196 external-priority patent/US20240088204A1/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN117320540A publication Critical patent/CN117320540A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes

Abstract

A semiconductor structure and a method of manufacturing the same are provided. An exemplary method includes depositing a first conductive material layer on a substrate, patterning the first conductive material to form a first conductor plate over the substrate, forming a first high-K dielectric layer on the first conductor plate, forming a second high-K dielectric layer on the first high-K dielectric layer, forming a third high-K dielectric layer on the second high-K dielectric layer, and forming a second conductor plate over the third high-K dielectric layer and vertically overlapping the first conductor plate, wherein a composition of the first high-K dielectric layer is the same as a composition of the third high-K dielectric layer and different from a composition of the second high-K dielectric layer.

Description

Semiconductor structure and manufacturing method thereof
Technical Field
Embodiments of the present application relate to semiconductor structures and methods of fabricating the same.
Background
The semiconductor Integrated Circuit (IC) industry has experienced a rapid growth. Technological advances in integrated circuit materials and design have resulted in a generation of yet another generation of integrated circuits, each of which is smaller and more complex than the previous generation. However, these advances increase the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are required to achieve these advances. During the development of ICs, functional density (i.e., the number of interconnected devices per chip area) generally increases, while geometry (i.e., the smallest component that can be created using a manufacturing process) decreases.
As IC device geometries decrease, there is a need to move large surface area passive devices to back end of line (BEOL) structures. Metal-insulator-metal (MIM) capacitors are one example of such passive devices. A typical MIM capacitor includes a plurality of conductor plates insulated from each other by a plurality of insulator layers. While existing MIM capacitors and their fabrication processes are generally adequate for their intended purposes, they are not entirely satisfactory in all respects.
Disclosure of Invention
According to one aspect of embodiments of the present application, there is provided a method of manufacturing a semiconductor structure, comprising: depositing a first layer of conductive material over a substrate; patterning the first conductive material layer to form a first conductor plate over the substrate; forming a first high-K dielectric layer over the first conductor plate; forming a second high-K dielectric layer over the first high-K dielectric layer; forming a third high-K dielectric layer over the second high-K dielectric layer; and forming a second conductor plate over the third high-K dielectric layer and vertically overlapping the first conductor plate, wherein the composition of the first high-K dielectric layer is the same as the composition of the third high-K dielectric layer and is different from the composition of the second high-K dielectric layer.
According to another aspect of embodiments of the present application, there is provided a method of manufacturing a semiconductor structure, comprising: forming a first conductor plate on the first insulating layer above the substrate; forming a second insulating layer extending along the top surface and the sidewall surface of the first conductor plate; conformally forming a multi-layer dielectric structure over the first conductor plate, wherein the multi-layer dielectric structure is in direct contact with both the first insulating layer and the second insulating layer, and wherein the multi-layer dielectric structure is formed of a high-K dielectric layer; and forming a second conductor plate over the multi-layer dielectric structure and vertically overlapping the first conductor plate.
According to yet another aspect of embodiments of the present application, a semiconductor structure is provided that includes a metal-insulator-metal (MIM) capacitor on a first insulating layer over a substrate. The MIM capacitor includes: the semiconductor device comprises a first conductor plate, a second insulation layer, a conformal dielectric structure and a second conductor plate, wherein the first conductor plate is positioned on the first insulation layer, the second insulation layer extends along and on the side wall and the top surface of the first conductor plate, the conformal dielectric structure is positioned above the substrate and the first conductor plate, the conformal dielectric structure is formed by a plurality of high-K dielectric layers, and the second conductor plate is positioned above the conformal dielectric structure and vertically overlaps with the first conductor plate, and the conformal dielectric structure is in direct contact with both the second insulation layer and the first insulation layer.
Drawings
The various aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawings. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1 is a flow chart of a method of fabricating a semiconductor structure in accordance with aspects of the present disclosure.
Fig. 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, and 16 are partial cross-sectional views of a workpiece during various stages of manufacture of the method of fig. 1 in accordance with various aspects of the disclosure.
Fig. 17 and 18 are partial cross-sectional views of an alternative workpiece during various stages of manufacture of the method of fig. 1 in accordance with various aspects of the disclosure.
Fig. 19 is a flow chart of a method for fabricating another semiconductor structure in accordance with aspects of the present disclosure.
Fig. 20, 21 and 22 are partial cross-sectional views of a workpiece during various stages of manufacture of the method of fig. 19 in accordance with various aspects of the disclosure.
Fig. 23 and 24 are partial cross-sectional views of an alternative workpiece during various stages of manufacture of the method of fig. 19 in accordance with various aspects of the disclosure.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, for ease of description, spaced relationship terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures. In addition to the orientations shown in the drawings, the term spaced apart relationship is intended to include different orientations of the device in use or operation. The device may be otherwise positioned (rotated 90 degrees or at other orientations) and the spaced apart relationship descriptors used herein interpreted accordingly.
Furthermore, when a number or range of numbers is described by "about," "approximately," etc., the term is intended to encompass numbers within a reasonable range that take into account variations inherent in manufacturing processes as understood by those of ordinary skill in the art. For example, the number or range of numbers encompasses a reasonable range of numbers described, including, for example, within +/-10% of the numbers described, based on known manufacturing tolerances associated with manufacturing features having characteristics associated with the numbers. For example, a material layer having a thickness of "about 5nm" may comprise a size range of 4.25nm to 5.75nm, wherein the manufacturing tolerances associated with depositing the material layer are +/-15% as known to one of ordinary skill in the art. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself limit the relationship between the various embodiments and/or configurations discussed.
Metal-Insulator-Metal (MIM) capacitors have been widely used in functional circuits such as mixed signal circuits, analog circuits, radio Frequency (RF) circuits, dynamic Random Access Memories (DRAMs), and logic circuits. In a System On Chip (SOC) application, different capacitors for different functional circuits must be integrated on the same chip to achieve different objectives. For example, in a mixed signal circuit, a capacitor is used as a decoupling capacitor and a high frequency noise filter. For DRAM and embedded DRAM circuits, capacitors are used for memory storage, while for RF circuits, capacitors are used in the oscillator and phase shift network for coupling and/or bypass purposes. For microprocessors, capacitors are used for decoupling. As the name suggests, MIM capacitors include a sandwich of alternating metal layers and insulator layers. An example MIM capacitor includes a plurality of conductor plates, each conductor plate insulated from an adjacent conductor plate by an insulator layer. MIM capacitors are also implemented in high performance computing (HPC, high-performance computing) today. Those MIM capacitors implemented in HPC may require high capacitance. Although existing MIM capacitors may be satisfactory in providing high capacitance, their lifetime may be short because the insulator layer disposed between two adjacent conductor plates may experience Time Dependent Dielectric Breakdown (TDDB) failure.
The present disclosure provides metal-insulator-metal (MIM) capacitors with improved TDDB performance and methods of forming the same. The MIM capacitor includes a multi-layer insulator structure disposed between two adjacent conductor plates. In an exemplary embodiment, a method of forming a MIM capacitor includes depositing a first conductive layer on a substrate, performing an etching process to pattern the first conductive layer to form a first conductive plate, performing a nitridation process to the first conductive plate, forming a first Hafnium Zirconium Oxide (HZO) layer on the first conductive plate, forming a titanium oxide layer or an aluminum oxide layer on the first Hafnium Zirconium Oxide (HZO) layer, and then forming a second hafnium zirconium oxide layer on the titanium oxide layer or the aluminum oxide layer. By interposing a titanium oxide layer or an aluminum oxide layer between the first and second hafnium zirconium oxide layers, defects in the first and second hafnium zirconium oxide layers may not be easily connected (linked). In this way, the conductive path along the grain boundaries of the first and second hafnium zirconium oxide layers may be reduced or eliminated. Thus, the TDDB performance of the MIM capacitor is advantageously improved.
Various aspects of the disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, fig. 1 is a flowchart illustrating a method 100 for fabricating a semiconductor structure according to an embodiment of the present disclosure. The method 100 is described below in connection with fig. 2-18, with fig. 2-18 being partial cross-sectional views of a workpiece 200 at different stages of manufacture in accordance with an embodiment of the method 100. Fig. 19 is a flowchart illustrating a method 300 for fabricating a semiconductor structure according to an embodiment of the present disclosure. The method 300 is described below in connection with fig. 1-18 and 20-24, with fig. 2-24 being partial cross-sectional views of a workpiece 200' at various stages of manufacture in accordance with an embodiment of the method 300. Since the workpiece 200/200 'will be manufactured into a semiconductor structure at the end of the manufacturing process, the workpiece may also be referred to as a semiconductor structure 200/200' depending on the context. Methods 100 and 300 are merely examples and are not intended to limit the present disclosure to what is explicitly shown therein. Additional steps may be provided before, during, and after the method 100/300, and some of the steps described may be replaced, eliminated, or moved for additional embodiments of the method. For simplicity, not all steps are described in detail herein. Moreover, throughout this application, like reference numerals designate like parts unless otherwise specified.
Referring to fig. 1 and 2, the method 100 includes a block 102 of providing a workpiece 200. The workpiece 200 includes a substrate 202, which substrate 202 may be made of silicon or other semiconductor material such as germanium. The substrate 202 may also include a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the substrate 202 may comprise an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In some embodiments, the substrate 202 may include an epitaxial layer, such as an epitaxial layer overlying a bulk semiconductor. Various microelectronic features may be formed in the substrate 202 or on the substrate 202, such as transistor features including source/drain features, gate structures, gate spacers, source/drain contacts, gate contacts, isolation structures including Shallow Trench Isolation (STI), or any other suitable feature. Depending on the context, the source/drain features may be referred to individually or collectively as a source or drain. The transistor formed on the substrate 202 may be a planar device or a multi-gate device. The multi-gate devices include, for example, fin field effect transistors (finfets) or multi-bridge channel (MBC) transistors. A FinFET has elevated channels surrounded by gates on multiple sides (e.g., gate wraps on top and sidewalls of a "fin" of semiconductor material extending from a substrate). MBC transistors have a gate structure that may extend partially or completely around the channel region to provide access to the channel region on two or more sides. MBC transistors may also be referred to as gate-all-around transistors (SGT) or gate-all-around (GAA) transistors because their gate structure surrounds the channel region.
The workpiece 200 also includes a multilayer interconnect (MLI) structure 210 that provides interconnections (e.g., routing) between the various microelectronic components of the workpiece 200. The MLI structure 210 may also be referred to as an interconnect structure 210. The MLI structure 210 may include a plurality of metal layers or metallization layers. In some cases, the MLI structure 210 may include eight (8) to fourteen (14) metal layers. Each metal layer includes a plurality of conductive features embedded in an inter-metal dielectric (IMD) layer. The conductive member may include a contact, a via, or a metal line. The IMD layer may be silicon oxide or a silicon oxide-containing material, with silicon being present in various suitable forms. For example, the IMD layer includes silicon oxide or a low-k dielectric material having a k value (dielectric constant) less than the k value (about 3.9) of silicon oxide. In some embodiments, the low-k dielectric material includes tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, doped silicon oxide (such as borophosphosilicate glass (BPSG), fused Silica Glass (FSG), phosphosilicate glass, silicon oxycarbide (SiOCN), spin-on silicon-based polymer dielectric), combinations thereof, or other suitable materials.
In one embodiment, a carbide layer 220 is deposited over the MLI structure 210. Deposition processes include Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or combinations thereof. Any suitable type of carbide material may be used in carbide layer 220, such as silicon carbide (SiC).
In an embodiment, oxide layer 230 is deposited on carbide layer 220. Any suitable deposition process for oxide layer 230 may be used, including CVD, flowable CVD (FCVD), spin-on, PVD, ALD, or combinations thereof. In one embodiment, oxide layer 230 comprises undoped silicon oxide.
The workpiece 200 also includes a first Etch Stop Layer (ESL) 240 deposited on the oxide layer 230. The first ESL240 may include silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon carbide (SiC), silicon oxynitride (SiOCN), or silicon nitride (SiN), or a combination thereof, and may be formed by Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or a combination thereof.
The workpiece 200 also includes a dielectric layer 250 deposited over the first ESL 240. The composition of dielectric layer 250 may be similar to the composition of oxide layer 230. In some embodiments, dielectric layer 250 comprises undoped quartz glass (USG) or silicon oxide. Dielectric layer 250 may be deposited using CVD, flowable CVD (FCVD), spin-on, PVD, ALD, or combinations thereof.
The workpiece 200 also includes a plurality of lower contact elements (e.g., lower contact element 253, lower contact element 254, and lower contact element 255) formed in the dielectric layer 250. The formation of the lower contact feature may include patterning of the dielectric layer 250 to form a trench, and depositing a barrier layer (not separately labeled) and a metal fill layer (not separately labeled) in the trench. In some embodiments, the barrier layer may comprise titanium nitride or tantalum nitride, and may be conformally deposited using PVD, CVD, metal Organic CVD (MOCVD), or suitable methods. In one embodiment, the barrier layer may comprise tantalum nitride. The metal fill layer may include copper (Cu), and may be deposited using electroplating or electroless plating. After depositing the barrier layer and the metal filling layer, a planarization process, such as a Chemical Mechanical Planarization (CMP) process, may be performed to remove the excess barrier layer and the metal filling layer, thereby forming the lower contact members 253, 254, and 255. Although the lower contact members 253, 254, and 255 are disposed below the upper contact members (e.g., upper contact members 292, 294), the lower contact members 253, 254, and 255 are sometimes referred to as Top Metal (TM) contacts.
The workpiece 200 also includes a second etch stop layer 256 formed directly on the dielectric layer 250. In an embodiment, the second etch stop layer 256 is deposited on the dielectric layer 250 by Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or combinations thereof. The second etch stop layer 256 may include silicon carbonitride (SiCN), silicon nitride (SiN), other suitable materials, or combinations thereof. In this embodiment, the second etch stop layer 256 is in direct contact with the top surfaces of the lower contact members 253, 254, and 255.
The workpiece 200 also includes an oxide layer 258 formed directly on the second etch stop layer 256. In an embodiment, the oxide layer 258 may include undoped quartz glass (USG), silicon oxide, or other suitable material.
Referring to fig. 1 and 3, the method 100 includes a block 104 in which a first conductive layer 262 is formed directly on the oxide layer 258. The first conductive layer 262 may be deposited on the oxide layer 258 using PVD, CVD, or MOCVD, and may cover the entire top surface of the workpiece 200. In some embodiments, the first conductive layer 262 may include titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), copper (Cu), cobalt (Co), nickel (Ni), tungsten (W), aluminum (Al), or other suitable materials. In one embodiment, the first conductive layer 262 includes titanium nitride (TiN).
Referring to fig. 1 and 4, the method 100 includes a block 106 in which a first conductive layer 262 is patterned to form a first conductor plate 262' directly on the lower contact member 254. Patterning may include depositing a hard mask layer on the first conductive layer 262, forming a photoresist layer on the hard mask, patterning the photoresist layer using photolithography, etching the hard mask using the patterned photoresist layer as an etching mask, and then etching the first conductive layer 262 using the patterned hard mask as an etching mask. The hard mask layer and the photoresist layer may be selectively removed. In this embodiment, etching the first conductive layer 262 and/or removing the hard mask layer and photoresist layer forms an oxide layer 263. That is, the top surface and the sidewall surface of the first conductor plate exposed to the etchant are oxidized, thereby forming the oxide layer 263. As shown in fig. 4, the oxide layer 263 extends along the top surface and the sidewall surface of the first conductor plate 262'. In an embodiment in which the first conductive layer 262 includes titanium nitride (TiN), the oxide layer 263 includes titanium oxide (TiO) 2 )。
Referring to fig. 1 and 5, the method 100 includes a block 108, performing a nitridation process 265 on the workpiece 200 in the block 108 to convert the oxide layer 263 into a nitrided oxide layer 263', thereby improving quality at the interface between the first conductor plate 262' and the first insulator structure 264 (shown in fig. 6) to be formed and improving reliability of the final structure of the workpiece 200. In an embodiment, the nitrogen source in nitridation process 265 includes a nitrogen plasma. The nitridation process 265 may be performed at a flow rate of about 8000 seem to about 10000 seem, at a temperature between about 350 ℃ and about 450 ℃, and at a plasma power of about 200W to about 300W for about 20 seconds to 60 seconds to form a satisfactory nitrided layer (e.g., nitrided oxide layer 263') without damaging front end devices (e.g., transistors formed on the substrate 202). After the nitridation process 265 is performed, the oxide layer 263 is nitrided and becomes a nitrided oxide layer 263'. In an embodiment, oxide layer 263 includes titanium oxide (TiO 2 ) The nitrided oxide layer 263' includes titanium oxynitride (TiON). After performing the nitriding process 265, the nitrogen content in the first conductor plate 262' is alsoMay vary. In an embodiment, the nitrogen content of the upper portion of the first conductor plate 262 'is higher than the nitrogen content of the lower portion of the first conductor plate 262'. That is, the upper portion of the first conductor plate 262 'includes titanium nitride (TiN) rich in nitrogen, and the lower portion of the first conductor plate 262' may be a nitrogen-less (nitrogen) hole.
Referring to fig. 1 and 6, the method 100 includes a block 110, where a first insulator structure 264 is formed on a workpiece 200. After patterning the first conductive layer 262 to form the first conductor plate 262', and after performing the nitridation process 265, a first insulator structure 264 is formed. The first insulator structure 264 is conformally formed to have a substantially uniform thickness on the top surface of the workpiece 200 (e.g., substantially the same thickness on the top surface and sidewall surfaces of the nitrided oxide layer 263').
In the present embodiment, to improve Time Dependent Dielectric Breakdown (TDDB) performance, thereby improving reliability of a semiconductor device (e.g., a metal-insulator-metal capacitor), the first insulator structure 264 is a multi-layer structure and includes a conformal first high-K dielectric layer 264a formed directly on the oxide layer 258 and the nitrided oxide layer 263', a conformal second high-K dielectric layer 264b formed directly on the first high-K dielectric layer 264a, and a conformal third high-K dielectric layer 264c formed directly on the second high-K dielectric layer 264 b. In an embodiment, the first high-K dielectric layer 264a, the second high-K dielectric layer 264b, and the third high-K dielectric layer 264c are deposited using thermal Atomic Layer Deposition (ALD) that achieves halide precursors at a temperature between about 200 ℃ and about 400 ℃. The temperature of the thermal ALD may be lower than the temperature of the nitridation process 265. The conformal first high-K dielectric layer 264a is in direct contact with the nitrided oxide layer 263' and the oxide layer 258 and is spaced apart from the first conductor plate 262' by the nitrided oxide layer 263 '.
The first insulator structure 264 has a total thickness T and, in an embodiment, the composition of the first high-K dielectric layer 264a is the same as the composition of the third high-K dielectric layer 264 c. Compared to the embodiment in which the insulator structure is a single layer structure and is formed of a first high-K dielectric layer having a thickness T, a first high-K dielectric layer 264a having a thickness T1 less than the thickness T is formed and hasThe third high-K dielectric layer 264c of thickness T3, which is less than thickness T, will advantageously reduce or prevent crystallization of the first high-K dielectric layer 264a and the third high-K dielectric layer 264c, thereby reducing the formation of conductive paths in the first and third high-K dielectric layers and improving TDDB performance. In an embodiment, the first high-K dielectric layer 264a and the third high-K dielectric layer 264c comprise Hafnium Zirconium Oxide (HZO). To provide a satisfactory forward bias-related TDDB and a satisfactory reverse bias-related TDDB, the ratio of thickness T1 to thickness T3 may be between about 0.9 and about 1.1. In an embodiment, thickness T1 is substantially equal to thickness T3. In some embodiments, each of thickness T1 and thickness T3 is greater thanAnd is less than->
The first insulator structure 264 further includes a second high-K dielectric layer 264b sandwiched between a first high-K dielectric layer 264a and a third high-K dielectric layer 264 c. In an embodiment, the dielectric constant of the second high-K dielectric layer 264b is less than the dielectric constants of the first high-K dielectric layer 264a and the third high-K dielectric layer 264 c. By forming the second high-K dielectric layer 264b between the first high-K dielectric layer 264a and the third high-K dielectric layer 264c, defects in the first high-K dielectric layer 264a and defects in the third low-K dielectric layer 264 may not be easily connected to form conductive paths along grain boundaries of the first high-K dielectric layer and the third high-K dielectric layer, and thus TDDB performance may be improved. The lattice constant of the second high-K dielectric layer 264b is different from the lattice constants of the first high-K dielectric layer 264a and the third high-K dielectric layer 264 c. In an embodiment in which the first and third high-K dielectric layers 264a and 264c include HZO, the second high-K dielectric layer 264b includes aluminum oxide (Al 2 O 3 ). In another embodiment, the second high-K dielectric layer 264b comprises titanium oxide (TiO 2 ). The thickness T2 of the second high-K dielectric layer 264b is less than the thickness T1. In an embodiment, the ratio of thickness T1 to thickness T2 may be greater than 10. The thickness T2 of the second high-K dielectric layer 264b is greater thanAnd is smaller than
Referring to fig. 1 and 7, the method 100 includes a block 112 in which a second conductor plate 266 is formed over the first insulator structure 264. In the present embodiment, the second conductor plate 266 is directly formed on the lower contact member 253 and vertically overlaps the first conductor plate 262'. The second conductor plate 266 may be similar in composition and formation to the first conductor plate 262'. For example, a second conductive layer may be deposited on the workpiece 200 and then patterned to form the second conductor plate 266. In an embodiment, second conductor plate 266 comprises titanium nitride (TiN). In some embodiments, the top surface and sidewall surfaces of the second conductor plate 266 may be oxidized, and the workpiece 200 may thus include titanium oxide formed on the second conductor plate 266. The oxide layer may then be nitrided by a nitridation process similar to nitridation process 265 to form nitrided oxide layer 267 (e.g., ton). Further, the nitrogen content of the upper portion of the second conductor plate 266 is higher than that of the lower portion of the second conductor plate 266.
Referring to fig. 1 and 8, the method 100 includes a block 114, where a second insulator structure 268 is formed over the workpiece 200 in block 114. In an embodiment, the second insulator structure 268 is conformally formed to have a substantially uniform thickness on the top surface of the workpiece 200 (e.g., substantially the same thickness on the top surface and sidewall surfaces of the nitrided oxide layer). In an embodiment, the formation and composition of the second insulator structure 268 is similar to the formation and composition of the first insulator structure 264. For example, the second insulator structure 268 includes a first high-K dielectric layer 268a, a second high-K dielectric layer 268, and a third high-K dielectric layer 268c. In an embodiment, the first high-K dielectric layer 268a is formed, composed, and thick the same as the first high-K dielectric layer 264a, the second high-K dielectric layer 268b is formed, composed, and thick the same as the second high-K dielectric layer 264b, the third high-K dielectric layer 268c is formed, composed, and thick the same as the third high-K dielectric layer 264c, and duplicate descriptions are omitted for simplicity reasons. Accordingly, the TDDB performance of the second insulator structure 268 disposed between the second conductor plate 266 and the third conductor plate 270a can be improved.
Referring to fig. 1 and 9, the method 100 includes a block 116 in which a third conductor plate 270a and a dummy conductive feature 270b are formed on the second insulator structure 268. More specifically, the third conductor plate 270a is formed directly above the lower contact member 254 and vertically overlaps the first and second conductor plates 262' and 266, and the dummy conductor member 270b is formed directly above the lower contact member 253 and vertically overlaps the second conductor plate 266. The formation and composition of the third conductor plate 270a and the dummy conductive member 270b may be similar to those of the first conductor plate 262', and duplicate descriptions are omitted for simplicity. In an embodiment, the third conductor plate 270a and the dummy conductive member 270b include titanium nitride (TiN). A nitridation process similar to nitridation process 265 may be performed. Similarly, the workpiece 200 further includes a nitrided oxide layer 270c formed on the sidewall and top surface of the third conductor plate 270a, and a nitrided oxide layer 270d formed on the sidewall or top surface of the dummy conductive member 270 b. In an embodiment, nitrided oxide layer 270c and nitrided oxide layer 270d include titanium oxynitride (ton). The upper portion of the third conductor plate 270a has a nitrogen content higher than that of the lower portion of the third conductor plate 270a, and the upper portion of the dummy conductive member 270b has a nitrogen content higher than that of the lower portion of the dummy conductive member 270 b.
After the third conductor plate 270a is formed, the structure of the MIM capacitor 272 is finally determined. In the embodiment shown in fig. 9, the workpiece 200 includes a MIM capacitor 272 and a dummy conductive feature 270b formed directly above the lower contact feature 253. In this embodiment, MIM capacitor 272 comprises three vertically stacked conductor plates (i.e., first conductor plate 262', second conductor plate 266, and third conductor plate 270 a), a plurality of insulator structures (i.e., first insulator structure 264 and second insulator structure 268), and a plurality of nitrided oxide layers (e.g., layers 263', 267, 270 c). It should be appreciated that MIM capacitor 272 may include other suitable numbers of conductor plates (e.g., two, four, or more), and that each two adjacent conductor plates are formed from a respective multi-layer insulatorThe structure (e.g., the multi-layer first insulator structure 264) is isolated from the nitrided oxide layer (e.g., nitrided oxide layer 263'). In an embodiment, the first and third high-K dielectric layers (e.g., 264a and 264c, 268a and 268 c) comprise HZO, and the second high-K dielectric layer (e.g., 264b, 268 b) comprises aluminum oxide (Al 2 O 3 ). In another embodiment, the first and third high-K dielectric layers (e.g., 264a and 264c, 268a and 268 c) comprise HZO, and the second high-K dielectric layer (e.g., 264b, 268 b) comprises titanium oxide (TiO 2 )。
Referring to fig. 1 and 10, the method 100 includes a block 118 in which a first passivation structure 274 is formed over the MIM capacitor 272. As shown in fig. 10, MIM capacitor 272 is sandwiched between first passivation structure 274 and oxide layer 258. In some embodiments, the first passivation structure 274 may include a dielectric layer or two or more dielectric layers formed of any suitable material, such as silicon oxide or silicon nitride. In an embodiment, the first passivation structure 274 comprises silicon oxide formed by Plasma Enhanced Chemical Vapor Deposition (PECVD). The thickness of the first passivation structure 274 may be aboutAnd->Between them.
Referring to fig. 1, 11, 12, 13, and 14, method 100 includes block 120 in which conductive via 288 and conductive via 290 are formed. Reference is first made to fig. 11. After forming the first passivation structure 274, a patterned mask 278 is formed over the first passivation structure 274, as shown in fig. 11. The patterned mask 278 includes two openings 278a and 278b exposing portions of the first passivation structure 274 thereunder. For example, the opening 278a exposes a portion of the first passivation structure 274 formed directly above the lower contact member 253, and the opening 278b exposes a portion of the first passivation structure 274 formed directly above the upper contact member 254.
When using the patterned mask 278 as an etch mask, an etch process may be performed to form openings 280 and 282, as shown in fig. 12. The etching process stops at the top surface of the second etch stop layer 256. In an embodiment, an etching process etches through the first passivation structure 274, the nitrided oxide layer 270d, the dummy conductive feature 270b, the second insulator structure 268, the nitrided oxide layer 267, the second conductor plate 266, and the first insulator structure 264 to form the opening 280. The etching process also etches through the first passivation structure 274, the nitrided oxide layer 270c, the third conductor plate 270a, the second insulator structure 268, the first insulator structure 264, the nitrided oxide layer 263 'and the first conductor plate 262' to form an opening 282. In an embodiment, the etching process may include a dry etching process.
Referring to fig. 13, after forming the opening 280 and the opening 282, another etching process is performed to vertically extend the opening 280 and the opening 282 to penetrate the second etch stop layer 256 and expose the lower contact members 253 and 254. Vertically extending openings 280 and 282 may be referred to as opening 284 and opening 286, respectively. In some embodiments, a dry etching process may be used to selectively etch the second etch stop layer 256 to form openings 284 and openings 286. After forming openings 284 and 286, patterned mask 278 may be selectively removed.
After forming the openings 284 and 286, as shown in fig. 14, conductive vias 288 and 290 are formed in the openings 284 or 286, respectively. In this embodiment, to form conductive via 288 and conductive via 290, barrier layer 289a is first conformally deposited over first passivation structure 274 and openings 284 and 286 using a suitable deposition technique (such as ALD, PVD, or CVD), and then metal fill layer 289b is deposited over barrier layer 289a using ALD, PVD, CVD, electroless plating, or electroplating. The barrier layer 289a may include titanium nitride (TiN), tantalum nitride (TaN), or other metal nitrides. The metal fill layer 289b may be formed of copper (Cu), aluminum (Al), aluminum copper (Al-Cu), or other suitable materials. A planarization process (e.g., CMP) may then be performed after the formation of the metal fill layer 289b to finally determine the shapes of the conductive via 288 and the conductive via 290.
Referring to fig. 1, 14, and 15, method 100 includes block 122 performing further processing. Such further processing may include, for example, forming metal lines (e.g., metal lines 292, 294 shown in fig. 14) over the first passivation structure 274. Metal lines 292 and 294 are electrically connected to the conductive vias 288 and 290, respectively, and in direct contact with the conductive vias 288 and 290. In some embodiments, the metal lines 292, 294 may be referred to as upper contact elements and may be part of a redistribution layer (RDL) to reroute the bonded connection between the upper and lower layers. Such further processing may also include forming a second passivation structure 296 (shown in fig. 15) on the workpiece 200. The second passivation structure 296 may be a multi-layer structure. Such further processing may also include forming openings extending through the second passivation structure 296 to expose the metal lines 292, 294, and forming pads in the openings to electrically connect to the metal lines 292 and 294. The bond pad may include multiple layers and forming the multiple layers involves multiple processes. In some embodiments, after first forming the openings to expose the metal lines 292, 294, an Under Bump Metal (UBM) layer may be deposited into the openings, and then a bump layer (e.g., made of copper) is deposited over the UBM layer. A solder layer may then be formed on the bump layer as a connection point to an external circuit.
Fig. 16 depicts a partial cross-sectional view of MIM capacitor 272. More specifically, as shown in fig. 16, a portion of MIM capacitor 272 includes a first conductor plate 262', a nitrided oxide layer 263' extending along sidewalls and a top surface of first conductor plate 262', a first high-K dielectric layer 264a on nitrided oxide layer 263' and in direct contact with nitrided oxide layer 263', a second high-K dielectric layer 264b on first high-K dielectric layer 264a, a third high-K dielectric layer 264c on second high-K dielectric layer 264b, and a second conductor plate 266 on third high-K dielectric layer 264c and overlapping first conductor plate 262'. In an embodiment, the first and third high-K dielectric layers 264a and 264c comprise HZO and the second high-K dielectric layer 264b comprises aluminum oxide (Al 2 O 3 ) Or titanium oxide (TiO) 2 )。
In the above-described embodiments described with reference to fig. 1-16, the first and third high-K dielectric layers 264a and 264c are formed by forming an aluminum oxide (Al 2 O 3 ) Or based on titanium oxide (TiO) 2 ) Is provided for the second high-K dielectric layer 264b of the MIM capacitor 272 to obtain TDDB performanceTo an improvement. In an alternative embodiment, to increase the forward bias breakdown voltage, the first insulator structure may further include a fourth high-K dielectric layer 264d. For example, in the embodiment shown in fig. 17, the first insulator structure 264' includes a first high-K dielectric layer 264a ' and a fourth high-K dielectric layer 264d formed on the first high-K dielectric layer 264a '. The first high-K dielectric layer 264a' has a thickness T and is a single layer formed of a high-K dielectric material (e.g., HZO) (as shown in fig. 17). In the embodiment shown in fig. 18, the first insulator structure 264 "includes the first insulator structure 264 and a fourth high-K dielectric layer 264d formed on the third high-K dielectric layer 264c of the first insulator structure 264. The fourth high-K dielectric layer 264d may be deposited by Plasma Enhanced ALD (PEALD) at a temperature between 150 ℃ and 250 ℃. Forming the fourth high-K dielectric layer 264d increases the overall thickness (e.g., thickness from T to T ') of the insulator structure disposed between two adjacent conductor plates (e.g., conductor plates 262' and 266), thereby increasing the forward bias breakdown voltage of the MIM capacitor 272. In an embodiment, the second high-K dielectric layer 264b comprises aluminum oxide (Al 2 O 3 ) The fourth high-K dielectric layer 264d includes titanium oxide (TiO 2 ). In an embodiment, the second high-K dielectric layer 264b comprises titanium oxide (TiO 2 ) And the fourth high-K dielectric layer 264d also comprises titanium oxide. Since titanium oxide has a high dielectric permittivity (dielectric permittivity), the introduction of the fourth high-K dielectric layer 264d advantageously increases the overall thickness of the insulator structure and the forward bias breakdown voltage of the MIM capacitor 272 without reducing the capacitance of the MIM capacitor 272. In an embodiment, to increase the forward bias breakdown voltage of MIM capacitor 272 without significantly reducing the capacitance of MIM capacitor 272, the thickness T4 of fourth high-K dielectric layer 264d may be aboutAnd->Between them.
While the embodiments shown in fig. 16-18 are directed to an insulator structure between the first conductor plate 262' and the second conductor plate 266, it should be understood that these embodiments also apply to an insulator structure between the second conductor plate 266 and the third conductor plate 270a or any other insulator structure between two adjacent conductor plates. The composition of the second insulator structure may be the same as or different from the composition of the first insulator structure. In some embodiments, the second insulator structure 268 may further include a titanium oxide layer formed on the third high-K dielectric layer 268 c. In alternative embodiments, the first insulator structure 264 may include a titanium oxide layer 264d and the second insulator structure 268 may be free of a titanium oxide layer, with the thickness (e.g., thickness T') of the second insulator structure 268 being less than the thickness (e.g., thickness T) of the first insulator structure 264 d.
In the above-described embodiments described with reference to fig. 1-18, the nitriding process (e.g., nitriding process 265) is performed after the first conductor plate, the second conductor plate, and/or the third conductor plate are formed. Fig. 19 depicts an alternative method 300 of forming a MIM capacitor. Method 300 is similar to method 100. One of the differences between method 100 and method 300 includes replacing the nitridation process (e.g., the nitridation process in block 108) with an ALD process. More specifically, as shown in fig. 20, a first conductor plate 262' is formed and an oxide layer 263 (e.g., tiO is formed in block 106 2 ) Thereafter, the method 300 proceeds to block 108', where in block 108', another oxide layer 401 is deposited on the workpiece 200' prior to forming the first insulator structure 264. In one embodiment, the oxide layer 401 comprises titanium oxide (TiO 2 ) And is formed by ALD. That is, the composition of the oxide layer 401 is the same as that of the oxide layer 263. Oxide layer 401 has higher uniformity, better topography, and fewer defects than oxide layer 263. After the oxide layer 401 is formed, the operations in blocks 110-122 may be performed to complete the fabrication of the workpiece 200'. The workpiece 200' in fig. 20 is similar to the workpiece 200 in fig. 15, one of the differences between the workpiece 200' and the workpiece 200 includes that the workpiece 200' does not have a nitrided oxide layer (e.g., ton), conversely, the workpiece 200' includes an oxide layer 263 extending along the sidewalls and top surface of the first conductor plate 262', and a conformal oxide layer 401 (e.g., tiO) formed over the oxide layer 263 and the oxide layer 258 2 ). SimilarlyThe workpiece 200' may also include oxide layers 403, 404, and 405 formed with the formation of the conductor plates 266 and 270a and the dummy conductive features 270b, respectively, and a conformal oxide layer 402 (e.g., tiO formed by ALD 2 ). Conformal oxide layer 402 is similar to conformal oxide layer 401.
Fig. 22 depicts a partial cross-sectional view of MIM capacitor 272 in workpiece 200'. More specifically, as shown in fig. 22, the workpiece 200 'includes a first conductor plate 262', an oxide layer 263 extending along the side walls and top surface of the first conductor plate 262', an oxide layer 401 on the oxide layer 263 and in direct contact with the oxide layer 263, a first high-K dielectric layer 264a on the oxide layer 401 and in direct contact with the oxide layer 401, a second high-K dielectric layer 264b on the first high-K dielectric layer 264a, a third high-K dielectric layer 264c on the second high-K dielectric layer 264b, and a second conductor plate 266 on the third high-K dielectric layer 264c and overlapping the first conductor plate 262'. In one embodiment, the first and third high-K dielectric layers 264a and 264c comprise HZO and the second high-K dielectric layer 264b comprises aluminum oxide (Al 2 O 3 ) Or titanium oxide (TiO) 2 )。
Methods of increasing the forward bias breakdown voltage (e.g., forming a titanium oxide layer on the first and/or second insulator structures 264/264 '/268) may also be applied to the workpiece 200' to increase the forward bias breakdown voltage of the workpiece 200 '. For example, in the embodiment shown in fig. 23, a first insulator structure 264 'including a first high-K dielectric layer 264a' and a fourth high-K dielectric layer 264d is formed on the oxide layer 401. In the embodiment shown in fig. 24, a first insulator structure 264 "comprising a first insulator structure 264 and a fourth high-K dielectric layer 264d is formed on the oxide layer 401. In an embodiment, the oxide layer 401 and the fourth high-K dielectric layer 264d each comprise titanium oxide (TiO 2 ) And the second high-K dielectric layer 264b includes aluminum oxide (Al 2 O 3 ) Or titanium oxide (TiO) 2 ). The forward bias breakdown voltage of the workpiece 200' may be advantageously increased for similar reasons as described above with reference to fig. 16-18. Although the embodiment shown in figures 22-24 is directed to a first insulator structure between first conductor plate 262' and second conductor plate 266,it should be understood that these embodiments also apply to the insulator structure between the second conductor plate 266 and the third conductor plate 270a or any other insulator structure between two adjacent conductor plates.
Although not intended to be limiting, one or more embodiments of the present disclosure provide a number of benefits to semiconductor structures and their formation. For example, the present disclosure provides a multi-layer insulator structure disposed between two adjacent conductor plates of a metal-insulator-metal capacitor. In the embodiment, the TDDB performance of the metal-insulator-metal capacitor can be improved by providing a multi-layer insulator structure. In some embodiments, the forward bias breakdown voltage of the metal-insulator-metal capacitor may also be increased. Therefore, the overall performance and reliability of the metal-insulator-metal capacitor can be advantageously improved.
The present disclosure provides many different embodiments. Semiconductor structures and methods of making the same are disclosed herein. In one exemplary aspect, the present disclosure is directed to a method. The method comprises the following steps: depositing a first layer of conductive material over a substrate; patterning the first conductive material layer to form a first conductor plate over the substrate; forming a first high-K dielectric layer over the first conductor plate; forming a second high-K dielectric layer over the first high-K dielectric layer; forming a third high-K dielectric layer over the second high-K dielectric layer; and forming a second conductor plate over the third high-K dielectric layer and vertically overlapping the first conductor plate, wherein the composition of the first high-K dielectric layer is the same as the composition of the third high-K dielectric layer and is different from the composition of the second high-K dielectric layer.
In some embodiments, the first high-K dielectric layer and the third high-K dielectric layer may include Hafnium Zirconium Oxide (HZO). In some embodiments, the second high-K dielectric layer may include aluminum oxide (Al 2 O 3 ) Or titanium oxide (TiO) 2 ). In some embodiments, patterning the first conductive material layer includes performing an etching process on the first conductive material layer, wherein performing the etching process further oxidizes the sidewalls and top surface of the first conductor plate to form an oxide layer. In some embodiments, the method may further include, prior to forming the first high-K dielectric layer, performing on the oxide layer And nitriding to form a nitrided oxide layer on the first conductor plate. In some embodiments, after performing the nitriding treatment, a nitrogen content in an upper portion of the first conductor plate is greater than a nitrogen content in a lower portion of the first conductor plate. In some embodiments, the method may further comprise: and forming a fourth high-K dielectric layer on the third high-K dielectric layer, wherein the composition of the fourth high-K dielectric layer is different from the composition of the first high-K dielectric layer. In some embodiments, the composition of the fourth high-K dielectric layer is the same as the composition of the second high-K dielectric layer. In some embodiments, the thickness of the third high-K dielectric layer is substantially equal to the thickness of the first high-K dielectric layer.
In another exemplary aspect, the present disclosure is directed to a method. The method comprises the following steps: forming a first conductor plate on the first insulating layer above the substrate; forming a second insulating layer extending along the top surface and the sidewall surface of the first conductor plate; conformally forming a multi-layer dielectric structure over the first conductor plate, wherein the multi-layer dielectric structure is in direct contact with both the first insulating layer and the second insulating layer, and wherein the multi-layer dielectric structure is formed of a high-K dielectric layer; and forming a second conductor plate over the multi-layer dielectric structure and vertically overlapping the first conductor plate.
In some embodiments, conformally forming the multi-layer dielectric structure includes: conformally depositing a first high-K dielectric layer over the first conductor plate, wherein the first high-K dielectric layer is in direct contact with both the first insulating layer and the second insulating layer; conformally depositing a second high-K dielectric layer over the first high-K dielectric layer; and conformally depositing a third high-K dielectric layer on the second high-K dielectric layer, wherein the composition of the second high-K dielectric layer is different from the composition of the first high-K dielectric layer and the composition of the third high-K dielectric layer. In some embodiments, conformally forming the multi-layer dielectric structure further comprises: a fourth high-K dielectric layer is conformally deposited over the third high-K dielectric layer, wherein a composition of the fourth high-K dielectric layer is different from a composition of the first high-K dielectric layer and a composition of the third high-K dielectric layer. In some embodiments, the composition of the fourth high-K dielectric layer is the same as the composition of the second high-K dielectric layer. In some embodiments, the forming of the first conductor plate includes: depositing a conductive material layer on the first insulating layer; and performing an etching process to pattern the conductive material layer to form a first conductor plate, wherein the performing of the etching process further oxidizes the sidewalls and the top surface of the first conductor plate to form a second insulating layer. In some embodiments, the method may further comprise: after the etching process is performed, nitridation plasma treatment is performed on the second insulating layer. In some embodiments, the method may further comprise: after performing the etching process, a dielectric layer is conformally deposited over the first insulating layer, wherein the composition of the dielectric layer is the same as the composition of the second insulating layer.
In another exemplary aspect, the present disclosure is directed to a semiconductor structure. The semiconductor structure includes: a metal-insulator-metal (MIM) capacitor on a first insulating layer over a substrate, the MIM capacitor comprising: the semiconductor device comprises a first conductor plate, a second insulation layer, a conformal dielectric structure and a second conductor plate, wherein the first conductor plate is positioned on the first insulation layer, the second insulation layer extends along and on the side wall and the top surface of the first conductor plate, the conformal dielectric structure is positioned above the substrate and the first conductor plate, the conformal dielectric structure is formed by a plurality of high-K dielectric layers, and the second conductor plate is positioned above the conformal dielectric structure and vertically overlaps with the first conductor plate, and the conformal dielectric structure is in direct contact with both the second insulation layer and the first insulation layer.
In some embodiments, the conformal dielectric structure may comprise: a first hafnium zirconium oxide layer over the second insulating layer; an aluminum oxide layer on the first hafnium zirconium oxide layer; and a second hafnium zirconium oxide layer on the aluminum oxide layer, wherein the thickness of the first hafnium zirconium oxide layer is substantially equal to the thickness of the second hafnium zirconium oxide layer. In some embodiments, the first conductor plate comprises titanium nitride (TiN) and the second insulating layer comprises titanium oxynitride (TiON). In some embodiments, the nitrogen content in the upper portion of the first conductor plate is greater than the nitrogen content in the lower portion of the first conductor plate.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (10)

1. A method of fabricating a semiconductor structure, comprising:
depositing a first layer of conductive material over a substrate;
patterning the first conductive material layer to form a first conductor plate over the substrate;
forming a first high-K dielectric layer over the first conductor plate;
forming a second high-K dielectric layer over the first high-K dielectric layer;
forming a third high-K dielectric layer over the second high-K dielectric layer; and
forming a second conductor plate positioned above the third high-K dielectric layer and vertically overlapped with the first conductor plate,
Wherein the composition of the first high-K dielectric layer is the same as the composition of the third high-K dielectric layer and is different from the composition of the second high-K dielectric layer.
2. The method of claim 1, wherein the first high-K dielectric layer and the third high-K dielectric layer comprise hafnium zirconium oxide.
3. The method of claim 2, wherein the second high-K dielectric layer comprises aluminum oxide or titanium oxide.
4. The method of claim 1, wherein patterning the first conductive material layer comprises performing an etching process on the first conductive material layer, wherein performing the etching process further oxidizes sidewalls and a top surface of the first conductor plate to form an oxide layer.
5. The method of claim 4, further comprising:
a nitridation process is performed on the oxide layer prior to forming the first high-K dielectric layer, thereby forming a nitrided oxide layer on the first conductor plate.
6. The method of claim 5, wherein after performing the nitriding treatment, a nitrogen content in an upper portion of the first conductor plate is greater than a nitrogen content in a lower portion of the first conductor plate.
7. A method of fabricating a semiconductor structure, comprising:
Forming a first conductor plate on the first insulating layer above the substrate;
forming a second insulating layer extending along a top surface and a sidewall surface of the first conductor plate;
conformally forming a multi-layer dielectric structure over the first conductor plate, wherein the multi-layer dielectric structure is in direct contact with both the first insulating layer and the second insulating layer, and wherein the multi-layer dielectric structure is formed of a high-K dielectric layer; and
a second conductor plate is formed overlying the multi-layer dielectric structure and vertically overlapping the first conductor plate.
8. A semiconductor structure, comprising:
a metal-insulator-metal capacitor on a first insulating layer over a substrate, the metal-insulator-metal capacitor comprising:
a first conductor plate on the first insulating layer,
a second insulating layer extending along and over the sidewalls and top surface of the first conductor plate,
a conformal dielectric structure over the substrate and the first conductor plate, wherein the conformal dielectric structure is formed of a plurality of high-K dielectric layers, an
A second conductor plate over the conformal dielectric structure and vertically overlapping the first conductor plate,
Wherein the conformal dielectric structure is in direct contact with both the second insulating layer and the first insulating layer.
9. The semiconductor structure of claim 8, wherein the conformal dielectric structure comprises:
a first hafnium zirconium oxide layer over the second insulating layer;
an aluminum oxide layer on the first hafnium zirconium oxide layer; and
a second hafnium zirconium oxide layer on the aluminum oxide layer,
wherein the thickness of the first hafnium zirconium oxide layer is equal to the thickness of the second hafnium zirconium oxide layer.
10. The semiconductor structure of claim 8, wherein the first conductor plate comprises titanium nitride and the second insulating layer comprises titanium oxynitride.
CN202311143147.1A 2022-09-08 2023-09-06 Semiconductor structure and manufacturing method thereof Pending CN117320540A (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US63/404,653 2022-09-08
US63/386,789 2022-12-09
US18/188,196 2023-03-22
US18/188,196 US20240088204A1 (en) 2022-09-08 2023-03-22 Metal-Insulator-Metal Capacitors And Methods Of Forming The Same

Publications (1)

Publication Number Publication Date
CN117320540A true CN117320540A (en) 2023-12-29

Family

ID=89283923

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311143147.1A Pending CN117320540A (en) 2022-09-08 2023-09-06 Semiconductor structure and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN117320540A (en)

Similar Documents

Publication Publication Date Title
US10373905B2 (en) Integrating metal-insulator-metal capacitors with air gap process flow
US11031337B2 (en) Forming dual metallization interconnect structures in single metallization level
US10204827B2 (en) Multi-level air gap formation in dual-damascene structure
TW202038383A (en) Semiconductor device and method of forming same
US20240088016A1 (en) Metal-Insulator-Metal Structure
US20240128312A1 (en) Multilayer capacitor electrode
CN113851422A (en) Semiconductor structure and forming method thereof
CN117320540A (en) Semiconductor structure and manufacturing method thereof
CN220569675U (en) Semiconductor structure
US20240088204A1 (en) Metal-Insulator-Metal Capacitors And Methods Of Forming The Same
US20230395487A1 (en) Semiconductor Structures And Methods Of Forming The Same
TW202201541A (en) Semiconductor device, semiconductor packageand method of forming semiconductor device
US20230352395A1 (en) Semiconductor structure and method for forming the same
US11961880B2 (en) Metal-insulator-metal structure
US11791371B2 (en) Resistor structure
US20230238323A1 (en) Interconnect structure including vertically stacked power and ground lines
TW202412241A (en) Semiconductor structure and method for forming the same
US20230352396A1 (en) Dummy Metal-Insulator-Metal Structures Within Vias
US20240113011A1 (en) Semiconductor Structures And Methods Of Forming The Same
TW202114234A (en) Capacitor device and capacitor structure and method for forming the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination