CN117319675A

CN117319675A - Video compression system of server management control chip

Info

Publication number: CN117319675A
Application number: CN202311604436.7A
Authority: CN
Inventors: 李拓; 李晓江; 邹晓峰; 满宏涛; 张贞雷
Original assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Current assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Priority date: 2023-11-28
Filing date: 2023-11-28
Publication date: 2023-12-29
Anticipated expiration: 2043-11-28
Also published as: CN117319675B

Abstract

The embodiment of the application provides a video compression system of a server management control chip, wherein the system comprises: the video compression system comprises N video processing modules which are sequentially connected, N is an integer greater than 1, each video processing module is provided with a switching unit and a video processing unit, an input interface of each switching unit is connected with a data input end of each video processing module, a first output interface of each switching unit is connected with each video processing unit, and each video processing unit is connected with the next-stage video processing module; the exchange unit also comprises a second output interface, and the second output interface is used for directly transmitting the input data transmitted by the data input end to the next stage video processing module under the condition of receiving the exchange instruction of the server management control chip. Through the video compression system stability control method and device, the problem that the stability of the video compression system is weak is solved, and the effect of improving the stability of the video compression system is achieved.

Description

Video compression system of server management control chip

Technical Field

The embodiment of the application relates to the field of computers, in particular to a video compression system of a server management control chip.

Background

At present, as the video compression system has a plurality of modules and the functions of each module are very complex, the abnormal video compression function of the whole video compression system can be caused under the condition that the abnormal working module occurs, in the prior art, a new video compression system is generally built by re-streaming, but the modules causing the abnormal video compression system can not be determined by re-streaming, so that the stability of the video compression system is weaker.

Aiming at the problems of weaker stability and the like of a video compression system in the related art, no effective solution is proposed yet.

Disclosure of Invention

The embodiment of the application provides a video compression system of a server management control chip, which at least solves the problem of weaker stability of the video compression system in the related art.

According to an embodiment of the present application, there is provided a video compression system of a server management control chip, where the video compression system includes N video processing modules sequentially connected, N is an integer greater than 1, each video processing module is configured with a switching unit and a video processing unit, an input interface of the switching unit is connected to a data input end of the video processing module, a first output interface of the switching unit is connected to the video processing unit, and the video processing unit is connected to a next stage video processing module, where the video processing unit in each video processing module is configured to execute a video processing task of each video processing module in the video compression system; the switching unit further comprises a second output interface, wherein the second output interface is used for directly transmitting the input data transmitted by the data input end to the next-stage video processing module under the condition that the switching instruction of the server management control chip is received; the server management control chip is used for sequentially sending the exchange instructions to the exchange units of the N video processing modules under the condition that the video compression function of the video compression system is abnormal, and detecting the running state of the video compression function after each time of sending the exchange instructions; and extracting target video processing modules which cause the video compression function to be abnormal from the N video processing modules according to the running state.

In an exemplary embodiment, the second output interface is connected to the next stage video processing module in a first connection manner, where the first connection manner is used to connect the second output interface to a data output end of the video compression system, and the data output end of the video compression system is connected to a memory on the server management control chip; the second output interface is used for transmitting the input data to the memory through a connection path formed by the first connection mode; the next stage video processing module is used for extracting the input data from the memory.

In an exemplary embodiment, a last stage of the N video processing modules is an output control module, and a data output end of the output control module is connected with the memory; the second output interface is connected with the data output end of the output control module; the second output interface is used for transmitting the input data transmitted by the data input end to the memory through the data output end of the output control module.

In an exemplary embodiment, the first connection is applied to a first video processing module of the N video processing modules, where video processing tasks performed by the first connection affect video compression functions.

In an exemplary embodiment, the N video processing modules include: the system comprises a capturing module, a scaling module, a color space conversion module, a block data generation module, an encryption module and an output control module; the first video processing module includes: the capture module, the color space conversion module, the block data generation module, and the output control module.

In an exemplary embodiment, the second output interface is connected to the next-stage video processing module in a second connection manner, where the second connection manner is used to connect the second output interface to a data input end of the next-stage video processing module; the second output interface is configured to directly transmit the input data to the next stage video processing module through a connection path formed by the second connection mode.

In an exemplary embodiment, a multiplexer is further disposed in the video processing module, and the multiplexer is connected between the video processing unit and the next stage video processing module; the second output interface is connected with the multiplexer; the second output interface is used for directly transmitting the input data transmitted by the data input end to the next stage video processing module through the multiplexer.

In an exemplary embodiment, the second connection is applied to a second video processing module of the N video processing modules, where video processing tasks performed by the second connection do not affect video compression functions.

In an exemplary embodiment, the N video processing modules include: the system comprises a capturing module, a scaling module, a color space conversion module, a block data generation module, an encryption module and an output control module; the second video processing module includes: the scaling module and the encryption module.

In an exemplary embodiment, the server management control chip is further configured to control the target video processing module to detect an abnormality cause that causes the abnormality of the video compression function after extracting the target video processing module that causes the abnormality of the video compression function from the N video processing modules according to the operation state.

In an exemplary embodiment, the video processing unit of the target video processing module is configured with a plurality of detection points, the detection points being task stages in the video processing unit performing corresponding video processing tasks; the server management control chip is used for sending a detection instruction to the target video processing module, wherein the detection instruction is used for indicating the target video processing module to detect the fault of the video processing unit; the target video processing module is used for responding to the detection instruction, taking each detection point in the plurality of detection points as a target detection point, and detecting a target running state of a target task stage when the video processing unit executes a corresponding video processing task to reach the target task stage of the target detection point; comparing the running state with a target expected state of the target task stage; and under the condition that the target running state is inconsistent with the target expected state, determining the target detection point as a fault point.

In an exemplary embodiment, the target video processing module includes a desired analysis module and a hardware self-checking module, where the desired analysis module configures the plurality of detection points and a desired state corresponding to each detection point; the hardware self-checking module is used for extracting each detection point from the expected analysis module as a target detection point under the condition of receiving the detection instruction, and detecting the target running state of the target task stage; comparing the target running state with a target expected state of the target task stage; and under the condition that the target running state is inconsistent with the target expected state, determining the target detection point as a fault point.

In one exemplary embodiment, in a case where the target video processing module is a capturing module, the plurality of detection points include: an ending stage of the frame RGB data, an ending stage of the next line, and a digital stage of the RGB data input to the post-stage module per frame at the current resolution; the expected state corresponding to the ending phase of the frame RGB data comprises an expected ending signal of the frame RGB data; the expected state corresponding to the ending stage of the next row comprises the step of acquiring an expected ending signal of the next row; the desired state corresponding to the number phase of the RGB data input to the rear module per frame at the current resolution includes a desired number of the RGB data input to the rear module per frame at the current resolution.

In one exemplary embodiment, in a case where the target video processing module is a scaling module, the plurality of detection points include: a filtering start stage, a filtering end stage, and a number stage of RGB data output to a post-stage module; the expected states corresponding to the filtering start phase comprise filtering start states; the expected states corresponding to the filtering ending stage comprise filtering ending states; the desired state corresponding to the number of stages of RGB data output to the post-stage module includes a desired number of RGB data output to the post-stage module.

In one exemplary embodiment, in the case where the target video processing module is a color space conversion module, the plurality of detection points include: the effective calculated YUV data stage is a clipping stage for completing the resolution of the current resolution and the number of YUV data which is subjected to resolution clipping and is output to a rear module; the expected states corresponding to the valid calculated YUV data phases include valid calculated YUV expected data; the expected states corresponding to the clipping stage of the current resolution completion resolution include the expected resolution of clipping of the current resolution completion resolution; the expected state corresponding to the number of YUV data which should be output to the post module after resolution clipping includes the expected number of YUV data which should be output to the post module after resolution clipping.

In one exemplary embodiment, in a case where the target video processing module is a block data generation module, the plurality of detection points include: a generation stage of Y data block data, a generation stage of U data block data, a generation stage of V data block data, and a data output stage of the block data generation module in a current compression mode; the expected state corresponding to the generation stage of the Y data block data comprises the completion of the generation of the Y data block data; the expected state corresponding to the generation stage of the U data block data comprises the completion of the generation of the U data block data; the expected state corresponding to the generation stage of the V data block data comprises the completion of the generation of the V data block data; the expected state corresponding to the data output stage of the block data generation module in the current compression mode comprises the expected data volume output by the block data generation module in the current compression mode.

In one exemplary embodiment, in a case where the target video processing module is an encryption module, the plurality of detection points include: a software configuration stage, completing an encryption result stage and combining the encrypted data; the expected state corresponding to the software configuration stage comprises the step of acquiring a key required by the encryption of the software configuration; the expected state corresponding to the encryption result stage is completed and comprises the expected length of the encrypted data; the expected state corresponding to the data combination stage of encryption completion includes the combination of data of which encryption completion is completed.

In one exemplary embodiment, in a case where the target video processing module is an output control module, the plurality of detection points include: a frame header information inputting stage, a frame tail information inputting stage, a memory interaction stage, a frame header information writing stage, and a memory writing stage for writing the frame length of the current frame; the expected state corresponding to the input frame header information stage comprises the detected input frame header information; the expected state corresponding to the input end-of-frame information stage comprises the detected end-of-frame information; the expected state corresponding to the memory interaction phase comprises that a channel of a bus interacted with the memory generates valid data and is a normal burst operation; the expected state corresponding to the frame header information writing stage comprises the steps of writing the frame header information into a memory, obtaining an effective address cached in the memory and triggering interrupt notification software to read; writing the frame length of the current frame into the expected state corresponding to the memory stage comprises writing the frame length of the current frame into the memory and obtaining a valid address cached in the memory and triggering interrupt notification software to read.

In an exemplary embodiment, the target video processing module is further configured to repair the fault point with repair logic corresponding to the target detection point after determining that the target detection point is the fault point.

In an exemplary embodiment, a hardware repair module is further disposed in the target video processing module; and the hardware repair module is used for taking over the target task stage in the process of executing the corresponding video processing task by the video processing unit.

In an exemplary embodiment, the server management control chip is further configured to send a resume instruction to the video processing module to which the exchange instruction is sent after each detection of the running state; and the video processing module is used for recovering to output data through the first output interface under the condition that the recovery instruction is received.

According to another embodiment of the present application, there is provided a server management control chip including: the video compression system comprises N video processing modules which are sequentially connected, N is an integer larger than 1, a switching unit and a video processing unit are arranged in each video processing module, an input interface of the switching unit is connected with a data input end of the video processing module, a first output interface of the switching unit is connected with the video processing unit, the video processing unit is connected with a next-stage video processing module, and the video processing unit in each video processing module is used for executing video processing tasks of each video processing module in the video compression system; the switching unit further comprises a second output interface, wherein the second output interface is used for directly transmitting the input data transmitted by the data input end to the next-stage video processing module under the condition that the switching instruction of the server management control chip is received; the processor is used for sequentially sending the exchange instructions to the exchange units of the N video processing modules under the condition that the video compression function of the video compression system is abnormal, and detecting the running state of the video compression function after each time of sending the exchange instructions; and extracting target video processing modules which cause the video compression function to be abnormal from the N video processing modules according to the running state.

Through the application, the video compression system comprises N video processing modules which are sequentially connected, N is an integer greater than 1, a switching unit and a video processing unit are deployed in each video processing module, an input interface of the switching unit is connected with a data input end of the video processing module, a first output interface of the switching unit is connected with the video processing unit, the video processing unit is connected with a next-stage video processing module, and the video processing unit in each video processing module is used for executing video processing tasks of each video processing module in the video compression system; the exchange unit also comprises a second output interface, wherein the second output interface is used for directly transmitting the input data transmitted by the data input end to the next stage video processing module under the condition of receiving an exchange instruction of the server management control chip; the server management control chip is used for sequentially sending exchange instructions to the exchange units of the N video processing modules under the condition that the video compression function of the video compression system is abnormal, and detecting the running state of the video compression function after each time of sending the exchange instructions; and extracting target video processing modules which cause abnormal video compression functions from the N video processing modules according to the running states. Under the condition that the video compression function of the video compression system is abnormal, the server management control chip is used for sequentially sending exchange instructions to the exchange units of the N video processing modules, and the target video processing module causing the video compression function to be abnormal is detected from the N video processing modules, so that the problem that the stability of the video compression system is weaker can be solved, and the effect of improving the stability of the video compression system is achieved.

Drawings

FIG. 1 is a schematic diagram of a video compression system of a server management control chip according to an embodiment of the present application;

FIG. 2 is a schematic diagram II of a video compression system with a server management control chip according to an embodiment of the present application;

FIG. 3 is a schematic diagram III of a video compression system of a server management control chip according to an embodiment of the present application;

FIG. 4 is a schematic diagram of the operation of a video compression system according to an embodiment of the present application;

FIG. 5 is a schematic diagram of the operation of a capture module according to an embodiment of the present application;

FIG. 6 is a schematic diagram of the operation of a scaling module according to an embodiment of the present application;

FIG. 7 is a schematic diagram of the operation of a color space conversion module according to an embodiment of the present application;

FIG. 8 is a schematic diagram of the operation of a block data generation module according to an embodiment of the present application;

FIG. 9 is a schematic diagram of the operation of an encryption module according to an embodiment of the present application;

FIG. 10 is a schematic diagram of the operation of an output control module according to an embodiment of the present application;

fig. 11 is a schematic diagram of a server management control chip according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will be described in detail below with reference to the accompanying drawings in conjunction with the embodiments.

It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.

In this embodiment, a video compression system of a server management control chip is provided, fig. 1 is a schematic diagram of a video compression system of a server management control chip according to an embodiment of the present application, as shown in fig. 1, the video compression system includes N video processing modules (102-1 to 102-N) sequentially connected, N is an integer greater than 1, a switching unit 104 and a video processing unit 106 are disposed in each of the video processing modules, an input interface 108 of the switching unit 104 is connected to a data input end of the video processing module, a first output interface 110 of the switching unit 104 is connected to the video processing unit 106, and the video processing unit 106 is connected to a next stage video processing module, where the video processing unit 106 in each of the video processing modules is configured to perform a video processing task in the video compression system; the switching unit 104 further includes a second output interface 112, where the second output interface 112 is configured to directly transmit the input data transmitted by the data input end to the next stage video processing module when receiving a switching instruction of the server management control chip; the server management control chip is used for sequentially sending the exchange instructions to the exchange units of the N video processing modules under the condition that the video compression function of the video compression system is abnormal, and detecting the running state of the video compression function after each time of sending the exchange instructions; and extracting target video processing modules which cause the video compression function to be abnormal from the N video processing modules according to the running state.

According to the video compression system with the server management control chip, the server management control chip is used for sequentially sending the exchange instructions to the exchange units of the N video processing modules under the condition that the video compression function of the video compression system is abnormal, and the target video processing module which causes the video compression function to be abnormal is detected from the N video processing modules, so that the problem that the stability of the video compression system is weak can be solved, and the effect of improving the stability of the video compression system is achieved.

Alternatively, in this embodiment, the video compression system may be widely used in a scene, which may include, but is not limited to: video compression scenes, image compression scenes, audio compression scenes, etc., the above-described video compression system will be described by taking, as an example, but not limited to application to video compression scenes, in the following embodiments, but not limited to usage scenes.

Alternatively, in this embodiment, the video compression system may be, but not limited to, disposed on a server management control chip, and the server management control chip controls the video compression system. Alternatively, the device may be disposed on a device other than the server management control chip, the device disposed on the video compression system may be managed by the server management control chip, or the like.

Optionally, in this embodiment, the video compression system may, but is not limited to, compress and output input data by using N video processing modules connected in sequence, where the input data may, but is not limited to, include: video data, image data, text data, audio data, and the like. Under the condition that input data are different, N video processing modules connected in sequence in the video compression system have different processing capacities, such as: in the case that the input data is video data, the video compression system is configured to compress the input video data and output the compressed video data, where N video processing modules sequentially connected in the video compression system may, but are not limited to, include: a capturing module, a scaling module, a color space conversion module, a BLOCK (BLOCK data) generation module, JPEG IP (a module for compressing YUV data in BLOCK format into JPEG format), an encryption module, an output control module, and the like. Or, in the case that the input data is image data, the video compression system is configured to compress the input image data and output the compressed image data, where N video processing modules sequentially connected in the video compression system may include, but are not limited to: a mapper, a quantizer, a symbol encoder, a symbol decoder, an inverse mapper, etc.

Optionally, in this embodiment, each video processing module in the video compression system may, but is not limited to, deploy the switching unit and the video processing unit, each video processing module may, but is not limited to, be responsive to control of a server management control chip, which may, but is not limited to, control the video processing module by instructions, which may, but is not limited to, include: exchange instructions, process instructions, data acquisition instructions, etc.

Optionally, in this embodiment, the video processing module receives the input data through the data input terminal, and may, but is not limited to, connect the data input terminal of the video processing module with the input interface of the switching unit. Alternatively, but not limited to, the switching unit may be disposed at a data output of the video processing module, with an input interface of the switching unit being the data input of the video processing module.

Alternatively, in this embodiment, the first output interface of the switching unit may, but is not limited to, transmit the input data acquired from the data input end of the video processing module to the video processing unit for performing the video processing task, and the video processing unit may, but is not limited to, be configured to output the data to the data input end of the next stage video processing module when the video processing task is completed.

Optionally, in this embodiment, each video processing module may, but is not limited to, have its corresponding video processing task, such as: taking the example that the video processing module comprises a capturing module, a scaling module, a color space conversion module, a BLOCK (BLOCK data) generating module, a JPEG IP, an encryption module and an output control module, the video processing task of the capturing module can be but not limited to capturing the original RGB image; the video processing tasks of the scaling module may include, but are not limited to, adjusting the resolution of the video; the video processing tasks of the color space conversion module may include, but are not limited to, matrix converting the RGB data; the video processing task of the BLOCK data generating module may include, but is not limited to, converting YUV (a color coding method, Y representing brightness, U and V representing chromaticity) format data into YUV BLOCK data; the video processing tasks of JPEG IP may include, but are not limited to, compressed video in JPEG format including output standards; the video processing task of the encryption module may include, but is not limited to, encrypting video data in JPEG format; the video processing task of the output control module may, but is not limited to, writing the encrypted data into the storage space, then informing the software of the frame header and frame end information by means of a register in units of frames, and then reading by the driver.

Optionally, in this embodiment, the video compression function of the video compression system may be implemented by, but not limited to, N video processing modules included in the video compression system, where an abnormality in the video compression function of the video compression system may be, but not limited to, an indication that an abnormality exists in N video processing modules included in the video compression system, and in a case where an abnormality occurs in the video compression function of the video compression system, the server management control chip may be, but not limited to, a detection of a video processing module that fails in the video compression system by issuing a switching instruction, for example: and shorting the video processing module which receives the exchange instruction from the video compression system, thereby detecting whether the input data which does not pass through the shorted video processing module can be normally output, and further determining whether the shorted video processing module is normal.

Thus, the switching instruction may be, but is not limited to, a video processing module for shorting a video processing module that receives the switching instruction from a video compression system, the video processing module being responsive to the switching instruction to be shorted from the video compression system by the switching unit, the shorting may be, but is not limited to, a manner that includes directly transmitting input data transmitted at a data input of the video processing module that receives the switching instruction to a next stage video processing module.

Optionally, in this embodiment, the video processing module directly transmits the input data transmitted from the data input terminal to the next stage video processing module through the switching unit, so the switching unit may, but is not limited to, be used to directly transmit the input data transmitted from the data input terminal to the next stage video processing module. Alternatively, the switching unit may also, but not limited to, transmit the input data transmitted from the data input terminal to a designated storage location, and the next-stage video processing module directly obtains the input data from the designated storage location, so as to directly transmit the input data transmitted from the data input terminal to the next-stage video processing module, and so on.

Alternatively, in this embodiment, the switching instruction may be sent to the switching unit of each of the N video processing modules in the video compression system in turn, for example: taking the example that the video compression system comprises a video processing module A, a video processing module B, a video processing module C and a video processing module D which are sequentially connected, wherein the video processing module A comprises a switching unit A, the video processing module B comprises a switching unit B, the video processing module C comprises a switching unit C, and the video processing module D comprises a switching unit D, the video compression system can send switching instructions to the switching unit A which is included in the video processing module A, and detects the running state of the video compression function of the video compression system after input data in the video compression system does not pass through the switching unit A, so as to determine whether the video processing module A has abnormality; under the condition that the video processing module A is detected and determined to be abnormal, an exchange instruction is sent to an exchange unit B included in the video processing module B, and the running state of a video compression function of the video compression system after input data in the video compression system does not pass through the exchange unit B is detected, so that whether the video processing module B is abnormal or not is determined; under the condition that the detection determines that the video processing module A and the video processing module B are not abnormal, sending an exchange instruction to an exchange unit C included in the video processing module C, and detecting the running state of a video compression function of the video compression system after input data in the video compression system does not pass through the exchange unit C, so as to determine whether the video processing module C is abnormal; under the condition that the detection and determination result shows that the video processing module A, the video processing module B and the video processing module C are not abnormal, an exchange instruction is sent to an exchange unit D included in the video processing module D, and the running state of the video compression function of the video compression system after input data in the video compression system does not pass through the exchange unit D is detected, so that whether the video processing module D is abnormal or not is determined.

Or, but not limited to, sending exchange instructions to the exchange units of a plurality of video processing modules in the N video processing modules in the video compression system at the same time to obtain a video processing module set with abnormal video processing modules, and determining a target video processing module with abnormality from the video processing module set through the exchange units.

Alternatively, in this embodiment, the input data transmitted from the data input terminal may be directly transmitted to the next stage video processing module through the second output interface of the switching unit, but is not limited to this. Or, the second output interface of the switching unit is used for transmitting the input data transmitted by the data input end to the designated storage position, and the next-stage video processing module directly acquires the input data from the designated storage position, so that the input data transmitted by the data input end is directly transmitted to the next-stage video processing module and the like.

Alternatively, in this embodiment, the switching unit may be, but not limited to, an interface, a functional module, or the like, which is used to receive the input data transmitted by the data input terminal and transmit the input data transmitted by the data input terminal.

In an exemplary embodiment, a second output interface is connected to the next stage video processing module in a first connection manner, where the first connection manner is used to connect the second output interface to a data output end of the video compression system, and the data output end of the video compression system is connected to a memory on the server management control chip; the second output interface is used for transmitting the input data to the memory through a connection path formed by the first connection mode; the next stage video processing module is used for extracting the input data from the memory.

Optionally, in this embodiment, the server management control chip deploys a memory, where the memory is connected to a data output end of the video compression system, and the memory may be, but is not limited to, configured to receive and store data processed by the video compression system, and transmit the data processed by the video compression system to the client for display.

Optionally, in this embodiment, the video processing module may, but is not limited to, be configured with a switching unit and a video processing unit, and the video processing unit may, but is not limited to, be connected to a next stage video processing module through an output end, and transmit data for performing a task of completing video processing to the next stage video processing module.

Meanwhile, the switching unit may be connected to the next stage video processing module through, but not limited to, a second output interface, and the switching unit may be connected to the next stage video processing module through, but not limited to, a transmission path between the switching unit and the next stage video processing module through the second output interface, so as to be capable of transmitting data to the next stage video processing module, and the second output interface may be connected to the next stage video processing module through, but not limited to, a first connection manner, for example: the second output interface is connected with the data output end of the video compression system, and the data output end of the video compression system is connected with the memory on the server management control chip, so that the next-stage video processing module can acquire input data stored in the memory from the memory on the server management control chip, and a transmission path of the second output interface and the next-stage video processing module is formed.

In an exemplary embodiment, fig. 2 is a schematic diagram two of a video compression system of a server management control chip according to an embodiment of the present application, as shown in fig. 2, a last stage of N video processing modules (102-1 to 102-N) is an output control module 202, and a data output end 204 of the output control module 202 is connected to the memory; the second output interface 112 is connected to the data output end 204 of the output control module 202; the second output interface 112 is configured to transmit the input data transmitted by the data input terminal to the memory through the data output terminal 204 of the output control module 202.

Optionally, in this embodiment, the video compression system includes N video processing modules sequentially connected, where the nth video processing module is an output control module, and the output control module may be, but is not limited to, connected to a memory disposed on the server management control chip, and transmits data processed by the video compression system to the memory for storage.

Optionally, in this embodiment, the second output interface of the switching unit may be, but is not limited to, connected to the data output end of the output control module, so as to transmit the input data input by the video processing module from the data input end of the video processing module to the data output end of the output control module, so that the output control module transmits the data processed by the video compression system to the memory for storage.

In an exemplary embodiment, the first connection is applied to a first video processing module of the N video processing modules, where video processing tasks performed by the first video processing module affect video compression functions.

Optionally, in this embodiment, the first video processing module includes a video processing module that performs a video processing task to affect a video compression function of the video compression system, and may, but is not limited to, determine whether there is an impact on the video compression function of the video compression system according to whether the overall flow of video compression performed by the video compression system is affected.

In one exemplary embodiment, the N video processing modules include: the system comprises a capturing module, a scaling module, a color space conversion module, a block data generation module, an encryption module and an output control module; the first video processing module includes: the capture module, the color space conversion module, the block data generation module, and the output control module.

Optionally, in this embodiment, the video compression system includes a capturing module, a scaling module, a color space conversion module, a block data generation module, an encryption module, and an output control module that are sequentially connected.

Alternatively, in this embodiment, the capture module may operate, but is not limited to, by: the capture module captures and captures raw video data from the VGA (Video Graphics Array ), which may be, but is not limited to, in the form of RGB images, which in the case of capture module capturing RGB images of raw video data, may be, but is not limited to, converted to digital signals for subsequent compression and processing operations.

Alternatively, in the present embodiment, the scaling module may operate, but is not limited to, by: adjusting the resolution of the input data may include, but is not limited to, adjusting the resolution in a small direction, thereby reducing the amount of data of the compressed video, such as: will 1024 (J) 768 is adjusted to 800 +.>600, etc.

Alternatively, in the present embodiment, the color space conversion module may operate, but is not limited to, by: the color space conversion module performs matrix conversion on input data, which may include, but is not limited to, RGB data, the conversion process of which is completed using a matrix conversion formula. Matrix conversion formulas may include, but are not limited to: y= (0.257)R)+（0.504/>G）+(0.098/>B)+16；U=0.148/>R–0.291/>G+0.439/>B+128；V=0.439/>R-0.368/>G-0.071/>B+128, wherein the coefficients may be, but are not limited to, adaptively adjusted according to the actual situation.

Alternatively, in the present embodiment, the block data generation module may operate, but is not limited to, by: converting YUV format data into YUV BLOCK data, i.e. BLOCK data, wherein the size of the BLOCK can be but not limited to 16 according to YUV444 and YUV420 compression formats16，16/>8，8/>8, etc., thus 16 y_rams, 16 u_rams, 16 v_rams are required for data buffering.

The principle in YUV420 mode is to retain all Y data, and to retain even rows and even columns of U/V data, and thus can operate, but is not limited to, by: y data of the 0 th row, the 16 th row, the 32 nd row and the 48 th row … … are written into Y_RAM_0 in sequence; writing Y data of row 1, row 17, row 33, and row 49, … …, into y_ram_1; writing Y data of row 2, row 18, row 34, row 50, … … into y_ram_2; until the complete Y data from row 0 to row 15 is written. Writing even column U data of row 0, row 16, row 32, row 48, row … … into u_ram_0; writing even column U data of row 2, row 18, row 34, row 50, … … into u_ram_1; until the even column U data of the 14 th, 30 th, 46 th, 62 th, and … … th rows are written into the u_ram_7, and the even column U data of the 14 th, 30 th, 46 th, and 62 th rows … … are written into the u_ram_7. Writing even column U data of row 0, row 16, row 32, row 48, row … … into v_ram_0; writing even column U data of row 2, row 18, row 34, row 50, … … into v_ram_1; until the even column U data of the 14 th, 30 th, 46 th, 62 th rows … … is written into v_ram_7.

The principle in YUV444 mode is to retain Y, U, V data for all rows and all columns and therefore can operate, but is not limited to, by: writing Y data of row 0, row 8, row 16, and row 24, … … into y_ram_0; writing Y data of row 1, row 9, row 17, and row 25 … … into y_ram_1; writing Y data of row 2, row 10, row 18, row 26, … … into y_ram_2; until the Y data of the 7 th, 15 th, 23 rd, 31 st line … … is written into the y_ram_7. Writing U data of row 0, row 8, row 16, and row 24 … … into U_RAM_0; writing U data of the 1 st row, the 9 th row, the 17 th row and the 25 th row … … into the U_RAM_1; writing U data of row 2, row 10, row 18, row 26 and row … into U_RAM_2; until the U data of the 7 th, 15 th, 23 rd, 31 st line … … is written into the u_ram_7. Writing V data of row 0, row 8, row 16, row 24, … … into v_ram_0; writing V data of row 1, row 9, row 17, row 25, … into v_ram_1; writing V data of row 2, row 10, row 18, row 26, … … into v_ram_2; until the V data of the 7 th, 15 th, 23 rd, 31 st line … … is written into v_ram_7.

YUV read side control logic in YUV420 mode is: sequentially reading Y_RAM_0 16 times, Y_RAM_ … … 16 times and Y_RAM_15 times 16 times to form 1616, and sequentially reading 8 times U_RAM_0,8 times U_RAM_1 and 8 times U_RAM_7 to form 8 +.>8 U_BLOCK data, 8 times V_RAM_0,8 times V_RAM_1,8 times V_RAM_7 are sequentially read to form 8->V_block data of 8 are sequentially looped.

YUV read side control logic in YUV444 mode is: sequentially reading 8 times of Y_RAM_0 and 8 times of Y_RAM_ … … 8 times of Y_RAM_7 to form 8 times of Y_RAM_78 Y_BLOCK data, 8 times U_RAM_0,8 times U_RAM_1,8 times U_RAM_7 are sequentially read to form 8->8 U_BLOCK data, 8 times V_RAM_0,8 times V_RAM_1,8 times V_RAM_7 are sequentially read to form 8->V_block data of 8.

Alternatively, in this embodiment, the encryption module may operate, but is not limited to, by: the encryption module encrypts the video data in the JPEG format, and the encryption manner may include, but is not limited to, AES128, AES256, RC4, and the like.

Alternatively, in the present embodiment, the output control module may operate, but is not limited to, by: the encrypted Data is written into a memory, which may include, but is not limited to, DDR (Double Data Rate) and then the frame header and frame end information are notified to the software by means of a register in frame units and then read by a driver of an EMAC (electronic computer).

Optionally, in this embodiment, according to the working modes of the capturing module, the scaling module, the color space conversion module, the block data generating module, the encryption module and the output control module, the video processing tasks executed by the capturing module, the color space conversion module, the block data generating module and the output control module affect the video compression function, so that the first video processing module includes: the system comprises a capturing module, a color space conversion module, a block data generation module and an output control module.

In an exemplary embodiment, a second output interface is connected to the next-stage video processing module in a second connection manner, where the second connection manner is used to connect the second output interface to a data input end of the next-stage video processing module; the second output interface is configured to directly transmit the input data to the next stage video processing module through a connection path formed by the second connection mode.

Meanwhile, the switching unit may be connected to the next stage video processing module through, but not limited to, a second output interface, and the switching unit may be connected to the next stage video processing module through, but not limited to, a transmission path between the switching unit and the next stage video processing module through the second output interface, so as to be capable of transmitting data to the next stage video processing module, and the second output interface may be connected to the next stage video processing module through, but not limited to, a second connection manner, for example: the second output interface is directly connected with the data input end of the next-stage video processing module, and a transmission path of the second output interface and the next-stage video processing module is formed.

In an exemplary embodiment, fig. 3 is a schematic diagram III of a video compression system of a server management control chip according to an embodiment of the present application, as shown in fig. 3, a multiplexer 304 is further disposed in the video processing module 302, and the multiplexer 304 is connected between the video processing unit 306 and the next stage video processing module 308; the second output interface 112 is connected to the multiplexer 304; the second output interface 112 is configured to directly transmit the input data transmitted from the data input terminal to the next stage video processing module 308 through the multiplexer 304.

Alternatively, in this embodiment, the multiplexer may be, but not limited to, used to directly transmit the input data transmitted from the data input terminal to the data input terminal of the next stage video processing module.

In an exemplary embodiment, the second connection is applied to a second video processing module of the N video processing modules, where video processing tasks performed by the second video processing module do not affect video compression functions.

Optionally, in this embodiment, the second video processing module includes a video processing module that performs a video processing task and has no influence on a video compression function of the video compression system, and may, but is not limited to, determine whether there is an influence on the video compression function of the video compression system according to whether the overall flow of video compression performed by the video compression system is influenced.

In one exemplary embodiment, the N video processing modules include: the system comprises a capturing module, a scaling module, a color space conversion module, a block data generation module, an encryption module and an output control module; the second video processing module includes: the scaling module and the encryption module.

Optionally, in this embodiment, according to the working modes of the capturing module, the scaling module, the color space conversion module, the block data generating module, the encryption module and the output control module, the video processing tasks executed by the scaling module and the encryption module do not affect the video compression function, so that the scaling module and the encryption module are determined to be the second video processing module.

In one exemplary embodiment, an example of the operation of a video compression system is provided. Fig. 4 is a schematic diagram illustrating an operation procedure of a video compression system according to an embodiment of the present application, and as shown in fig. 4, N video processing modules of the video compression system are respectively: a capturing module, a scaling module, a color space conversion module, a block data generation module, a JPEG IP (joint photographic experts group intellectual property core) module, an encryption module, and an output control module, comprising, with a first video processing module: the system comprises a capturing module, a color space conversion module, a block data generation module and an output control module, wherein the second video processing module comprises: for example, the scaling module and the encryption module process the original video data of the HOST (HOST) to form RGB data after the video graphics array VGA, where the RGB data has two output modes, one is a DVI mode (i.e., output 1 of the VGA) and the other is a buffer mode (i.e., output 2 of the VGA).

The video processing module may, but not limited to, respond to control of a management module of the server management control chip, and the server management control chip management module may, but not limited to, be configured to, in a case where an abnormality occurs in a video compression function of the video compression system, sequentially send an exchange instruction to the exchange units of the N video processing modules, and detect an operation state of the video compression function after each sending of the exchange instruction; and extracting target video processing modules which cause abnormal video compression functions from the N video processing modules according to the running states.

The capturing module captures an original RGB image, including an original RGB image in a DVI mode or a buffer mode, it should be noted that, for the buffer mode, the VGA writes the original data into a double rate synchronous dynamic random access memory (DDR) buffer of the VGA (may, but is not limited to, acquire a part of DDR buffer space to store as a video memory of the VGA), and the capturing module actively reads the RGB original data from the DDR, otherwise, the DVI mode pushes the original RGB image to the capturing module by the VGA.

In the event of an abnormality in the video compression function of the video compression system, the target video processing module causing the abnormality in the video compression function may be detected, but is not limited to, by:

the server management control chip management module sequentially sends an exchange instruction to each video processing module, for a first video processing module, the video processing module transmits received input data to a data output end of an output control module through a connection path formed by a first connection mode, the output control module transmits the received input data to the DDR, a next stage video processing module connected with the video processing module acquires the input data from the DDR, a subsequent video processing task is sequentially executed, and whether the video processing module is a target video processing module or not is determined by detecting the running state of a video compression function, and further description is made by taking a block data generation module as an example, wherein the video processing module in the first video processing module can but is not limited to adopt a similar processing mode:

The server management control chip management module sends an exchange instruction to the exchange unit of the block data generation module, the exchange unit of the block data generation module responds to the exchange instruction and transmits input data transmitted by a data input end to the output control module in a first connection mode, and then the output control module transmits the input data to the DDR, wherein the exchange unit can be used for converting the input data into a format which can be transmitted by the output control module, the output control module can be used for converting the input data into a format which can be recognized and stored by the DDR and then transmitting the converted input data into the DDR for storage, and the input data transmitted by the data input end of the block data generation module can be used for being processed by the capture module, the scaling module and the color space conversion module before the input data are processed.

After the exchange unit of the block data generating module transmits the input data to the DDR, the JPEG IP may, but is not limited to, acquire the input data transmitted by the block data generating module from the DDR as the input data of the JPEG IP and sequentially process the input data to obtain the data output by the output control module, and finally detect the operation state of the video compression function according to the data output by the output control module, thereby detecting whether the block data generating module is a target video processing unit.

For the second video processing module, the video processing module directly transmits the received input data to the next stage of video processing module through a connection path formed by the second connection mode, so as to determine whether the video processing module is a target video processing module, and the scaling module is taken as an example for further explanation, and the video processing module in the second video processing module can but is not limited to adopt a similar processing mode:

the server management control chip management module sends an exchange instruction to the exchange unit of the scaling module, the exchange unit of the scaling module responds to the exchange instruction and transmits input data transmitted by the data input end to the color space conversion module through the multiplexer to carry out subsequent processing work, and finally the running state of the video compression function is detected according to the data output by the output control module, so that whether the block scaling module is a target video processing unit is detected.

In an exemplary embodiment, the server management control chip is further configured to control the target video processing module to detect an abnormality cause causing the abnormality of the video compression function after extracting the target video processing module causing the abnormality of the video compression function from the N video processing modules according to the operation state.

Alternatively, in this embodiment, the video processing module may perform the video processing task through a plurality of task phases, and may detect an abnormal cause that causes an abnormality in the video compression function of the video processing module by detecting a processing condition that the video processing module performs each task phase.

Alternatively, in this embodiment, the video compression system may, but is not limited to, include one or more video processing modules that are abnormal, and may, but is not limited to, determine, in turn, each abnormal video processing module as a target video processing module to perform the detection operation.

In one exemplary embodiment, a video processing unit of a target video processing module is configured with a plurality of detection points, the detection points being task stages in a corresponding video processing task performed by the video processing unit; the server management control chip is used for sending a detection instruction to the target video processing module, wherein the detection instruction is used for indicating the target video processing module to detect the fault of the video processing unit; the target video processing module is used for responding to the detection instruction, taking each detection point in the plurality of detection points as a target detection point, and detecting a target running state of a target task stage when the video processing unit executes a corresponding video processing task to reach the target task stage of the target detection point; comparing the running state with a target expected state of the target task stage; and under the condition that the target running state is inconsistent with the target expected state, determining the target detection point as a fault point.

Optionally, in this embodiment, each video processing module performs a video processing task corresponding to each video processing module in the video compression system, where the video processing module may, but is not limited to, perform the video processing task by executing a plurality of task phases, and may, but is not limited to, set a corresponding detection point at each task phase, for example: and setting a detection point for acquiring and detecting data output by the task stage under the condition that the task stage is ended. Alternatively, during execution of the task phase, a detection point is set for detecting whether or not the period of time for executing the task phase exceeds a threshold value or the like.

Alternatively, in this embodiment, the server management control chip may, but not limited to, send the detection instruction to the target video processing module, and the target video processing module may, but not limited to, perform task phase detection in response to the detection instruction. The detection point may be, but is not limited to being issued by a detection instruction, such as: and the target video processing module receives the detection instruction and obtains a target detection point through analysis. Alternatively, the detection instructions may be, but are not limited to, used to trigger a detection point, such as: one or more detection points are stored in the target video processing module, and under the condition that a detection instruction is received, the corresponding target detection points are triggered to detect a task stage and the like.

Alternatively, in this embodiment, the target expected state of the target task stage may be obtained according to, but not limited to, the detection point, and the target expected state corresponding to the target detection point is obtained when the target detection point is determined. Or, obtaining the target expected state of the target task stage according to the detection instruction, for example: and obtaining a target expected state corresponding to the target detection point through analyzing the detection instruction.

Optionally, in this embodiment, the target video processing module includes a desired analysis module and a hardware self-checking module, and the desired analysis module may store the detection point and the desired state corresponding to the detection point.

Optionally, in this embodiment, in the case of receiving the detection instruction, the hardware self-checking module may, but is not limited to, extract the target detection point from the expected analysis module, and compare the target running state of the target video processing unit with the target expected state to detect whether the target detection point is a fault point.

Alternatively, in this embodiment, the target desired state of the target task stage may be, but not limited to, issued by the server management control chip or pre-stored in the target video processing module.

Optionally, in the present embodiment, an example of a detection point of the capturing module and a target expected state is provided, the detection point of the capturing module includes an ending phase (one_frame_end) of the frame RGB data, an ending phase (one_line_end) of the next line, and, at the current resolutionThe digital value phase (data_cnt) of the RGB data input to the post-stage module per frame may include, but is not limited to, a destination desired state next_state of each detection point in the capture module including get_one_frame_end, get_one_line_end, out_data_cnt, where get_one_frame_end is used to indicate a desired end signal of the RGB data of the frame is acquired, get_one_line_end is used to indicate a desired end signal of the next line is acquired, out_data_cnt is used to indicate a desired number of the RGB data input to the post-stage module per frame at the current resolution, such as: at 800At 600 resolution, out_data_cnt=800 +.>600 =240000 RGB data.

Optionally, in this embodiment, an example of the detection point of the scaling module and the target desired state is provided, where the detection point of the scaling module includes a filter start stage (filter_begin), a filter end stage (filter_end), and a number stage (data_cnt) of RGB data output to the post-stage module, the target desired state next_state of each detection point in the scaling module may include, but is not limited to, begin_ filter, filter _end, out_data_cnt, where begin_filter is used to indicate the filter start state, filter_end is used to indicate the filter end state, and out_data_cnt is used to indicate the desired number of RGB data output to the post-stage module.

Optionally, in this embodiment, an example of a detection point of the color space conversion module and a target expected state is provided, where the detection point of the color space conversion module includes an effective calculated YUV data stage (yuv_vld), a clipping stage (rsl _ mdy) for completing resolution for the current resolution, and a number stage (out_data_cnt) of YUV data that should be output to a post module after resolution clipping, and the target expected state next_state of each detection point in the color space conversion module may include, but is not limited to, get_yuv_vld, get_ rsl _ mdy, get_out_data_cnt, where get_yuv_vld is used to indicate effective calculated YUV expected data, get_ rsl _ mdy is used to indicate the expected resolution for completing clipping for the resolution for the current resolution, and get_out_data_cnt is used to indicate the expected number of YUV data that should be output to the post module after resolution clipping.

Optionally, in this embodiment, an example of the detection point of the BLOCK data generating module and the target expected state is provided, where the detection point of the BLOCK data generating module includes a generation stage (y_block) of Y data BLOCK data, a generation stage (u_block) of U data BLOCK data, a generation stage (v_block) of V data BLOCK data, and an output data stage (out_data_cnt) of the BLOCK data generating module in the current compression mode, and the target expected state next_state of each detection point in the BLOCK data generating module may include, but is not limited to, get_y_block, get_u_block, get_v_block, get_out_data_cnt, where get_y_block is used to indicate that generation of Y data BLOCK data is completed, get_u_block is used to indicate that generation of V data BLOCK data is completed, and get_out_cnt is used to indicate that generation of V data BLOCK data is completed.

Optionally, in this embodiment, an example of a detection point and a target expected state of the encryption module is provided, where the detection point of the encryption module includes a software configuration stage (secret_key), a complete encryption result stage (secret_result), and a data combination stage (get_256 Bytes) where each detection point in the encryption module includes a target expected state, which may include, but is not limited to, get_secret_key, get_secret_result, get_256Bytes, where get_secret_key is used to indicate that a key required for completing encryption is acquired by the software configuration, get_secret_result is used to indicate a desired length of encrypted data, and get_256Bytes is used to indicate a combination of data that completes encryption.

Optionally, in this embodiment, an example of a detection point of the output control module and a target expected state is provided, where the detection point of the output control module includes an input frame header information stage (frame_header), an input frame end information stage (frame_end), a memory interaction stage (axi_aw_w), a frame header information writing memory stage (frame_header_addr), and a frame length writing memory stage (frame_length_addr) of the current frame, and the target expected state of each detection point in the output control module may include, but is not limited to, get_frame_header, get_frame_end, get_axi_aw_w, get_frame_header_addr, get_frame_length_addr, the get_frame_header is used for indicating that the input frame header information is detected, the get_frame_end is used for indicating that the input frame end information is detected, the get_axi_aw_w is used for indicating that a channel of a bus interacting with the memory generates valid data and is a normal burst operation, the get_frame_header_addr is used for indicating that the frame header information is written into the memory and valid addresses cached in the memory are obtained and interrupt notification software reading is triggered, and the get_frame_length_addr is used for indicating that the frame length of the current frame is written into the memory and valid addresses cached in the memory are obtained and interrupt notification software reading is triggered.

Alternatively, in this embodiment, the target video processing module may, but is not limited to, use a spare working module to replace the fault point to perform working so as to repair the fault point. Or, reporting the fault point.

Alternatively, in the present embodiment, the hardware repair module may have a function capable of operating instead of the failure point, but is not limited thereto.

Alternatively, in the present embodiment, the hardware repairing module using the capturing module may perform repairing, but is not limited to, including: under the condition that the reason of the abnormality is positioned that the expected end signal of the frame RGB data cannot be obtained, the hardware repair module can take over the data on the DVI interface or the AXI interface into the hardware repair module, calculate the end mark of the frame RGB data through the hardware repair module, and replace the frame end mark in the original logic with the end mark for repair; or, in the case that the expected end signal of the line cannot be obtained due to the abnormal reason, the hardware repair module may take over the data on the DVI interface or the AXI interface into the hardware repair module, calculate to obtain the end mark of the line, and replace the end mark of the line in the original logic with the end mark to repair; alternatively, when it is located that the reason for the abnormality is that the desired number of RGB data input to the post-stage module per frame at the current resolution is abnormal, the hardware repair module may take over the processed RGB data again to the inside of the present module to count again, and output to the post-stage module.

Alternatively, in the present embodiment, the hardware repairing module using the scaling module may perform repairing, but is not limited to, including: when the hardware repair module locates that the reason for the abnormality is abnormal output counting function, namely the expected number of RGB data output to the post-stage module by the scaling module is abnormal, the control logic in the hardware repair module takes over the filtered RGB data into the module again to count again and then outputs the RGB data to the post-stage module.

Optionally, in this embodiment, after detecting the running state each time, the server management control chip sends a recovery instruction to the video processing module that has sent the exchange instruction, and resumes the next detection operation performed by its machine or resumes its operation in the video compression system.

In one exemplary embodiment, an example of the operation of a capture module is provided. Fig. 5 is a schematic diagram of a working process of a capturing module according to an embodiment of the present application, as shown in fig. 5, the capturing module receives input data through a data input end 1, the data input end 1 is connected with an input interface of a switching unit, under the condition that the capturing module receives a switching instruction, the switching unit of the capturing module transmits the input data to a data output end of a video compression system through a second output interface 2, a next stage video processing module of the capturing module acquires data transmitted by the capturing module to perform subsequent processing, if a video processing result of the video compression system at this time is still abnormal and an abnormal phenomenon is consistent with the previous one, it is indicated that the capturing module is normal, a cause of abnormal video compression function is not the capturing module, and positioning analysis needs to be continuously performed on other modules.

If the video processing result of the video compression system is normal at this time, the capturing module is determined as a target video processing module, and the capturing module is continuously positioned and analyzed as follows:

the server management control chip sends a detection instruction to the capture module, the hardware self-checking module of the capture module responds to the detection instruction to extract a target detection point from the expected analysis module, the target running state of the target task stage is detected, the target running state is compared with the target expected state of the target task stage, and the target detection point is determined to be a fault point under the condition that the target running state is inconsistent with the target expected state.

Using a hardware repair module to try to repair the existing hardware problem, under the condition that the expected end signal of the frame RGB data cannot be obtained due to the abnormal reason, the hardware repair module can take over the data on the DVI interface or the AXI interface into the hardware repair module, calculate the end mark of the frame RGB data through the hardware repair module, and replace the end mark of the frame in the original logic with the end mark for repair; or, in the case that the expected end signal of the line cannot be obtained due to the abnormal reason, the hardware repair module may take over the data on the DVI interface or the AXI interface into the hardware repair module, calculate to obtain the end mark of the line, and replace the end mark of the line in the original logic with the end mark to repair; alternatively, when it is located that the reason for the abnormality is that the desired number of RGB data input to the post-stage module per frame at the current resolution is abnormal, the hardware repair module may take over the processed RGB data again to the inside of the present module to count again, and output to the post-stage module.

Second, the capturing module further includes a data retention module, where the data retention module is used to retain key information of internal processing, because the processing speed of the hardware is faster, and retain all key information of internal data processing of the data retention module, such as all current configurations, FIFO (First In First Out, a first-in first-out data storage) state, jump flow of the state machine, etc., and then write the key information into the memory through the switching unit, and perform reading analysis by software.

In one exemplary embodiment, an example of the operation of a scaling module is provided. Fig. 6 is a schematic diagram of a working process of a scaling module according to an embodiment of the present application, as shown in fig. 6, the scaling module receives input data through a data input end 1, the data input end 1 is connected with an input interface of a switching unit, the switching unit of the scaling module transmits the input data to a multiplexer, the multiplexer directly transmits the input data to a next stage video processing module for subsequent processing without passing through the video processing unit, if a video processing result of the video compression system is still abnormal and an abnormal phenomenon is consistent with the previous one, it is indicated that the scaling module is normal, a cause of the abnormal video compression function is not the module, and positioning analysis needs to be continuously performed on other modules.

If the video processing result of the video compression system is normal at this time, determining the scaling module as a target video processing module, and continuing to locate and analyze the scaling module, wherein the method specifically comprises the following steps: the server management control chip sends a detection instruction to the scaling module, the hardware self-checking module of the scaling module responds to the detection instruction to extract a target detection point from the expected analysis module, the target running state of the target task stage is detected, the target running state is compared with the target expected state of the target task stage, and the target detection point is determined to be a fault point under the condition that the target running state is inconsistent with the target expected state.

When the hardware repair module is used for attempting to repair the existing hardware problem, when the hardware repair module is positioned that the abnormality cause is abnormal output counting function, the control logic in the hardware repair module takes over the filtered RGB data into the module again for counting again, and then outputs the RGB data to the later-stage module.

The scaling module further comprises a data retention module, wherein the data retention module has the function of retaining key information of internal processing, and because the processing speed of hardware is faster, all key information of the internal data processing of the data retention module, such as all current configurations, real-time space-full states of the FIFO, jump flow of a state machine and the like, are retained, and then the key information is written into a memory through a switching unit and is read and analyzed by software.

In one exemplary embodiment, an example of the operation of a color space conversion module is provided. Fig. 7 is a schematic diagram of a working process of a color space conversion module according to an embodiment of the present application, as shown in fig. 7, the color space conversion module receives input data through a data input end 1, the data input end 1 is connected with an input interface of an exchange unit, the exchange unit of the color space conversion module transmits the input data to a multiplexer under the condition that the color space conversion module receives an exchange instruction, the multiplexer directly transmits the input data to a next stage video processing module for subsequent processing without passing through a video processing unit, if a video processing result of a video compression system at the moment is still abnormal and an abnormal phenomenon is consistent with the previous one, it is indicated that the color space conversion module is normal, a reason for causing video compression function abnormality is not the module, and positioning analysis needs to be continuously performed on other modules.

If the video processing result of the video compression system is normal at this time, the color space conversion module is determined as a target video processing module, and the positioning analysis of the color space conversion module is continued, specifically as follows: the server management control chip sends a detection instruction to the color space conversion module, the hardware self-checking module of the color space conversion module responds to the detection instruction to extract a target detection point from the expected analysis module, the target running state of the target task stage is detected, the target running state is compared with the target expected state of the target task stage, and the target detection point is determined to be a fault point under the condition that the target running state is inconsistent with the target expected state.

The color space conversion module also comprises a data retention module, wherein the data retention module has the function of retaining key information of internal processing, and the key information of the internal data processing of the data retention module, such as all current configurations, real-time space-full states of the FIFO, jump flow of a state machine and the like, is retained because the processing speed of the hardware is faster, and then is written into a memory through an exchange unit to be read and analyzed by software.

In one exemplary embodiment, an example of the operation of a block data generation module is provided. Fig. 8 is a schematic diagram of a working process of a block data generating module according to an embodiment of the present application, as shown in fig. 8, the block data generating module receives input data through a data input end 1, the data input end 1 is connected with an input interface of an exchange unit, under the condition that the block data generating module receives an exchange instruction, the exchange unit of the block data generating module transmits the input data to a multiplexer, the multiplexer directly transmits the input data to a next stage video processing module for subsequent processing without passing through a video processing unit, if a video processing result of a video compression system at the moment is still abnormal and an abnormal phenomenon is consistent with the previous one, it is indicated that the block data generating module is normal, a reason for causing video compression function abnormality is not the module, and positioning analysis needs to be continuously performed on other modules.

If the video processing result of the video compression system is normal at this time, determining the block data generating module as a target video processing module, and continuing to locate and analyze the block data generating module, wherein the method specifically comprises the following steps: the server management control chip sends a detection instruction to the block data generation module, the hardware self-checking module of the block data generation module responds to the detection instruction to extract a target detection point from the expected analysis module, the target running state of the target task stage is detected, the target running state is compared with the target expected state of the target task stage, and the target detection point is determined to be a fault point under the condition that the target running state is inconsistent with the target expected state.

An attempt is made to repair existing hardware problems using a hardware repair module that aims to attempt to repair existing hardware problems, and when Y_BLOCK data is not waiting, either the generation logic of Y_BLOCK or the on-chip Y_RAM is determined to be abnormal. The hardware repair module is to discard a part of U/V data, keep Y data as much as possible, because Y is brightness, U/V is chromaticity, human eyes are more sensitive to Y component, so at this time, the hardware repair module controls the flow direction of Y data to write into U_RAM, and controls U/V component to write into V_RAM, and in order to realize the correspondence of the whole number of Y_BLOCK U_BLOCK V_BLOCK, the number of U_BLOCK/V_BLOCK needs to be duplicated in YUV444 mode, because 8 is reserved originally at this time The U component of 8 is kept only 8 +.>4, while still requiring an output to JPEG IP 8->8, thus will be 84 copy one copy to 8->8 likewise, it is originally necessary to retain 8 +.>The V component of 8 is kept only 8 +.>4, while still requiring an output to JPEG IP 8->8, thus 8 +.>4 copy one copy to 8->8, and no such processing is required in YUV420 mode, since in YUV420 mode the size of Y is 16 +.>16, and U/V is 8 +.>8, the lower 8 +_ that can be fully placed with 16 U_RAM sets>UV component and V component of 8.

When the U_BLOCK data is not waiting, judging whether the generation logic of the U_BLOCK or the on-chip U_RAM is abnormal. At this time, the hardware repair module is to buffer U/V components with 16 U_RAMs, respectively generating 8U_block and v_block of 8.

When the V_BLLOCK data is not waited, judging that the generation logic of the V_BLOCK or the on-chip V_RAM is abnormal, at the moment, the hardware repair module needs to buffer U/V components by using 16 V_RAMs to generate 8 respectivelyU_block and v_block of 8.

When the abnormality is located to be the abnormality of the output counting module, the control logic in the hardware repairing module counts the processed Y_BLOCK/U_BLOCK/V_BLOCK data again and outputs the processed Y_BLOCK/U_BLOCK/V_BLOCK data to the later-stage module.

And secondly, the block data generating module further comprises a data retaining module, wherein the data retaining module has the function of retaining key information of internal processing, and because the processing speed of hardware is faster, all key information of the internal data processing of the data retaining module, such as all current configurations, real-time space-full states of the FIFO, jump flow of a state machine and the like, are retained, and then are written into a memory through a switching unit and are read and analyzed by software.

In one exemplary embodiment, an example of the operation of an encryption module is provided. Fig. 9 is a schematic diagram of a working process of an encryption module according to an embodiment of the present application, as shown in fig. 9, the encryption module receives input data through a data input end 1, the data input end 1 is connected with an input interface of a switching unit, the switching unit of the encryption module transmits the input data to a multiplexer under the condition that the encryption module receives a switching instruction, the multiplexer directly transmits the input data to a next stage video processing module for subsequent processing without passing through a video processing unit, if a video processing result of the video compression system is still abnormal and an abnormal phenomenon is consistent with the previous one, it is indicated that the encryption module is normal, a cause of the abnormal video compression function is not the module, and positioning analysis needs to be continuously performed on other modules.

If the video processing result of the video compression system is normal at this time, the encryption module is determined as a target video processing module, and the encryption module is continuously positioned and analyzed, specifically as follows: the server management control chip sends a detection instruction to the encryption module, the hardware self-checking module of the encryption module responds to the detection instruction to extract a target detection point from the expected analysis module, the target running state of the target task stage is detected, the target running state is compared with the target expected state of the target task stage, and the target detection point is determined to be a fault point under the condition that the target running state is inconsistent with the target expected state.

The encryption module also comprises a data retention module, wherein the data retention module has the function of retaining key information of internal processing, and the key information of the internal data processing of the data retention module, such as all current configurations, real-time space-full states of the FIFO, jump flows of a state machine and the like, is retained because the processing speed of the hardware is faster, and then is written into a memory through a switching unit and is read and analyzed by software.

In one exemplary embodiment, an example of the operation of an output control module is provided. Fig. 10 is a schematic diagram of a working process of an output control module according to an embodiment of the present application, as shown in fig. 10, the output control module receives input data through a data input end 1, the data input end 1 is connected with an input interface of a switching unit, the switching unit of the output control module transmits the input data to a multiplexer under the condition that the output control module receives a switching instruction, the multiplexer directly transmits the input data to a next stage video processing module for subsequent processing without passing through a video processing unit, if a video processing result of the video compression system at this time is still abnormal and an abnormal phenomenon is consistent with the previous one, it is indicated that the output control module is normal, a cause of abnormal video compression function is not the module, and positioning analysis needs to be continuously performed on other modules.

If the video processing result of the video compression system is normal at this time, determining the output control module as a target video processing module, and continuing to locate and analyze the output control module, wherein the method specifically comprises the following steps: the server management control chip sends a detection instruction to the output control module, the hardware self-checking module of the output control module responds to the detection instruction to extract a target detection point from the expected analysis module, the target running state of the target task stage is detected, the target running state is compared with the target expected state of the target task stage, and the target detection point is determined to be a fault point under the condition that the target running state is inconsistent with the target expected state.

The hardware repair module is used for attempting to repair the existing hardware problems, and secondly, the output control module further comprises a data retention module, wherein the data retention module has the function of retaining key information of internal processing, and because the processing speed of hardware is faster, all key information of the internal data processing of the data retention module, such as all current configurations, real-time space-full states of the FIFO, jump flow of the state machine and the like, are retained, and then are written into a memory through the exchange unit and are read and analyzed by software.

Also provided in this embodiment is a server management control chip, and fig. 11 is a schematic diagram of a server management control chip according to an embodiment of the present application, where, as shown in fig. 11, the server management control chip includes a video compression system 1102 and a processor 1104, where, the video compression system 1102 includes N video processing modules (1106-1 to 1106-N) that are sequentially connected, N is an integer greater than 1, an exchange unit 1108 and a video processing unit 1110 are disposed in each of the video processing modules (1106-1 to 1106-N), an input interface 1112 of the exchange unit 1108 is connected to a data input of the video processing module, a first output interface 1114 of the exchange unit 1108 is connected to the video processing unit 1110, and the video processing unit 1110 is connected to a next-stage video processing module, where, the video processing unit in each of the video processing modules is used to perform a video processing task in the video compression system; the switching unit 1108 further includes a second output interface 1116, where the second output interface 1116 is configured to directly transmit the input data transmitted by the data input end to the next-stage video processing module when receiving a switching instruction of the server management control chip; the processor 1104 is configured to send the switching instructions to the switching units of the N video processing modules in sequence when the video compression function of the video compression system is abnormal, and detect an operation state of the video compression function after each sending of the switching instructions; and extracting target video processing modules which cause the video compression function to be abnormal from the N video processing modules according to the running state.

According to the server management control chip, under the condition that the video compression function of the video compression system is abnormal, the server management control chip is used for sequentially sending the exchange instructions to the exchange units of the N video processing modules, and the target video processing module causing the video compression function to be abnormal is detected from the N video processing modules, so that the problem that the stability of the video compression system is weak can be solved, and the effect of improving the stability of the video compression system is achieved.

Optionally, in this embodiment, the second output interface is connected to the next stage video processing module in a first connection manner, where the first connection manner is used to connect the second output interface to a data output end of the video compression system, and the data output end of the video compression system is connected to a memory on the server management control chip; the second output interface is used for transmitting the input data to the memory through a connection path formed by the first connection mode; the next stage video processing module is used for extracting the input data from the memory.

Optionally, in this embodiment, a last stage of the N video processing modules is an output control module, and a data output end of the output control module is connected to the memory; the second output interface is connected with the data output end of the output control module; the second output interface is used for transmitting the input data transmitted by the data input end to the memory through the data output end of the output control module.

Optionally, in this embodiment, the first connection manner is applied to a first video processing module that affects a video compression function of the video processing tasks performed by the N video processing modules.

Optionally, in this embodiment, the N video processing modules include: the system comprises a capturing module, a scaling module, a color space conversion module, a block data generation module, an encryption module and an output control module; the first video processing module includes: the capture module, the color space conversion module, the block data generation module, and the output control module.

Optionally, in this embodiment, the second output interface is connected to the next stage video processing module in a second connection manner, where the second connection manner is used to connect the second output interface to a data input end of the next stage video processing module; the second output interface is configured to directly transmit the input data to the next stage video processing module through a connection path formed by the second connection mode.

Optionally, in this embodiment, a multiplexer is further disposed in the video processing module, and the multiplexer is connected between the video processing unit and the next stage video processing module; the second output interface is connected with the multiplexer; the second output interface is used for directly transmitting the input data transmitted by the data input end to the next stage video processing module through the multiplexer.

Optionally, in this embodiment, the second connection manner is applied to a second video processing module that does not affect the video compression function of the video processing tasks executed by the N video processing modules.

Optionally, in this embodiment, the N video processing modules include: the system comprises a capturing module, a scaling module, a color space conversion module, a block data generation module, an encryption module and an output control module; the second video processing module includes: the scaling module and the encryption module.

Optionally, in this embodiment, the server management control chip is further configured to, after extracting, from the N video processing modules according to the running state, a target video processing module that causes an abnormality in the video compression function, control the target video processing module to detect an abnormality cause that causes the abnormality in the video compression function.

Optionally, in this embodiment, the video processing unit of the target video processing module is configured with a plurality of detection points, where the detection points are task stages in the video processing unit executing a corresponding video processing task; the server management control chip is used for sending a detection instruction to the target video processing module, wherein the detection instruction is used for indicating the target video processing module to detect the fault of the video processing unit; the target video processing module is used for responding to the detection instruction, taking each detection point in the plurality of detection points as a target detection point, and detecting a target running state of a target task stage when the video processing unit executes a corresponding video processing task to reach the target task stage of the target detection point; comparing the running state with a target expected state of the target task stage; and under the condition that the target running state is inconsistent with the target expected state, determining the target detection point as a fault point.

Optionally, in this embodiment, the target video processing module includes an expected analysis module and a hardware self-checking module, where the expected analysis module configures the plurality of detection points and an expected state corresponding to each detection point; the hardware self-checking module is used for extracting each detection point from the expected analysis module as a target detection point under the condition of receiving the detection instruction, and detecting the target running state of the target task stage; comparing the target running state with a target expected state of the target task stage; and under the condition that the target running state is inconsistent with the target expected state, determining the target detection point as a fault point.

Optionally, in this embodiment, in a case where the target video processing module is a capturing module, the plurality of detection points include: an ending stage of the frame RGB data, an ending stage of the next line, and a digital stage of the RGB data input to the post-stage module per frame at the current resolution; the expected state corresponding to the ending phase of the frame RGB data comprises an expected ending signal of the frame RGB data; the expected state corresponding to the ending stage of the next row comprises the step of acquiring an expected ending signal of the next row; the desired state corresponding to the number phase of the RGB data input to the rear module per frame at the current resolution includes a desired number of the RGB data input to the rear module per frame at the current resolution.

Optionally, in this embodiment, in a case where the target video processing module is a scaling module, the plurality of detection points include: a filtering start stage, a filtering end stage, and a number stage of RGB data output to a post-stage module; the expected states corresponding to the filtering start phase comprise filtering start states; the expected states corresponding to the filtering ending stage comprise filtering ending states; the desired state corresponding to the number of stages of RGB data output to the post-stage module includes a desired number of RGB data output to the post-stage module.

Optionally, in this embodiment, in a case where the target video processing module is a color space conversion module, the plurality of detection points include: the effective calculated YUV data stage is a clipping stage for completing the resolution of the current resolution and the number of YUV data which is subjected to resolution clipping and is output to a rear module; the expected states corresponding to the valid calculated YUV data phases include valid calculated YUV expected data; the expected states corresponding to the clipping stage of the current resolution completion resolution include the expected resolution of clipping of the current resolution completion resolution; the expected state corresponding to the number of YUV data which should be output to the post module after resolution clipping includes the expected number of YUV data which should be output to the post module after resolution clipping.

Optionally, in this embodiment, in a case where the target video processing module is a block data generating module, the plurality of detection points include: a generation stage of Y data block data, a generation stage of U data block data, a generation stage of V data block data, and a data output stage of the block data generation module in a current compression mode; the expected state corresponding to the generation stage of the Y data block data comprises the completion of the generation of the Y data block data; the expected state corresponding to the generation stage of the U data block data comprises the completion of the generation of the U data block data; the expected state corresponding to the generation stage of the V data block data comprises the completion of the generation of the V data block data; the expected state corresponding to the data output stage of the block data generation module in the current compression mode comprises the expected data volume output by the block data generation module in the current compression mode.

Optionally, in this embodiment, in a case where the target video processing module is an encryption module, the plurality of detection points include: a software configuration stage, completing an encryption result stage and combining the encrypted data; the expected state corresponding to the software configuration stage comprises the step of acquiring a key required by the encryption of the software configuration; the expected state corresponding to the encryption result stage is completed and comprises the expected length of the encrypted data; the expected state corresponding to the data combination stage of encryption completion includes the combination of data of which encryption completion is completed.

Optionally, in this embodiment, in a case where the target video processing module is an output control module, the plurality of detection points include: a frame header information inputting stage, a frame tail information inputting stage, a memory interaction stage, a frame header information writing stage, and a memory writing stage for writing the frame length of the current frame; the expected state corresponding to the input frame header information stage comprises the detected input frame header information; the expected state corresponding to the input end-of-frame information stage comprises the detected end-of-frame information; the expected state corresponding to the memory interaction phase comprises that a channel of a bus interacted with the memory generates effective data and is normal burst operation; the expected state corresponding to the frame header information writing stage comprises the steps of writing the frame header information into a memory, obtaining an effective address cached in the memory and triggering interrupt notification software to read; writing the frame length of the current frame into the expected state corresponding to the memory stage comprises writing the frame length of the current frame into the memory and obtaining a valid address cached in the memory and triggering interrupt notification software to read.

Optionally, in this embodiment, the target video processing module is further configured to repair the fault point by using repair logic corresponding to the target detection point after determining that the target detection point is the fault point.

Optionally, in this embodiment, a hardware repair module is further disposed in the target video processing module; and the hardware repair module is used for taking over the target task stage in the process of executing the corresponding video processing task by the video processing unit.

Optionally, in this embodiment, the server management control chip is further configured to send a recovery instruction to the video processing module that is sent the exchange instruction after detecting the running state each time; and the video processing module is used for recovering to output data through the first output interface under the condition that the recovery instruction is received.

The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application should be included in the protection scope of the present application.

Claims

1. A video compression system of a server management control chip is characterized in that,

the video compression system comprises N video processing modules which are sequentially connected, N is an integer greater than 1, a switching unit and a video processing unit are deployed in each video processing module, an input interface of the switching unit is connected with a data input end of the video processing module, a first output interface of the switching unit is connected with the video processing unit, the video processing unit is connected with a next-stage video processing module, and the video processing unit in each video processing module is used for executing video processing tasks of each video processing module in the video compression system;

The switching unit further comprises a second output interface, wherein the second output interface is used for directly transmitting the input data transmitted by the data input end to the next-stage video processing module under the condition that the switching instruction of the server management control chip is received;

the server management control chip is used for sequentially sending the exchange instructions to the exchange units of the N video processing modules under the condition that the video compression function of the video compression system is abnormal, and detecting the running state of the video compression function after each time of sending the exchange instructions; and extracting target video processing modules which cause the video compression function to be abnormal from the N video processing modules according to the running state.

2. The system of claim 1, wherein the system further comprises a controller configured to control the controller,

the second output interface is connected with the next-stage video processing module in a first connection mode, the first connection mode is used for connecting the second output interface to the data output end of the video compression system, and the data output end of the video compression system is connected with a memory on the server management control chip;

The second output interface is used for transmitting the input data to the memory through a connection path formed by the first connection mode;

the next stage video processing module is used for extracting the input data from the memory.

3. The system of claim 2, wherein the system further comprises a controller configured to control the controller,

the last stage of the N video processing modules is an output control module, and the data output end of the output control module is connected with the memory;

the second output interface is connected with the data output end of the output control module;

the second output interface is used for transmitting the input data transmitted by the data input end to the memory through the data output end of the output control module.

4. The system of claim 2, wherein the system further comprises a controller configured to control the controller,

the first connection mode is applied to a first video processing module, of which the video processing tasks executed in the N video processing modules affect a video compression function.

5. The system of claim 4, wherein the system further comprises a controller configured to control the controller,

the N video processing modules comprise: the system comprises a capturing module, a scaling module, a color space conversion module, a block data generation module, an encryption module and an output control module;

The first video processing module includes: the capture module, the color space conversion module, the block data generation module, and the output control module.

6. The system of claim 1, wherein the system further comprises a controller configured to control the controller,

the second output interface is connected with the next-stage video processing module in a second connection mode, and the second connection mode is used for connecting the second output interface to the data input end of the next-stage video processing module;

the second output interface is configured to directly transmit the input data to the next stage video processing module through a connection path formed by the second connection mode.

7. The system of claim 6, wherein the system further comprises a controller configured to control the controller,

a multiplexer is also arranged in the video processing module and is connected between the video processing unit and the next-stage video processing module;

the second output interface is connected with the multiplexer;

the second output interface is used for directly transmitting the input data transmitted by the data input end to the next stage video processing module through the multiplexer.

8. The system of claim 6, wherein the system further comprises a controller configured to control the controller,

The second connection mode is applied to a second video processing module, wherein video processing tasks executed by the second video processing module do not affect a video compression function.

9. The system of claim 8, wherein the system further comprises a controller configured to control the controller,

the second video processing module includes: the scaling module and the encryption module.

10. The system of claim 1, wherein the system further comprises a controller configured to control the controller,

the server management control chip is further used for controlling the target video processing module to detect an abnormal reason causing the video compression function to be abnormal after extracting the target video processing module causing the video compression function to be abnormal from the N video processing modules according to the running state.

11. The system of claim 10, wherein the system further comprises a controller configured to control the controller,

the video processing unit of the target video processing module is configured with a plurality of detection points, and the detection points are task stages in the video processing task corresponding to the video processing unit;

The server management control chip is used for sending a detection instruction to the target video processing module, wherein the detection instruction is used for indicating the target video processing module to detect the fault of the video processing unit;

the target video processing module is used for responding to the detection instruction, taking each detection point in the plurality of detection points as a target detection point, and detecting a target running state of a target task stage when the video processing unit executes a corresponding video processing task to reach the target task stage of the target detection point; comparing the running state with a target expected state of the target task stage; and under the condition that the target running state is inconsistent with the target expected state, determining the target detection point as a fault point.

12. The system of claim 11, wherein the system further comprises a controller configured to control the controller,

the target video processing module comprises an expected analysis module and a hardware self-checking module, wherein the expected analysis module is configured with the plurality of detection points and expected states corresponding to each detection point;

the hardware self-checking module is used for extracting each detection point from the expected analysis module as a target detection point under the condition of receiving the detection instruction, and detecting the target running state of the target task stage; comparing the target running state with a target expected state of the target task stage; and under the condition that the target running state is inconsistent with the target expected state, determining the target detection point as a fault point.

13. The system of claim 12, wherein the system further comprises a controller configured to control the controller,

in the case where the target video processing module is a capturing module, the plurality of detection points include: an ending stage of the frame RGB data, an ending stage of the next line, and a digital stage of the RGB data input to the post-stage module per frame at the current resolution;

the expected state corresponding to the ending phase of the frame RGB data comprises an expected ending signal of the frame RGB data;

the expected state corresponding to the ending stage of the next row comprises the step of acquiring an expected ending signal of the next row;

the desired state corresponding to the number phase of the RGB data input to the rear module per frame at the current resolution includes a desired number of the RGB data input to the rear module per frame at the current resolution.

14. The system of claim 12, wherein the system further comprises a controller configured to control the controller,

in the case where the target video processing module is a scaling module, the plurality of detection points include: a filtering start stage, a filtering end stage, and a number stage of RGB data output to a post-stage module;

the expected states corresponding to the filtering start phase comprise filtering start states;

The expected states corresponding to the filtering ending stage comprise filtering ending states;

the desired state corresponding to the number of stages of RGB data output to the post-stage module includes a desired number of RGB data output to the post-stage module.

15. The system of claim 12, wherein the system further comprises a controller configured to control the controller,

in the case where the target video processing module is a color space conversion module, the plurality of detection points include: the effective calculated YUV data stage is a clipping stage for completing the resolution of the current resolution and the number of YUV data which is subjected to resolution clipping and is output to a rear module;

the expected states corresponding to the valid calculated YUV data phases include valid calculated YUV expected data;

the expected states corresponding to the clipping stage of the current resolution completion resolution include the expected resolution of clipping of the current resolution completion resolution;

the expected state corresponding to the number of YUV data which should be output to the post module after resolution clipping includes the expected number of YUV data which should be output to the post module after resolution clipping.

16. The system of claim 12, wherein the system further comprises a controller configured to control the controller,

In the case where the target video processing module is a block data generation module, the plurality of detection points include: a generation stage of Y data block data, a generation stage of U data block data, a generation stage of V data block data, and a data output stage of the block data generation module in a current compression mode;

the expected state corresponding to the generation stage of the Y data block data comprises the completion of the generation of the Y data block data;

the expected state corresponding to the generation stage of the U data block data comprises the completion of the generation of the U data block data;

the expected state corresponding to the generation stage of the V data block data comprises the completion of the generation of the V data block data;

the expected state corresponding to the data output stage of the block data generation module in the current compression mode comprises the expected data volume output by the block data generation module in the current compression mode.

17. The system of claim 12, wherein the system further comprises a controller configured to control the controller,

in the case where the target video processing module is an encryption module, the plurality of detection points include: a software configuration stage, completing an encryption result stage and combining the encrypted data;

the expected state corresponding to the software configuration stage comprises the step of acquiring a key required by the encryption of the software configuration;

The expected state corresponding to the encryption result stage is completed and comprises the expected length of the encrypted data;

the expected state corresponding to the data combination stage of encryption completion includes the combination of data of which encryption completion is completed.

18. The system of claim 12, wherein the system further comprises a controller configured to control the controller,

in the case where the target video processing module is an output control module, the plurality of detection points include: a frame header information inputting stage, a frame tail information inputting stage, a memory interaction stage, a frame header information writing stage, and a memory writing stage for writing the frame length of the current frame;

the expected state corresponding to the input frame header information stage comprises the detected input frame header information;

the expected state corresponding to the input end-of-frame information stage comprises the detected end-of-frame information;

the expected state corresponding to the memory interaction phase comprises that a channel of a bus interacted with the memory generates valid data and is a normal burst operation;

the expected state corresponding to the frame header information writing stage comprises the steps of writing the frame header information into a memory, obtaining an effective address cached in the memory and triggering interrupt notification software to read;

Writing the frame length of the current frame into the expected state corresponding to the memory stage comprises writing the frame length of the current frame into the memory and obtaining a valid address cached in the memory and triggering interrupt notification software to read.

19. The system of claim 11, wherein the system further comprises a controller configured to control the controller,

and the target video processing module is also used for repairing the fault point by adopting repair logic corresponding to the target detection point after determining that the target detection point is the fault point.

20. The system of claim 19, wherein the system further comprises a controller configured to control the controller,

a hardware repair module is also deployed in the target video processing module;

and the hardware repair module is used for taking over the target task stage in the process of executing the corresponding video processing task by the video processing unit.

21. The system of claim 1, wherein the system further comprises a controller configured to control the controller,

the server management control chip is also used for sending a recovery instruction to the video processing module which is sent with the exchange instruction after detecting the running state each time;

and the video processing module is used for recovering to output data through the first output interface under the condition that the recovery instruction is received.

22. A server management control chip is characterized in that,

comprising the following steps: a video compression system and a processor, wherein,

the video compression system comprises N video processing modules which are sequentially connected, N is an integer greater than 1, a switching unit and a video processing unit are deployed in each video processing module, an input interface of the switching unit is connected with a data input end of the video processing module, a first output interface of the switching unit is connected with the video processing unit, the video processing unit is connected with a next-stage video processing module, and the video processing unit in each video processing module is used for executing video processing tasks of each video processing module in the video compression system; the switching unit further comprises a second output interface, wherein the second output interface is used for directly transmitting the input data transmitted by the data input end to the next-stage video processing module under the condition that the switching instruction of the server management control chip is received;

the processor is used for sequentially sending the exchange instructions to the exchange units of the N video processing modules under the condition that the video compression function of the video compression system is abnormal, and detecting the running state of the video compression function after each time of sending the exchange instructions; and extracting target video processing modules which cause the video compression function to be abnormal from the N video processing modules according to the running state.