CN117319518A - High performance FC protocol processing engine - Google Patents

Abstract

The invention discloses a high-performance FC protocol processing engine, which comprises: the primitive control module analyzes the received FC primitives, initializes the FC link based on primitive sequences and performs FC link flow control management based on flow control primitives; the sending control module is used for selecting to send the FC primitive according to the primitive sending enabling signal or reading the AXIS bus data and sending the FC frame; the receiving control module judges the FC frames according to the frame delimiters, completes error detection and data alignment processing of each FC frame and outputs the FC frames through an AXIS bus; and the transmission word encoding and decoding module sequentially performs 64b/66b encoding, scrambling and 256b/257b encoding on all sent FC transmission words, and sequentially performs 256b/257b decoding, descrambling and 64b/66b decoding on received FC transmission words. The high-performance FC protocol processing engine provided by the invention has the functions of 64b/66b encoding and decoding and 256b/257b encoding and decoding, and has an expansion space supporting a future higher-rate FC standard.

Description

High performance FC protocol processing engine

Technical Field

The invention belongs to the technical field of networks, and particularly relates to a high-performance FC protocol processing engine.

Background

The Fiber Channel (FC) protocol is mainly applied to storage area networks and avionic environments, and has the advantages of high bandwidth, low delay, long transmission distance, high reliability, strong expansibility, support of various upper-layer protocols and the like. The FC protocol adopts a five-layer network model, and is sequentially provided with a protocol mapping layer (FC-4), a public service layer (FC-3), a frame and signaling protocol layer (FC-2), a transmission protocol layer (FC-1) and a physical interface layer (FC-0) from top to bottom. The FC protocol processing engine realizes partial functions of the FC-2 layer and the FC-1 layer, is responsible for sending and receiving FC primitives and frames and encoding and decoding FC transmission words, and is an indispensable module of all FC devices.

With the continuous development of technology, the fibre channel industry association (Fibre Channel Industry Association, abbreviated as FCIA) sequentially pushes out FC standards for 1G, 2G, 4G, 8G, 16G, 32G/128G, and 64G/256G rates. However, most of the FC protocols are still under research, and the few commercial FC product rates are mainly 4G and 8G.

Disclosure of Invention

The invention provides a high-performance FC protocol processing engine which solves the technical problems, and specifically adopts the following technical scheme:

a high performance FC protocol processing engine comprising: primitive control module, send control module, receive control module and transmit word coding and decoding module;

the primitive control module is used for analyzing the received FC primitives, initializing the FC links based on primitive sequences and performing FC link flow control management based on flow control primitives;

the sending control module is used for selecting to send the FC primitive according to the primitive sending enabling signal or reading AXIS bus data and sending the FC frame;

the receiving control module is used for judging FC frames according to frame delimiters, completing error detection and data alignment processing of each FC frame and outputting the FC frames through an AXIS bus;

the transmission word encoding and decoding module is used for sequentially performing 64b/66b encoding, scrambling and 256b/257b encoding on all sent FC transmission words, and sequentially performing 256b/257b decoding, descrambling and 64b/66b decoding on all received FC transmission words.

Further, the primitive control module includes: the word effective judging and primitive detecting sub-module, the port state machine sub-module and the cache flow control sub-module;

the word validity judging and primitive detecting submodule is used for judging the validity of FC transmission words and detecting frame delimiters, frame data, primitives and primitive sequences; the port state machine sub-module is used for carrying out FC port state conversion according to the received primitive sequences, and instructs the sending control module to send the corresponding primitive sequences under different states so as to complete the link initialization between adjacent FC ports;

and the buffer-to-buffer flow control sub-module is used for managing the current available credit according to the received flow control primitive and the sent FC frame, and indicating the sending control module to send the flow control primitive according to the received FC frame.

Further, the sending control module sends a primitive sequence according to the instruction of the port state machine sub-module, sends a flow control primitive according to the instruction cached to the cache flow control sub-module, and sends an FC frame under the conditions that an FC link is effective, the available credit is not zero and data exists on an AXIS bus.

Further, the transmission priority of the sending control module is primitive sequence > least padding word > flow control primitive > FC frame > idle padding word.

Further, the transmission control module has a cyclic redundancy check code generating function, calculates a cyclic redundancy check code from a start of frame delimiter to a last 4-byte payload in FC frame transmission, and inserts the cyclic redundancy check code before an end of frame delimiter;

the sending control module is provided with an exception handling mechanism, and when FC frames are transmitted, a frame abnormal end delimiter is inserted immediately once the FC link fails or the AXIS bus data is interrupted.

Further, the receiving control module judges the FC frame according to the frame delimiter, and sequentially performs frame end delimiter loss detection, frame start delimiter alignment processing, ultra-long/ultra-short frame detection, cyclic redundancy check code error detection and FC link failure detection, outputs the FC frame through the AXIS bus, and uses an AXIS_USER bit to identify different types of errors.

Further, the frame end delimiter loss detection analyzes abnormal conditions such as 'frame data immediately following FC control word/filler word (except for frame end delimiter)', inserts the frame end delimiter immediately after the abnormal conditions occur, and uses AXIS_USER 1 st bit identification;

the extra-long/ultra-short frame detection analyzes the abnormal condition that the total frame length is more than 2148 bytes or less than 36 bytes, the extra-long frame uses AXIS_USER 3 rd bit identification, and the ultra-short frame uses AXIS_USER 2 nd bit identification;

the error detection of the cyclic redundancy check code analyzes the abnormal condition that the cyclic redundancy check code check result is not matched with the theoretical value, and an AXIS_USER 0 th bit mark is used;

and the FC link failure detection analyzes the abnormal condition of 'link disconnection during FC frame transmission', inserts a frame abnormal end delimiter immediately after the abnormal condition occurs, and uses the 4 th bit identification of AXIS_USER.

Further, the frame start delimiter alignment process aligns all frame start delimiters to the low 32 bits of the 512 bit data bus, and the following data moves integrally with the frame start delimiters;

the alignment processing of the start of frame delimiter allocates a FIFO to each FC transmission word on a 512-bit data bus, and the 16 FIFOs are used for caching the FC transmission word and related type identifiers;

the frame start delimiter alignment process is provided with a cyclic pointer ROT_POINT for indicating which FIFO output is moved to the lower 32 bits of the 512 bit data bus;

the start of frame delimiter alignment process uses a state machine to control the next position of the rot_point, the read enable signal of the FIFO, and the valid signal of the output data.

Further, the transmission word encoding and decoding module includes: a 64b/66b coding sub-module, a 64b/66b decoding sub-module, a scrambling sub-module, a descrambling sub-module, a 256b/257b coding sub-module, and a 256b/257b decoding sub-module;

the 64b/66b coding submodule is used for dividing two FC transmission words into a group, adding a two-bit synchronous head newly, discarding K codes for FC control words/filling words, adding a type field, a control code and an ordered code newly, and carrying out 64b/66b coding based on the synchronous head, the type field, the control code, the ordered code and the reserved D code;

the 64b/66b decoding submodule is used for restoring the FC transmission word based on the synchronous head, the type field, the control code and the ordered code to finish 64b/66b decoding;

the scrambling submodule is used for carrying out exclusive or operation on corresponding bits of the input and linear feedback shift register to obtain a scrambling result;

the descrambling submodule is used for carrying out the same exclusive-or operation again according to the same linear feedback shift register to obtain a descrambling result;

the 256b/257b coding submodule is used for dividing four scrambled 64b/66b codes into a group, compressing an eight-bit synchronous head into one bit, compressing the type field of the first 64b/66b code containing FC control words/filling words, and adding four control word indication bits to complete 256b/257b coding;

the 256b/257b decoding submodule is used for finishing 256b/257b decoding based on the synchronous head before one-bit synchronous head and four-bit control word indicating bit reduction compression and the type field.

Further, the scrambling submodule and the descrambling submodule are used for obtaining a polynomial G (x) =x ⁵⁸ +x ³⁹ +1 generates a linear feedback shift register.

The invention has the advantages that the provided high-performance FC protocol processing engine has the functions of 64b/66b encoding and decoding and 256b/257b encoding and decoding, reduces the system power consumption and has an expansion space supporting future FC standards with higher speed.

The invention has the advantages that the provided high-performance FC protocol processing engine supports the 32G FC standard, and can transmit a maximum FC frame by adopting a 512-bit data bus for 33 clock cycles, thereby realizing full bandwidth transmission of the 32G FC under a low-frequency clock of 55 MHz.

The invention has the advantages that the provided high-performance FC protocol processing engine can detect and report various types of errors, can select continuous transmission or direct discarding of error frames, has error recovery capability no matter transmission word abnormality, frame abnormality or link abnormality, and has perfect fault tolerance design.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive faculty for a person skilled in the art.

FIG. 1 is a schematic diagram of the overall architecture of a high performance FC protocol processing engine of the present invention;

FIG. 2 is a schematic diagram of a primitive control module of the high performance FC protocol processing engine of the present invention;

FIG. 3 is a port state transition representation intent of the high performance FC protocol processing engine of the present invention;

FIG. 4 is a schematic diagram of a transmission control module of the high-performance FC protocol processing engine according to the present invention;

FIG. 5 is a schematic diagram of a transport word select and frame read state machine of a high performance FC protocol processing engine of the present invention;

FIG. 6 is a schematic diagram of a receiving control module of the high performance FC protocol processing engine according to the present invention;

FIG. 7 is a schematic diagram of a frame alignment processing state machine of the high performance FC protocol processing engine of the present invention;

FIG. 8 is a diagram of "frame data+frame data" encoded by 64b/66b of the high performance FC protocol processing engine of the present invention;

FIG. 9 is a schematic diagram of a 64b/66b encoded "FC filler + FC filler" of the high performance FC protocol processing engine of the present invention;

FIG. 10 is a schematic diagram of a 64b/66b encoded "FC control word+FC control word" of a high performance FC protocol processing engine of the present invention;

FIG. 11 is a schematic diagram of the "FC fill word+FC control word" and "FC control word+FC fill word" encoded by 64b/66b of the high performance FC protocol processing engine of the present invention;

FIG. 12 is a schematic diagram of "SOF+frame data" and "frame data+EOF" encoded by 64b/66b of a high performance FC protocol processing engine according to the present invention;

FIG. 13 is a 256b/257b code schematic of a high performance FC protocol processing engine of the invention.

Detailed Description

Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and intended for the purpose of explaining the present application and are not to be construed as limiting the present application.

The "FC transport word" described in this application refers to a basic unit of data transmission of a high performance FC protocol processing engine, and has a length of 4 bytes.

The "FC primitive" described in the present application refers to some FC transport words having a specific meaning specified by the FC protocol, consisting of 1K code and 3D codes, including NOS, OLS, LR, LRR, idle, R _rdy, etc.

The term "primitive sequence" as used herein refers to a set of at least three consecutive identical NOS/OLS/LR/LRR/Idle primitives.

The "flow control primitive" described in this application refers to an r_rdy primitive.

The "FC frame" described in the present application refers to one set consisting of a start of frame delimiter (SOF, 4 bytes), a header (24 bytes), a payload (2048 bytes data padding at maximum+64 bytes extension header at maximum), a cyclic redundancy check code (CRC, 4 bytes), and an end of frame delimiter (EOF, 4 bytes).

"frame data" as described in this application refers to a set of parts of FC frames excluding SOF and EOF.

The "FC control word" described in the present application refers to a set consisting of SOF, EOF, NOS, OLS, LR, LRR, R _rdy primitives.

The "FC filler word" described in this application refers to the Idle primitive.

Note that FC primitives, primitive sequences, flow control primitives, FC control words, FC fill words include, but are not limited to, the several listed above.

Fig. 1 is a schematic diagram of the overall structure of a high-performance FC protocol processing engine according to the present application, based on the 32G FC standard and a 512-bit data bus. The high performance FC protocol processing engine includes: primitive control module, send control module, receive control module and transmission word coding and decoding module. Specifically, the primitive control module analyzes the received FC primitive, initializes the FC link based on the primitive sequence, and performs FC link flow control management based on the flow control primitive. The sending control module selects to send the FC primitive or read the AXIS bus data according to the primitive sending enabling signal and sends the FC frame. And the receiving control module judges the FC frames according to the frame delimiters, completes error detection and data alignment processing of each FC frame and outputs the FC frames through an AXIS bus. The transmission word encoding and decoding module sequentially performs 64b/66b encoding, scrambling and 256b/257b encoding on all sent FC transmission words, and sequentially performs 256b/257b decoding, descrambling and 64b/66b decoding on all received FC transmission words.

As shown in fig. 2, as a preferred embodiment, the primitive control module includes: the word effective judging and primitive detecting sub-module, the port state machine sub-module and the buffer flow control sub-module. The word validity judging and primitive detecting submodule is used for judging the validity of FC transmission words and detecting frame delimiters, frame data, primitives and primitive sequences. The port state machine sub-module is used for carrying out FC port state conversion according to the received primitive sequence, and instructs the sending control module to send the corresponding primitive sequence under different states so as to complete the link initialization between adjacent FC ports. The buffer-to-buffer flow control sub-module is used for managing the current available credit according to the received flow control primitive and the sent FC frame, and sending the flow control primitive according to the received FC frame indication sending control module.

The word valid judgment and primitive detection submodule instantiates 16 FC transmission word detectors to detect data on the 512-bit bus in parallel. For each FC transfer word, byte 3 is determined to be valid when it is a K code and the D code combination of bytes 0-2 is correct, or byte 3 is not a K code. If a certain FC transport word is valid and the D-code combination matches SOF/EOF, then it is determined to be a frame delimiter. If a certain FC transport word is valid and byte 3 is not K code, it is determined as frame data. If a certain FC transport word is valid and the D-code combination matches NOS/OLS/LR/LRR/Idle, then it is determined as primitive. If three consecutive FC transport words are the same primitive, the primitive sequence is determined.

The port state machine sub-module considers that each FC port may be in four states, valid, recovery, failed and offline. The recovery state may be further divided into three sub-states of recovery 1, recovery 2, and recovery 3, the failure state may be further divided into two sub-states of failure 1 and failure 2, and the offline state may be further divided into three sub-states of offline 1, offline 2, and offline 3. The port state machine jumps between different states according to the received primitive sequence in combination with the current state, and instructs the transmission control module to transmit the corresponding primitive sequence, see fig. 3 in particular. After the FC port enters the valid state, the initialization of the link and the credit is completed, and a link valid indication is given.

The buffer-to-buffer flow control submodule controls the number of FC frames on a unidirectional link between adjacent FC ports according to the amount of credit, for example, the initial value of the credit is 4, which indicates that at most 4 FC frames are allowed to be transmitted on the FC link. And each time the sending control module sends an FC frame, buffering the FC frame to the buffer flow control sub-module to reduce the current available credit by 1. And the word effective judgment and primitive detection submodule caches the current available credit amount by 1 when detecting one flow control primitive. And each time the receiving control module receives an FC frame, the buffer flow control submodule gives a flow control primitive sending enabling signal, and the sending control module sends a flow control primitive. When the available credit is reduced to zero, the buffer flow control submodule gives an indication of no credit, and the sending control module pauses sending the FC frame.

As a preferred embodiment, the sending control module sends the primitive sequence according to the instruction of the port state machine submodule, sends the flow control primitive according to the instruction buffered in the buffer flow control submodule, and sends the FC frame when the FC link is valid, the available credit is not zero, and there is data on the AXIS bus.

As shown in fig. 4, as a preferred embodiment, the transmission control module uses a transport word selection and frame reading state machine to interact with the primitive control module to select to transmit NOS/OLS/LR/LRR/Idle when the primitive sequence is enabled, select to transmit r_rdy when the flow control primitive signal is enabled, and read the FC frame via the axis_ctrl signal when the FC link is valid and the available credit is not zero. The FC frame in AXIS format passes through CRC generation module, calculates cyclic redundancy check code from frame start delimiter to last 4 byte load, and inserts cyclic redundancy check code before frame end delimiter, i.e. the transmission control module has cyclic redundancy check code generation function.

As shown in fig. 5, the transport word select and frame read state machine consists of four states s_fline, s_active, s_wait_sof, and s_tra_frm. In the S_OFFLINE state, the enabling signal is sent according to the primitive sequence to select and transmit NOS/OLS/LR/LRR/Idle, and the state of S_ACTIVE is entered after the initialization of the FC link is completed. In the S_ACTIVE state, if the FC link fails, returning to the S_OFFLINE state, if the FC link is valid, selecting to transmit R_RDY according to the flow control primitive sending enabling signal, and entering the S_WAIT_SOF state when R_RDY is not transmitted and the available credit is not zero. In the S_WAIT_SOF state, if the axis_valid signal is valid, it indicates that there is an FC frame waiting to be transmitted, entering the S_TRA_FRM state, otherwise returning to the S_ACTIVE state. In the S_TRA_FRM state, if the FC link fails, whether EOFa is inserted is selected according to whether the FC frame being transmitted is available or not, and the FC frame is read by pulling up an axis_ready signal, if the FC link is available, and the FC frame is read by using a tra_sof identification frame start delimiter, a tra_data identification whole FC frame, a tra_crc identification cyclic redundancy check code, a tra_ eof identification frame end delimiter, if the axis_last signal is available, the transmission of one FC frame is completed, and the FC frame is returned to the S_ACTIVE state.

The transmission word selection and frame reading state machine design can embody the transmission priority of the sending control module, the primitive sequence has the highest priority, the least filling word has the second priority, the flow control primitive has the third priority, the FC frame has the fourth priority, and the idle filling word has the lowest priority. Note that the default transfer Idle, when no transfer word selection is made, is specifically reflected in the least filled words and the free filled words.

The sending control module of the application also has an exception handling mechanism, and when FC frame transmission occurs, once the FC link fails or the AXIS bus data is interrupted, a frame abnormal end delimiter is inserted immediately.

As shown in fig. 6, as a preferred embodiment, the reception control module judges the FC frame according to the frame delimiter, sequentially performs end-of-frame delimiter loss detection, start-of-frame delimiter alignment processing, ultralong/ultrashort frame detection, cyclic redundancy check code error detection, and FC link failure detection, monitors the FC link state using one frame reception state machine, filters the FC primitive, converts the FC frame into the data of the AXIS format, outputs the FC frame through the AXIS bus, and reports all error types through the axis_ctrl signal, and uses the axis_user bit to identify different types of errors.

The start of frame delimiter alignment process aligns all start of frame delimiters to the low 32 bits of the 512 bit data bus, with the following data moving integrally with the start of frame delimiters. Specifically, a FIFO is allocated to each FC transmission word on the 512-bit data bus, 16 FIFOs in total are used for buffering the FC transmission word and the related type identifier, and a round-robin pointer rot_point is provided for indicating which FIFO output is moved to the lower 32 bits of the 512-bit data bus, and a frame alignment processing state machine is used for controlling the next position of the rot_point, the read enable signal of the FIFO, and the valid signal of the output data. As shown in fig. 7, the frame alignment processing state machine is composed of three states of s_idle, s_align, and s_trans. In the S_IDLE state, it is detected whether there is SOF at the output of the current 16 FIFOs, and if the lower 32 bits are SOF, the S_TRANS state is entered, if the SOF is not located at the lower 32 bits, the S_ALIGN state is entered, and if there is no SOF, all of the outputs of the 16 FIFOs are pushed out for discarding when they are all valid. In the s_align state, the FC transport word before discarding the SOF is pushed out, the rot_point is controlled to POINT to the SOF in the next state, and the s_trans state is entered. In the S_TRANS state, detecting whether EOF exists in the output of the current 16 FIFOs, if EOF does not exist, enabling all output data to be valid when the output of the 16 FIFOs is valid, and if EOF exists, enabling the EOF and the output data before the EOF to be valid, controlling ROT_POINT to POINT to FC transmission words after EOF in the next state, and returning to the S_IDLE state.

In the aspect of fault-tolerant design, the receiving control module can realize error detection and reporting as follows, and can select to continue transmission or directly discard for the error frame.

1. The frame end delimiter loss detection analyzes the abnormal condition of 'frame data immediately following FC control word/filling word (except frame end delimiter)', inserts frame end delimiter immediately after the abnormal condition occurs, and uses AXIS_USER 1 st bit identification.

2. The extra-long/ultra-short frame detection analyzes the abnormal condition that the total frame length is more than 2148 bytes or less than 36 bytes, the extra-long frame is marked by the 3 rd bit of AXIS_USER, and the ultra-short frame is marked by the 2 nd bit of AXIS_USER.

3. And (3) detecting and analyzing the abnormal condition that the cyclic redundancy check result is not matched with the theoretical value by using the 0 th bit mark of the AXIS_USER.

4. The FC link failure detection resolves the abnormal situation of 'link disconnection during FC frame transmission', inserts a frame abnormal end delimiter immediately after the abnormal situation occurs, and uses the 4 th bit mark of AXIS_USER.

As a preferred embodiment, the transport word codec module comprises: 64b/66b coding submodule, 64b/66b decoding submodule, scrambling submodule, descrambling submodule, 256b/257b coding submodule and 256b/257b decoding submodule.

The 64b/66b coding submodule is used for dividing two FC transmission words into a group, adding a two-bit synchronous head, discarding K codes for FC control words/filling words, adding a type field, a control code and an ordered code, and carrying out 64b/66b coding based on the synchronous head, the type field, the control code, the ordered code and the reserved D code. As shown in fig. 8-12, the 64b/66b encoding results for different FC transport word combinations are as follows.

1. Both FC transport words are frame data as shown in fig. 8. The two-bit synchronous header is 2' b10, which indicates that two FC transmission words are frame data, and the two frame data are respectively subjected to size end conversion to obtain a coding result.

2. Both FC transport words are FC fill words, as shown in fig. 9. The two-bit sync header is 2' b01, which indicates that two FC transport words are not both frame data, four control codes are used to indicate one FC fill word, the default control code for Idle is 00h, and the type field is set to 1Eh, which indicates that both FC transport words are FC fill words.

3. Both FC transport words are FC control words, as shown in fig. 10. And discarding the K codes for each FC control word to reserve the D codes, adding an ordered code, setting to 0h to indicate that the FC control word belongs to a primitive sequence or a frame delimiter, setting to Fh to indicate that the FC control word belongs to a flow control primitive, and setting a type domain according to the type of the FC control word.

4. The two FC transport words are FC fill word + FC control word or FC control word + FC fill word, as shown in fig. 11a, 11 b. And using four control codes to represent FC filling words, discarding K codes for FC control words, reserving D codes, adding an ordered code, and setting a type field according to the type of the FC control words.

5. The two FC transport words are sof+frame data or frame data+eof, as shown in fig. 12a, 12 b. The frame data is subjected to size end conversion, K codes are abandoned for SOF/EOF, D codes are reserved for the SOF/EOF, an ordered code is added, a type field is set to 78h, two FC transmission words are SOF+frame data, the type field is set to FFh, and two FC transmission words are frame data+EOF.

The 64b/66b decoding submodule restores the FC transport word based on the synchronous head, the type field, the control code and the ordered code, and completes 64b/66b decoding. If the decoding is wrong, the decoding is not transmitted to the subsequent modules.

The scrambling submodule is based on a polynomial G (x) =x ⁵⁸ +x ³⁹ +1 generates a linear feedback shift register, exclusive-ors the input and the corresponding bits of the linear feedback shift register to obtain an output, and shifts the output into the linear feedback shift register for scrambling for the next clock cycle.

The descrambling submodule adopts the same polynomial and the initial value of the register to carry out the same exclusive or operation again, and the correct descrambling result can be obtained as long as adjacent data have no errors.

The 256b/257b coding sub-module is used for dividing four scrambled 64b/66b codes into a group, compressing eight-bit synchronous heads into one bit, compressing the type field of the first 64b/66b code containing FC control words/filling words, and adding four new control word indication bits to complete 256b/257b coding. As shown in FIG. 13, the 256b/257b code results for the different 64b/66b code combinations are as follows. For convenience of description, the 64b/66b code that does not contain FC control words/padding will be referred to as data words, and the 64b/66b code that contains FC control words/padding will be referred to as control words.

1. The four 64b/66b codes each do not contain a control word, as shown in fig. 13 a. Setting bit 0 to 0 indicates that the four 64b/66b codes are all data words, and the contents of the data words are directly transmitted.

2. The four 64b/66b codes contain one control word as shown in figure 13 b. Setting bit [0] to 1, indicating that the four 64b/66b codes contain at least one control word, bit [4:1] is a control word indication bit, setting bit [ i ] to 1 indicates that the ith 64b/66b code is a data word, setting 0 indicates that the ith 64b/66b code is a control word, and only the low 4 bits are reserved in the control word type field.

3. Four 64b/66b codes contain multiple control words as shown in fig. 13 c. For the first control word, the type field is reserved for only the lower 4 bits, and the remaining control word type fields are all reserved.

The 256b/257b decoding submodule is used for completing 256b/257b decoding based on the synchronous head before one-bit synchronous head and four-bit control word indicating bit reduction compression and the type field. If the decoding is erroneous, the 64b/66b encoded two-bit sync header is set to 2' b11.

The foregoing has shown and described the basic principles, principal features and advantages of the invention. It will be appreciated by persons skilled in the art that the above embodiments are not intended to limit the invention in any way, and that all technical solutions obtained by means of equivalent substitutions or equivalent transformations fall within the scope of the invention.

Claims (10)

1. A high performance FC protocol processing engine comprising: primitive control module, send control module, receive control module and transmit word coding and decoding module;

the primitive control module is used for analyzing the received FC primitives, initializing the FC links based on primitive sequences and performing FC link flow control management based on flow control primitives;

the sending control module is used for selecting to send the FC primitive according to the primitive sending enabling signal or reading AXIS bus data and sending the FC frame;

the receiving control module is used for judging FC frames according to frame delimiters, completing error detection and data alignment processing of each FC frame and outputting the FC frames through an AXIS bus;

the transmission word encoding and decoding module is used for sequentially performing 64b/66b encoding, scrambling and 256b/257b encoding on all sent FC transmission words, and sequentially performing 256b/257b decoding, descrambling and 64b/66b decoding on all received FC transmission words.

2. The high performance FC protocol processing engine of claim 1 wherein the high performance FC protocol comprises a high performance FC protocol,

the primitive control module comprises: the word effective judging and primitive detecting sub-module, the port state machine sub-module and the cache flow control sub-module;

the word validity judging and primitive detecting submodule is used for judging the validity of FC transmission words and detecting frame delimiters, frame data, primitives and primitive sequences;

the port state machine sub-module is used for carrying out FC port state conversion according to the received primitive sequences, and instructs the sending control module to send the corresponding primitive sequences under different states so as to complete the link initialization between adjacent FC ports;

and the buffer-to-buffer flow control sub-module is used for managing the current available credit according to the received flow control primitive and the sent FC frame, and indicating the sending control module to send the flow control primitive according to the received FC frame.

3. The high performance FC protocol processing engine of claim 2 wherein the high performance FC protocol comprises a high performance FC protocol,

and the sending control module sends a primitive sequence according to the indication of the port state machine submodule, sends a flow control primitive according to the indication of the buffer flow control submodule, and sends an FC frame under the conditions that an FC link is effective, the available credit is not zero and data exists on an AXIS bus.

4. The transmission control module according to claim 3, wherein,

and the transmission priority of the sending control module is primitive sequence > least filling word > flow control primitive > FC frame > idle filling word.

5. The transmission control module according to claim 3, wherein,

the sending control module has a cyclic redundancy check code generating function, calculates a cyclic redundancy check code from a frame start delimiter to a last 4 byte load when FC frames are transmitted, and inserts the cyclic redundancy check code before an end of frame delimiter;

the sending control module is provided with an exception handling mechanism, and when FC frames are transmitted, a frame abnormal end delimiter is inserted immediately once the FC link fails or the AXIS bus data is interrupted.

6. The high performance FC protocol processing engine of claim 1 wherein the high performance FC protocol comprises a high performance FC protocol,

the receiving control module judges the FC frame according to the frame delimiter, and sequentially carries out frame end delimiter loss detection, frame start delimiter alignment treatment, ultra-long/ultra-short frame detection, cyclic redundancy check code error detection and FC link failure detection, outputs the FC frame through the AXIS bus, and uses AXIS_USER bits to identify different types of errors.

7. The receiving control module of claim 6, wherein,

the frame end delimiter loss detection analyzes abnormal conditions such as 'frame data immediately following FC control word/filling word (except frame end delimiter)', inserts frame end delimiter immediately after the abnormal conditions occur, and uses AXIS_USER 1 st bit identification;

the extra-long/ultra-short frame detection analyzes the abnormal condition that the total frame length is more than 2148 bytes or less than 36 bytes, the extra-long frame uses AXIS_USER 3 rd bit identification, and the ultra-short frame uses AXIS_USER 2 nd bit identification;

the error detection of the cyclic redundancy check code analyzes the abnormal condition that the cyclic redundancy check code check result is not matched with the theoretical value, and an AXIS_USER 0 th bit mark is used;

and the FC link failure detection analyzes the abnormal condition of 'link disconnection during FC frame transmission', inserts a frame abnormal end delimiter immediately after the abnormal condition occurs, and uses the 4 th bit identification of AXIS_USER.

8. The receiving control module of claim 6, wherein,

the frame start delimiter alignment process aligns all frame start delimiters to the low 32 bits of the 512 bit data bus, and the following data moves integrally with the frame start delimiters;

the alignment processing of the start of frame delimiter allocates a FIFO to each FC transmission word on a 512-bit data bus, and the 16 FIFOs are used for caching the FC transmission word and related type identifiers;

the frame start delimiter alignment process is provided with a cyclic pointer ROT_POINT for indicating which FIFO output is moved to the lower 32 bits of the 512 bit data bus;

the start of frame delimiter alignment process uses a state machine to control the next position of the rot_point, the read enable signal of the FIFO, and the valid signal of the output data.

9. The high performance FC protocol processing engine of claim 1 wherein the high performance FC protocol comprises a high performance FC protocol,

the transmission word encoding and decoding module comprises: a 64b/66b coding sub-module, a 64b/66b decoding sub-module, a scrambling sub-module, a descrambling sub-module, a 256b/257b coding sub-module, and a 256b/257b decoding sub-module;

the 64b/66b coding submodule is used for dividing two FC transmission words into a group, adding a two-bit synchronous head newly, discarding K codes for FC control words/filling words, adding a type field, a control code and an ordered code newly, and carrying out 64b/66b coding based on the synchronous head, the type field, the control code, the ordered code and the reserved D code;

the 64b/66b decoding submodule is used for restoring the FC transmission word based on the synchronous head, the type field, the control code and the ordered code to finish 64b/66b decoding;

the scrambling submodule is used for carrying out exclusive or operation on corresponding bits of the input and linear feedback shift register to obtain a scrambling result;

the descrambling submodule is used for carrying out the same exclusive-or operation again according to the same linear feedback shift register to obtain a descrambling result;

the 256b/257b coding submodule is used for dividing four scrambled 64b/66b codes into a group, compressing an eight-bit synchronous head into one bit, compressing the type field of the first 64b/66b code containing FC control words/filling words, and adding four control word indication bits to complete 256b/257b coding;

the 256b/257b decoding submodule is used for finishing 256b/257b decoding based on the synchronous head before one-bit synchronous head and four-bit control word indicating bit reduction compression and the type field.

10. The high performance FC protocol processing engine of claim 9 wherein the high performance FC protocol comprises a high performance FC protocol,

the scrambling submodule and the descrambling submodule are used for obtaining the code according to a polynomial G (x) =x ⁵⁸ +x ³⁹ +1 generates a linear feedback shift register.