CN117319328A

CN117319328A - Message processing system based on RISCV heterogeneous multi-core SOC

Info

Publication number: CN117319328A
Application number: CN202311416353.5A
Authority: CN
Inventors: 张啸宇; 刘如意; 陆湘
Original assignee: Shenzhen Forward Industrial Co Ltd
Current assignee: Shenzhen Forward Industrial Co Ltd
Priority date: 2023-10-27
Filing date: 2023-10-27
Publication date: 2023-12-29

Abstract

The invention discloses a message processing system based on RISCV heterogeneous multi-core SOC, which comprises: the message processing system based on the RISCV heterogeneous multi-core SOC comprises a control core cluster, a plurality of data core clusters and a switching chip, wherein each data core cluster is provided with a shared memory, and the message processing system based on the RISCV heterogeneous multi-core SOC is provided with a routing mode, and under the routing mode: the control core cluster is used for reading the forwarding packet and writing the table item configuration into the shared memory; the switching chip is used for receiving the packet, uploading the packet to each shared memory, and repackaging the forwarding packet of each data core cluster and then carrying out packet sending processing; and each data core cluster is used for reading the table item configuration, and processing and forwarding the packet according to the table item configuration.

Description

Message processing system based on RISCV heterogeneous multi-core SOC

Technical Field

The invention relates to the technical field of message processing, in particular to a message processing system based on a RISCV heterogeneous multi-core SOC.

Background

System on chip, a system on chip, also known as a system on chip, abbreviated as SOC, is an integrated circuit with a dedicated target. Including the complete system and the entire contents of the embedded software. Typically custom made or specific purpose oriented standard products.

The asymmetricmulti processing, heterogeneous polynuclear, abbreviated AMP, is a design classification of the polynuclear architecture. The cores are not all the same architecture as for an isomorphic multi-core. Different kernels are designed for different specific needs, thereby improving the computational or real-time performance of the application. There is typically one primary core for controlling the overall system and other secondary cores, with a master-slave mode.

RISCV is a completely new, simple and open-free instruction set architecture. And the system is completely autonomous and controllable because of no limitation of various aspects such as X86, ARM and the like requiring authorization. The RISC-V instruction set is a reduced instruction set, consisting of a "basic instruction set" + "extended instruction set". The basic instruction set is mandatory and not extended.

Real time-Thread, a real-time operating system that is born in 2006 and is domestic, abbreviated RTThread, and RTT. The system is an embedded real-time operating system which is completely developed and maintained by domestic team, has complete independent intellectual property and realizes multi-task through multithreading.

Heterogeneous multi-cores in an SOC system are composed of master cores and slave cores. The main core is a control core, and a Linux system is operated as a control plane to manage and configure the exchange chip and most hardware; the slave core is a data core, and runs the RTT system as a data plane to perform message table lookup forwarding and statistics. Both the master core and the slave core have their own DDR memory, but due to hardware limitations, the master core can access the DDR memory of the slave core, while the slave core cannot access the DDR memory of the master core. Also because of the hardware design, the slave core is designed for message forwarding, i.e.: after the message is written into the memory of the slave core through the hardware packet receiving DMA, the packet receiving thread of the slave core processes the message, and then the interface is sent after the interface is found out.

In the existing message processing method, under the exchange mode forwarding, specific forwarding details, part of vendor private characteristics and part of advanced characteristics may be limited by the functional performance of the chip.

Disclosure of Invention

The invention aims to provide a message processing method based on a RISCV heterogeneous multi-core SoC, so that more flexible, private and advanced forwarding functions and performances can be obtained under the RISCV scene.

The technical scheme for solving the technical problems is as follows:

the invention provides a message processing system based on RISCV heterogeneous multi-core SOC, which comprises: the control core cluster, a plurality of data core clusters and a switching chip, wherein each data core cluster is provided with a shared memory,

the message processing system based on the RISCV heterogeneous multi-core SOC is provided with a routing mode, and the routing mode is as follows:

the control core cluster is used for processing the protocol message to generate a forwarding table entry and writing the table entry configuration into the shared memory;

the switching chip is used for receiving the packet, uploading the packet to each shared memory, and repackaging the forwarding packet of each data core cluster and then carrying out packet sending processing;

and each data core cluster is used for reading the table item configuration, processing the packet according to the table item configuration and transmitting the packet to a control core or transmitting the packet to a switching chip designated interface for forwarding according to the requirement.

Optionally, the control core cluster includes an entry management module, where the entry management module includes an NPAS program and a cls_rfc program, where the NPAS program is configured to issue an interface information table, an adjacency table, and a forwarding information table, the cls_rfc program is configured to issue an L4 rule matching entry, and the NPAS program and the cls_rfc program are further configured to: initializing the table entry memory of each data core cluster, reading the table entry memory of each data core cluster, and counting the information in the table entry memory to obtain statistical information.

Optionally, the shared memory includes a forwarding table entry part and a communication supporting part, where the forwarding table entry part is used to forward the interface information table, the adjacency table and the forwarding information table; the communication support section provides a ring queue of the shared memory between systems for supporting communication between systems.

Optionally, forwarding the packet according to the entry configuration includes:

carrying out message analysis on the packet to obtain a protocol message;

inquiring whether various forwarding table items in the table item configuration contain the protocol message, if so, reporting the forwarding table items containing the protocol message to the control core cluster; otherwise, forwarding the protocol message and the table item configuration to the switching chip.

Optionally, the message processing system based on the RISCV heterogeneous multi-core SOC further has a switching mode, where:

the control core cluster is used for issuing the chip configuration to the exchange chip;

the exchange chip is used for reading the chip configuration, receiving the packet, forwarding the packet according to the chip configuration, and repackaging the forwarded packet and then performing packet sending processing.

The invention also provides a message processing method of the message processing system based on the RISCV heterogeneous multi-core SOC, which comprises the following steps:

receiving a packet;

judging whether related instructions exist, if so, entering a routing mode and processing a message in the routing mode; otherwise, entering an exchange mode and processing the message in the exchange mode;

the related instruction is an instruction input by a user.

Optionally, the routing mode is:

uploading the packet to a shared memory of each data core cluster;

the control core cluster is controlled to write the table item configuration into the shared memory;

controlling each data core cluster to read the table item configuration and process and forward the packet according to the table item configuration;

and the control exchange chip repackages the forwarding packets of the data core clusters and then carries out packet sending processing.

Optionally, the switching mode is:

the control core cluster is controlled to issue the chip configuration to the exchange chip;

and the control core cluster reads the chip configuration, forwards the packet according to the chip configuration, and repackages the forwarded packet and then sends the packet.

The invention has the following beneficial effects:

the invention can solve the limit of the architecture core number performance of the traditional CPU, break the upper limit of forwarding performance, and further obtain more flexible, private and advanced forwarding functions and performances under the RISCV scene.

Drawings

FIG. 1 is a flow chart of a message processing system based on a RISCV heterogeneous multi-core SOC of the invention;

FIG. 2 is a schematic diagram of a message processing process in a routing mode;

fig. 3 is a schematic diagram of a message processing procedure in the switching mode.

Detailed Description

The principles and features of the present invention are described below with reference to the drawings, the examples are illustrated for the purpose of illustrating the invention and are not to be construed as limiting the scope of the invention.

The invention provides a message processing system based on RISCV heterogeneous multi-core SOC, referring to FIG. 1, the message processing system based on RISCV heterogeneous multi-core SOC comprises: the system comprises a control core cluster, a plurality of data core clusters and a switching chip, wherein each data core cluster is provided with a shared memory;

the shared memory comprises a forwarding table entry part and a communication support part, wherein the forwarding table entry part is used for forwarding an interface information table, an adjacent table and a forwarding information table; the communication support section provides a ring queue of the shared memory between systems for supporting communication between systems.

The message processing system based on the RISCV heterogeneous multi-core SOC provided by the invention has a routing mode, and the routing mode is as follows:

the control core cluster is used for reading the forwarding packet and writing the table item configuration into the shared memory. Here, reading the forwarding packet generates a forwarding table entry for processing the protocol packet.

In the invention, the control core cluster comprises an item management module, wherein the item management module comprises an NPAS program and a CLS_RFC program, the NPAS program is used for issuing an interface information table, an adjacent table and a forwarding information table, and the CLS_RFC program is used for issuing an L4 rule matching item. The two are generally implemented in different sizes, and the main difference is the processing of different entries. The NPAS program and cls_rfc program are also used to: initializing the table entry memory of each data core cluster (because the device has a plurality of sets of slave core memories, each execution is needed in this step), reading the table entry memory of each data core cluster, and counting the information in the table entry memory to obtain the statistical information.

Specifically, the NPAS procedure initializing the table entry memory of each data core cluster includes:

initializing the memory head of the table entry and distributing the address range of each table entry; initializing an item assignable memory pool; initializing interface information table, adjacent table, forwarding information table and marking table item memory initialization.

In addition to this, other modules such as initializing command lines, command message processing, log printing, etc. are available.

In the command line and command message processing, the following table entry is written into or modified by all slave core memories, and various global variables are ensured not to be influenced by multiple memory writing

The table reading item is directly read from Round Trip Time (RTT) memory of a first data core cluster in all data core clusters, but the statistical information is obtained by summarizing from all RTT memory.

The initializing the table entry memory of each data core cluster by the CLS_RFC program comprises the following steps:

initializing a correlation table of the CLS; and (5) allocating the table entry memory needed by the part and marking the initialization completion of the table entry memory.

The switching chip is used for receiving the packet, uploading the packet to each shared memory, and repackaging the forwarding packet of each data core cluster and then carrying out packet sending processing; with particular reference to fig. 2.

And each data core cluster is used for reading the table item configuration, processing the packet according to the table item configuration and transmitting the packet to a control core or transmitting the packet to a switching chip designated interface for forwarding according to the requirement. Here, whether the message is a protocol message, a message with the destination MAC as the own message, and a message configured with an ACL are determined according to the need.

carrying out message analysis on the packet to obtain a protocol message;

Optionally, the RISCV heterogeneous multi-core SOC based packet processing system further has a switching mode, as shown in fig. 3, in which:

In the exchange mode, the working mode of the system is simpler, only the control core cluster is required to issue configuration to the exchange chip, the message processing flow is mainly on the exchange chip, and no much interaction exists between the control core cluster and the data core cluster. This is not much different from the processing manner of the normal network device, and thus the present invention will not be described in detail.

The mode of the shared memory communication between the control core cluster and the data core cluster is as follows:

the Linux in the control core cluster and the RTT in the data core cluster can communicate through a ring queue of the shared memory between the systems, and taking a common process of Linux as an example, a message is sent to the RTT by using the shared memory ring queue operation library:

1. first, the message to be sent is prepared and the message sending interface of the ring queue is invoked.

2. The sending interface firstly constructs a message header, calculates and stores the message length, and starts writing the message length into the shared memory from the in position of the shared memory.

3. The in position of the Linux side queue is modified after the memory barrier is used.

4. The Cache is refreshed.

And 5, the message receiving thread at the RTT side discovers the in position change and checks to find that the receivable message exists.

6. The message receiving thread receives the message.

7. The out position of the Linux side queue is modified after the memory barrier is used.

8. The Cache is refreshed.

The receiving thread of rtt calls the registered receiving processing function.

The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.

Claims

1. The message processing system based on the RISCV heterogeneous multi-core SOC is characterized by comprising the following components: the control core cluster, a plurality of data core clusters and a switching chip, wherein each data core cluster is provided with a shared memory,

the control core cluster is used for reading the forwarding packet and writing the table item configuration into the shared memory;

2. The RISCV heterogeneous multi-core SOC based packet processing system of claim 1, wherein the control core cluster includes an entry management module including an NPAS program for issuing interface information tables, adjacency tables, and forwarding information tables, and a cls_rfc program for issuing L4 rule matching entries, the NPAS program and cls_rfc program further for: initializing the table entry memory of each data core cluster, reading the table entry memory of each data core cluster, and counting the information in the table entry memory to obtain statistical information.

3. The message processing system based on the RISCV heterogeneous multi-core SOC of claim 1, wherein the shared memory includes a forwarding table entry portion and a communication support portion, the forwarding table entry portion being configured to forward an interface information table, an adjacency table, and a forwarding information table; the communication support section provides a ring queue of the shared memory between systems for supporting communication between systems.

4. The RISCV heterogeneous multi-core SOC based packet processing system of claim 1, wherein processing forwarding the packet according to the entry configuration includes:

carrying out message analysis on the packet to obtain a protocol message;

5. The RISCV heterogeneous multi-core SOC based packet processing system of any of claims 1 to 4, further having a switching mode in which:

6. A message processing method based on the message processing system of the RISCV heterogeneous multi-core SOC according to any of claims 1 to 5, wherein the message processing method includes:

receiving a packet;

the related instruction is an instruction input by a user.

7. The method for processing a message according to claim 6, wherein the routing mode is:

uploading the packet to a shared memory of each data core cluster;

8. The message processing method according to claim 6, wherein the switching mode is: