CN117317018A - 一种高容错率抑制电压过冲的U槽屏蔽型SiC VDMOSFET结构 - Google Patents

一种高容错率抑制电压过冲的U槽屏蔽型SiC VDMOSFET结构 Download PDF

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CN117317018A
CN117317018A CN202311522453.6A CN202311522453A CN117317018A CN 117317018 A CN117317018 A CN 117317018A CN 202311522453 A CN202311522453 A CN 202311522453A CN 117317018 A CN117317018 A CN 117317018A
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许一力
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Hangzhou Spectro Crystal Semiconductor Technology Co ltd
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Abstract

本发明公开一种高容错率抑制电压过冲的U槽屏蔽型SiC VDMOSFET结构，包括引入U槽的MOS元胞并在其中构建有N+/P+/polySi背靠背二极管、屏蔽结构及阶梯栅氧，避免栅源电极在开关过程中因剧烈振荡而出现的过电压应力，屏蔽结构可以提高器件的雪崩能力，还可以大幅降低器件发生短路时的饱和电流，提高器件的短路能力，采用更厚的氧化层厚度，提高器件在出现漏源电压过冲或雪崩击穿时的性能稳定性，保障器件的长期可靠安全工作，二者协同工作可以避免某些单步工艺偏差对器件的抑制电压过冲效果产生严重影响，极大的提高器件制造过程中的容错率，提高器件良品率，此外，单个重复的元胞尺寸得以减小，增大电流密度，进一步提升器件的性能的丰富性和容错率。

Description

一种高容错率抑制电压过冲的U槽屏蔽型SiC VDMOSFET结构
技术领域
本发明涉及SiC MOSFET的片上结构改进技术领域，具体涉及一种高容错率抑制电压过冲的U槽屏蔽型SiC VDMOSFET结构。
背景技术
SiC MOSFET器件具有高频低损耗的显著优势，在电动汽车、光伏逆变器和充电桩等领域有十分广泛的应用。然而，SiC MOSFET极快的开关速度使得器件在开通和关断过程中极易产生电压过冲的问题，电压过冲问题主要体现在两个方面：1.栅源电压过冲；2.漏源电压过冲。
栅源电压过冲：栅源电压过冲问问题极易导致SiC MOS栅氧承受极高的电压应力，长期使用过程中易出现栅氧性能退化甚至栅极损坏的现象。为了抑制开关过程中栅源电压过冲的问题，通常采用增大栅极驱动电阻以降低开关速度和在栅源电极之间外接稳压二极管等方法。增大栅极驱动电阻虽然有效缓解了开关过程中的电压过冲问题，但较长的开关时间不仅增大了开关损耗，而且无法充分发挥出SiC MOSFET高速开关的性能优势。同样地，在栅源电极之间外接稳压二极管会增大栅源之间的电容，降低SiC MOSFET的开关速度。此外，由于外接稳压二极管通常为型号固定的商用器件，其稳压性能、寄生电容等通常无法直接和SiC MOSFET形成最佳匹配，严重限制了SiC MOSFET器件性能的充分发挥。图1中展示了两种常用的抑制SiC MOSFET快速开关过程中出现电压过冲的方法。
漏源电压过冲：漏源电压过冲极易在800V的电驱系统等应用中导致SiC MOSFET器件出现短时的雪崩击穿，在SiC MOS栅氧附近形成极大的电热应力，长期使用过程中易出现器件性能退化甚至损坏的问题；另一方面SiC MOSFET在电驱系统发生负载短路时会出现短路故障，瞬时的高压大电流极易导致器件短路失效。目前针对同时优化SiC MOSFET器件雪崩能力和短路能力的方法极少，大部分仍是基于单种鲁棒性进行优化提升。比如，通常采用优化P阱掺杂形貌和优化终端电场分布等调整元胞结构参数的方法，或者在器件关断过程中优化驱动防止器件出现漏源电压过冲等方法来提升SiC MOSFET雪崩能力或者抑制器件出现漏源电压过冲，采用缩短JFET区或者在驱动电路中集成短路保护功能等方法来改善SiC MOSFET在实际电源系统中的短路故障穿越能力。这些方法通常只能改善器件的一种鲁棒性，而且会给器件的其他性能引入负面影响。例如，缩短JFET宽度可能造成SiC MOSFET器件比导通电阻增大，导致器件导通损耗增大。如图2所示为提升器件雪崩能力而采用的倒掺杂P阱SiC MOSFET元胞结构，图3所示为提升器件短路能力而采用的窄JFET区SiC MOSFET元胞结构，图4所示为图2和图3两种结构的源区俯视图。
但是实际成产和实用过程中发现，现有的器件性能单一，不能兼顾抑制栅源电压和漏源电压，仅有单一的功能，另外，目前在改善器件的各种性能方面太过于注重，但是很多研发这忽略了器件尺寸方面的同步改进优势，要么就是在传统的器件上减小尺寸，要么就是只研究各种抑制栅源电压过冲和漏源电压过冲等顾此失彼，研究表明，目前尚未有关将抑制栅源电压过冲和漏源电压过冲兼并较小元胞尺寸的器件文件批漏，并且某些单步工艺偏差对器件的抑制电压过冲效果产生严重影响，器件制造过程中的容错率极低，器件良品率极低，因此本发明提供了一种针对SiC MOSFET器件全方位的解决方案，。
发明内容
有鉴于此，本发明的目的在于提供一种高容错率抑制电压过冲的U槽屏蔽型SiCVDMOSFET结构，通过在原SiC VDMOSFET的元胞引入U槽并在其内的栅极和源极之间单片集成N+/P+1/polySi结构，构建出两个背靠背的钳位二极管，其一为N+/P+1二极管，其二为P+1/polySi异质结二极管，避免栅源电极在开关过程中因剧烈振荡而出现的过电压应力，在同一元胞的P阱侧面JFET区引入屏蔽结构及对应的阶梯型栅氧结构，屏蔽结构一方面在JFET区底部实现大幅缩短JFET区的宽度，达到屏蔽器件在发生漏源电压过冲时在栅氧下形成的极强电场，提升器件的雪崩能力；另一方面较窄的JFET区出口有利于在JFET区底部通过耗尽效应减小器件短路时的电流路径宽度，大幅降低器件的短路饱和电流，进而提升SiCMOSFET的短路能力。此外，通过引入屏蔽结构，可以对栅氧下方的JFET区形成良好的保护作用，因此可以大幅提高栅氧下方JFET区的掺杂浓度，降低SiC MOSFEET积累层电阻和JFET电阻，突破常规SiC MOSFET结构优化中器件导通电阻和短路能力难以协同提升的难题；在沟道区上面保持原有的栅氧厚度不变进而保持SiC MOSFET具有稳定的阈值电压，在JFET区上方则采用加厚的栅氧厚度，通过增加JFET区上方的栅氧厚度达到降低SiC MOSFET发生雪崩击穿时栅氧内的电场强度，进而抑制热载流子注入效应，降低SiC MOSFET器件因发生漏源电压过冲而导致的器件性能退化甚至损坏的风险，从而可以避免某些单步工艺偏差对器件的抑制电压过冲效果产生严重影响，极大的提高器件制造过程中的容错率，提高器件良品率；引入U槽结构使P阱与N阱的欧姆接触需同时与源极的短接由横向转为纵向，减小了单个重复元胞尺寸，增加了器件的电流密度。
为解决以上技术问题，本发明提供一种高容错率抑制电压过冲的U槽屏蔽型SiCVDMOSFET结构，包括碳化硅外延层，所述碳化硅外延层上通过离子注入等距分布呈井状并为P型半导体的P阱，相邻所述P阱之间形成有JFET区，所述P阱中部通过极高浓度的相同离子注入形成为P型半导体的P+1，所述P+1的两侧通过极高浓度的离子注入形成为N型半导体的N阱，所述N阱与所述P+1接触，所述N阱不靠近所述P阱侧面，所述JFET区上方形成有所述栅氧层，所述栅氧层上淀积有所述多晶硅栅极，所述多晶硅栅极上淀积有介质层，所述栅氧层和所述多晶硅栅极至少延伸位于所述N阱上方，所述碳化硅外延层上淀积有覆盖所述介质层的源极，所述碳化硅外延层下侧具有N衬底，所述N衬底下方具有漏极，为了便于理解，将由多晶硅栅极纵向对应的单位范围内相同的结构定义为所述MOS元胞，其特征在于，至少一侧的所述N阱上通过离子注入形成有P型半导体区的P+2，所述P+2与多晶硅栅极接触，同一所述N阱的欧姆接触与源极短接以形成N+/P+/polySi背靠背二极管，所述JFET区的横截面呈柱型轮廓，所述柱型轮廓至少具有一粗径段和一细径段以形成屏蔽结构，所述粗径段与所述MOS元胞的栅氧层接触，所述栅氧层上具有一凸起段，所述凸起段位于所述MOS元胞的JFET区上方，使得凸起段降低自身内部的雪崩击穿时的电场强度进行抑制热载流子注入，所述多晶硅栅极与所述栅氧层榫卯适配型淀积；所述N阱上刻蚀开凿有U槽，所述U槽贯穿所述N阱并深入至所述P阱内，所述U槽内淀积有金属的源极，所述源极与所述N阱和P阱的欧姆接触同时短接，使得源极与所述N阱和P阱的欧姆接触同时短接由横向转变为纵向。
在一些实施例中优选地方案，所述P+2位于所述N阱内中部或不靠近侧面，所述多晶硅栅极只与所述P+2接触。
在一些实施例中优选地方案，所述凸起段横截面呈矩形状或椭圆状或拱桥形状或倒拱桥形状或台阶状或连续不规则形状或梯形状。
在一些实施例中优选地方案，所述栅氧层上还具有位于所述凸起段两端的平薄段，所述平薄段厚度小于凸起段的厚度，所述JFET区与所述N阱之间的P阱正上方的栅氧层为平薄层。
在一些实施例中优选地方案，所述粗径段和所述细径段自上而下布置并依次连通。
在一些实施例中优选地方案，所述粗径段与所述细径段的直径呈等差数值，和/或，所述粗径段与所述细径段的直径呈非等差数值。
在一些实施例中优选地方案，所述JFET区的粗径段和细径段对应的离子浓度相同并且为高浓度。
在一些实施例中优选地方案，所述介质层为SiO2。
在一些实施例中优选地方案，所述P阱上的注入的离子为倒注入，即所述P阱的底部离子浓度高于顶部浓度。
在一些实施例中优选地方案，所述P阱注入的离子为Al离子或B离子，所述P+1注入为极高浓度的Al离子或B离子，所述N阱注入的离子为极高浓度的P离子或N离子。
与现有技术相比，本发明的优点如下：
1、本发明的结构通过在原SiC VDMOSFET的元胞内引入U槽并在栅极和源极之间单片集成N+/P+1/polySi结构，构建出两个背靠背的钳位二极管，其一为N+/P+1二极管，其二为P+1/polySi异质结二极管，避免栅源电极在开关过程中因剧烈振荡而出现的过电压应力，并且在同一元胞的JFET区采用屏蔽注入结构和对应的阶梯型栅氧结构，阶梯型栅氧结构可以实现在沟道区上面保持原有的栅氧厚度不变进而保持SiC MOSFET具有稳定的阈值电压，在JFET区上方则采用加厚的栅氧厚度，通过增加JFET区上方的栅氧厚度达到降低SiCMOSFET发生雪崩击穿时栅氧内的电场强度，进而抑制热载流子注入效应，降低SiC MOSFET器件因发生漏源电压过冲而导致的器件性能退化甚至损坏的风险。通过在P阱底部引入屏蔽结构，一方面在JFET区底部实现大幅缩短JFET区的宽度，达到屏蔽器件在发生漏源电压过冲时在栅氧下形成的极强电场，提升器件的雪崩能力；另一方面较窄的JFET区出口有利于在JFET区底部通过耗尽效应减小器件短路时的电流路径宽度，大幅降低器件的短路饱和电流，进而提升SiC MOSFET的短路能力，且二者相互配合，可以避免某些单步工艺偏差对器件的抑制电压过冲效果产生严重影响，极大的提高器件制造过程中的容错率，提高器件良品率，从而可以实现器件的性能全面兼顾性，不用额外加装器件，引入U槽结构使P阱与N阱的欧姆接触需同时与源极的短接由横向转为纵向，减小了单个重复元胞尺寸，增加了器件的电流密度。
2、本发明引入的屏蔽结构和阶梯型栅氧结构为直接在SiC MOSFET元胞中的JFET区中直接改进形成，结构简单，工艺易于实现。
3、通过引入屏蔽结构，可以对栅氧下方的JFET区形成良好的保护作用，因此可以大幅提高栅氧下方JFET区的掺杂浓度，降低SiC MOSFEET积累层电阻和JFET电阻，突破常规SiC MOSFET结构优化中器件导通电阻和短路能力难以协同提升的难题，可以大幅提升器件的综合性能。
4、本发明的结构在单片集成N-SiC/P-SiC/polySi结构时，仅需在SiC MOSFET芯片版图设计中，将部分元胞结构中的栅极多晶硅直接和P-SiC接触形成异质结二极管，并将P-SiC旁边的N+型半导体区上的欧姆接触和源极金属短接，既可在版图局部形成N-SiC/P-SiC/polySi结构，实际实现方法简便可行。
5、可同时实现SiC MOSFET栅源电极之间正向和反向过电压保护。
6、通过结构或工艺优化，易于实现SiC MOSFET与集成N-SiC/P-SiC/polySi结构性能的最佳匹配。
7、本发明的单片集成结构工艺实现和SiC MOSFET完全兼容，实现成本低，性能提升高。
8、本发明的结构片上集成N-SiC/P-SiC/polySi结构集成进P-WELL中，节省了源区面积，具有更大的电流密度。
附图说明
图1为现有的调节驱动电阻抑制栅源电压过冲的SiC MOSFET局部片上结构图。
图2为现有的外接稳压二极管抑制栅源电压过冲的SiC MOSFET局部片上结构图。
图3为现有的含倒掺杂P阱注入形貌的SiC MOSFET结构示意图。
图4为现有的窄JFET区的SiC MOSFET结构示意图。
图5为图3和图4两种结构的源区俯视图。
图6为本发明的SiC VDMOSFET结构示意图。
图7为本发明的屏蔽结构的另一种结构示意图。
图8为本发明的屏蔽结构的另一种结构示意图。
图9为本发明的屏蔽结构的另一种结构示意图。
图10为本发明的屏蔽结构的另一种结构示意图。
图11为本发明的屏蔽结构的另一种结构示意图。
具体实施方式
为了便于理解本发明技术方案，以下结合附图与具体实施例进行详细说明。
参见图6，在本实施例中举例说明本发明的一种高容错率抑制电压过冲的U槽屏蔽型SiC VDMOSFET结构，首先一般的SiC MOSFET结构，包括碳化硅外延层，碳化硅外延层上通过离子注入等距分布呈井状并为P型半导体的P阱，相邻P阱之间形成有JFET区，P阱中部通过极高浓度的相同离子注入形成为P型半导体的P+1，P+1的两侧通过极高浓度的离子注入形成为N型半导体的N阱，N阱与P+1接触，N阱不靠近P阱侧面，在本发明中，P阱注入的离子为Al离子或B离子，P+1注入为极高浓度的Al离子或B离子，N阱注入的离子为极高浓度的P离子或N离子，在本实施例中，P阱注入的离子为Al离子，N阱注入的离子为极高浓度的P离子，并且在本发明中，P阱上的注入的离子为倒注入，即P阱的底部离子浓度高于顶部浓度，JFET区上方形成有栅氧层，栅氧层上淀积有多晶硅栅极，多晶硅栅极上淀积有介质层，栅氧层和多晶硅栅极至少延伸位于N阱上方，碳化硅外延层上淀积有覆盖介质层的源极，在本实施例中，介质层为SiO2，碳化硅外延层下侧具有N衬底，N衬底下方具有漏极，为了便于理解，将由多晶硅栅极纵向对应的单位范围内相同的结构定义为MOS元胞，这些MOS元胞并联连接。
在本发明中，首先在，N阱上刻蚀开凿有U槽，U槽贯穿所述N阱并深入至P阱内，U槽内淀积有金属的源极，源极与N阱和P阱的欧姆接触同时短接，使得源极与所述N阱和P阱的欧姆接触同时短接由横向转变为纵向，从而单个重复的元胞尺寸得以减小，进而增大电流密度，MOS元胞中具有N+/P+/polySi背靠背二极管，N+/P+/polySi背靠背二极管包括通过离子注入形成于MOS元胞其中一侧的N阱内的P+2型半导体区，P+2位于N阱内中部或不靠近侧面，也就是在P+2的两侧空出N阱，在本发明中，P+1与P+2注入为相同Al离子，N阱的欧姆接触短接源极，以形成源极侧的N+/P+结二极管，P+2直接与MOS元胞的一端多晶硅栅极接触，多晶硅栅极位于P+2正上部贯穿MOS元胞的栅氧层并与之连接，多晶硅栅极只与P+2接触，也就是说，在本发明中，多晶硅栅极仅仅局部在不影响MOS元胞的基本性能基础上将其连接至P+2上，不影响MOS元胞其他栅氧层和基本开关结构，以形成P+/polySi异质结二极管。在制造时，仅需在SiC MOSFET芯片版图设计中，通过将部分元胞结构中的N阱中加入P+型半导体区形成P+2，然后将栅极多晶硅直接和P-SiC接触形成异质结二极管，并将P-SiC旁边的N阱上的欧姆接触和源极金属短接，在版图局部形成N-SiC/P-SiC/polySi结构，实现在栅源电极之间构建出两个背靠背的钳位二极管。在工作时，由于N+P+结两侧的掺杂浓度极高，具有较强的隧穿效应，可以实现钳位稳压的作用，同时，P-SiC/polySi异质结二极管的势垒高度有限，同样存在较强的隧穿效应，可以实现钳位稳压的作用，在栅源电极正向过电压时，P-SiC/polySi异质结反偏结构出现隧穿，避免SiC MOS栅氧遭受正向过电压应力；在栅源电极负向过电压时，N+(源极侧)P+反偏结构出现隧穿，避免SiC MOS栅氧遭受负向过电压应力，在栅源过压时利用隧穿效应有效抑制电压过冲，保护SiC MOS栅氧免遭极高的电压应力冲击而退化或损伤。另外，最佳适应性能调整发明，P-SiC/polySi异质结势垒高度和N+(源极侧)P+结的隧穿电压可以通过调节掺杂浓度等方法实现，保障集成结构具有预期的钳位能力，并与SiC MOSFET实现最佳的性能匹配。将片上集成N-SiC/P-SiC/polySi结构集成进P-WELL中，大幅度减少了单个重复元胞尺寸，节省了源区面积，具有更大的电流密度
对于现有没有抵抗雪崩击穿能力、较低短路能力以及短路能力和导通电阻难以协同优化的SiC MOSFET结构的JFET区是宽度比较大的竖直井状。而本发明的实施例中提供了一种引入屏蔽结构的JFET区，在本发明中，该JFET区的横截面呈柱型轮廓，柱型轮廓至少具有一粗径段和一细径段以形成屏蔽结构，粗径段与所述MOS元胞的栅氧层接触，粗径段和所述细径段自上而下布置并依次连通，即无论粗径段和细井段直径之间的连接差值多大，二者之间总是连续连通的，在本发明中，粗径段与细径段的直径呈等差数值，即可以是如梯形状的自上而下均匀变小的形状，也可以是具有台阶状自上而下缩小的多个竖直柱状，如图7和8，当然，本发明还考虑到，粗径段与细径段的直径呈非等差数值，即粗径段是很大的直径突然变化到直径很小的细径段，也可以是，一段是直径连续变小的后又突变差值比较大的，如上面是阶梯状下面是倒锥台或上面是到锥台下面是阶梯状，如图9-11。JFET区的粗径段和细径段对应的离子浓度相同并且为高浓度，P阱与所述JFET区外侧对应的结构呈榫卯适配的连接。
SiC MOSFET在发生雪崩击穿时，JFET区域存在极高的电场分布，在强电场的作用下，器件内部将产生强烈的碰撞电离，大量的电子-空穴对在电场作用下可能发生隧穿效应进入栅氧中，进而导致器件出现性能退化甚至因为极强的电热耦合效应损坏器件。本发明的结构在JFET区底部引入屏蔽结构，可以利用底部的细径段的JFET形成良好的夹断效应，有效屏蔽强电场在栅氧下方的分布，从而提高器件的雪崩能力。
SiC MOSFET在发生短路时，较高的漏源偏压导致极大的饱和电流流过器件内部，导致器件内部瞬时形成极高的热积累，进而引发器件性能退化或直接失效。本发明结构在JFET区底部引入的屏蔽结构可以在高漏源偏压下将细径段的JFET电流通道极大程度的耗尽，大幅降低器件发生短路时的饱和电流，从而有效降低器件短路时内部的热产生和热积累，提高器件的短路能力。
此外，由于引入的屏蔽结构可以对栅氧下方的JFET区形成良好的屏蔽保护，因此可以进一步提高栅氧下方JFET区的掺杂浓度，进而降低SiC MOSFET积累层电阻和JFET电阻，实现更低比导通电阻的SiC MOSFET。
在本发明中，多晶硅栅极下侧具有一层栅氧层，栅氧层上具有一凸起段，栅氧层上还具有位于凸起段两端的平薄段，平薄段厚度小于凸起段的厚度，在本实施例中，凸起段横截面为矩形，包括本实施例但不限于还可以为凸起段横截面呈椭圆状或拱桥形状或倒拱桥形状或台阶状或连续不规则形状或梯形状，无论怎么变性必须保证最低点的高度高于平薄段，在本发明中，JFET区与N阱之间的P阱正上方的栅氧层为平薄层，使得在沟道区上面保持原有的栅氧厚度不变进而保持SiC MOSFET具有稳定的阈值电压，凸起段位于MOS元胞的JFET区上方，使得凸起段降低自身内部的雪崩击穿时的电场强度进行抑制热载流子注入，多晶硅栅极与栅氧层榫卯适配型淀积，从而实现采用阶梯型栅氧结构，在沟道区上面保持原有的栅氧厚度不变进而保持SiC MOSFET具有稳定的阈值电压，在JFET区上方则采用加厚的栅氧厚度，通过增加JFET区上方的栅氧厚度达到降低SiC MOSFET发生雪崩击穿时栅氧内的电场强度，进而抑制热载流子注入效应，降低SiC MOSFET器件因发生漏源电压过冲而导致的器件性能退化甚至损坏的风险。工作时，由于在SiC MOSFET在发生雪崩击穿时，JFET区域存在极高的电场分布，在强电场的作用下，器件内部将产生强烈的碰撞电离，大量的电子-空穴对在电场作用下可能发生隧穿效应进入栅氧中，进而导致器件出现性能退化甚至因为极强的电热耦合效应损坏器件，本发明的结构通过在JFET区上方采用更厚的氧化层厚度，实现降低SiC MOSFET发生雪崩击穿时氧化层中的电场强度，抑制热载流子注入到栅氧中，提高器件在出现漏源电压过冲或雪崩击穿时的性能稳定性，保障器件的长期可靠安全工作。
从而本发明的结构在同一元胞中采用N+/P+/polySi背靠背二极管、阶梯栅氧及屏蔽注入结构，可以实现同一器件兼顾抑制栅源电压过冲和漏源电压过冲，从而提升器件的性能全面性，避免额外加装，可以避免某些单步工艺偏差对器件的抑制电压过冲效果产生严重影响，极大的提高器件制造过程中的容错率，提高器件良品率。
以上仅是本发明的优选实施方式，本发明的保护范围以权利要求所限定的范围为准，本领域技术人员在不脱离本发明的精神和范围内做出的若干改进和润饰，也应视为本发明的保护范围。

Claims (10)

1.一种高容错率抑制电压过冲的U槽屏蔽型SiC VDMOSFET结构，包括碳化硅外延层，所述碳化硅外延层上通过离子注入等距分布呈井状并为P型半导体的P阱，相邻所述P阱之间形成有JFET区，所述P阱中部通过极高浓度的相同离子注入形成为P型半导体的P+1，所述P+1的两侧通过极高浓度的离子注入形成为N型半导体的N阱，所述N阱与所述P+1接触，所述N阱不靠近所述P阱侧面，所述JFET区上方形成有所述栅氧层，所述栅氧层上淀积有所述多晶硅栅极，所述多晶硅栅极上淀积有介质层，所述栅氧层和所述多晶硅栅极至少延伸位于所述N阱上方，所述碳化硅外延层上淀积有覆盖所述介质层的源极，所述碳化硅外延层下侧具有N衬底，所述N衬底下方具有漏极，为了便于理解，将由多晶硅栅极纵向对应的单位范围内相同的结构定义为所述MOS元胞，其特征在于，至少一侧的所述N阱上通过离子注入形成有P型半导体区的P+2，所述P+2与多晶硅栅极接触，同一所述N阱的欧姆接触与源极短接以形成N+/P+/polySi背靠背二极管，所述JFET区的横截面呈柱型轮廓，所述柱型轮廓至少具有一粗径段和一细径段以形成屏蔽结构，所述粗径段与所述MOS元胞的栅氧层接触，所述栅氧层上具有一凸起段，所述凸起段位于所述MOS元胞的JFET区上方，使得凸起段降低自身内部的雪崩击穿时的电场强度进行抑制热载流子注入，所述多晶硅栅极与所述栅氧层榫卯适配型淀积；所述N阱上刻蚀开凿有U槽，所述U槽贯穿所述N阱并深入至所述P阱内，所述U槽内淀积有金属的源极，所述源极与所述N阱和P阱的欧姆接触同时短接，使得源极与所述N阱和P阱的欧姆接触同时短接由横向转变为纵向。
2.根据权利要求1所述的一种高容错率抑制电压过冲的U槽屏蔽型SiC VDMOSFET结构，其特征在于，所述P+2位于所述N阱内中部或不靠近侧面，所述多晶硅栅极只与所述P+2接触。
3.根据权利要求1所述的一种高容错率抑制电压过冲的U槽屏蔽型SiC VDMOSFET结构，其特征在于，所述凸起段横截面呈矩形状或椭圆状或拱桥形状或倒拱桥形状或台阶状或连续不规则形状或梯形状。
4.根据权利要求1所述的一种高容错率抑制电压过冲的U槽屏蔽型SiC VDMOSFET结构，其特征在于，所述栅氧层上还具有位于所述凸起段两端的平薄段，所述平薄段厚度小于凸起段的厚度，所述JFET区与所述N阱之间的P阱正上方的栅氧层为平薄层。
5.根据权利要求1所述的一种高容错率抑制电压过冲的U槽屏蔽型SiC VDMOSFET结构，其特征在于，所述粗径段和所述细径段自上而下布置并依次连通。
6.根据权利要求1所述的一种高容错率抑制电压过冲的U槽屏蔽型SiC VDMOSFET结构，其特征在于，所述粗径段与所述细径段的直径呈等差数值，和/或，所述粗径段与所述细径段的直径呈非等差数值。
7.根据权利要求1所述的一种高容错率抑制电压过冲的U槽屏蔽型SiC VDMOSFET结构，其特征在于，所述JFET区的粗径段和细径段对应的离子浓度相同并且为高浓度。
8.根据权利要求1所述的一种高容错率抑制电压过冲的U槽屏蔽型SiC VDMOSFET结构，其特征在于，所述介质层为SiO2。
9.根据权利要求1所述的一种高容错率抑制电压过冲的U槽屏蔽型SiC VDMOSFET结构，其特征在于，所述P阱上的注入的离子为倒注入，即所述P阱的底部离子浓度高于顶部浓度。
10.根据权利要求1所述的一种高容错率抑制电压过冲的U槽屏蔽型SiC VDMOSFET结构，其特征在于，所述P阱注入的离子为Al离子或B离子，所述P+1注入为极高浓度的Al离子或B离子，所述N阱注入的离子为极高浓度的P离子或N离子。
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