CN117316932A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The present application relates to a semiconductor device and a method of manufacturing the same, the semiconductor device including: the first metal layer is arranged on the substrate; the dielectric layer is arranged on one side of the first metal layer far away from the substrate; the dielectric layer is internally provided with at least one metal ring; the second metal layer is arranged on one side of the dielectric layer far away from the first metal layer; the potential of the second metal layer is higher than that of the first metal layer; the metal ring is projected on the substrate, is positioned at the periphery of the second metal layer projected on the substrate, and has a first interval between the metal ring projected on the substrate and the second metal layer projected on the substrate. Therefore, the electric field distribution at the edge of the second metal layer is optimized through the field plate effect of the metal ring, so that the electric field intensity at the edge of the second metal layer is reduced, the withstand voltage of the semiconductor device is improved, the dielectric layer is prevented from being broken down in advance, and the service life of the semiconductor device is prolonged.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present disclosure relates to the field of integrated circuits, and more particularly, to a semiconductor device and a method for manufacturing the same.

Background

Electrical isolation (galvanic isolation) refers to a way to avoid direct current flow from one region to another region in a circuit, i.e., no direct current flow path is established between the two regions. Originally, an optocoupler isolator is mostly adopted as an isolator, and with the continuous progress of a CMOS (complementary metal oxide semiconductor) process, a digital isolation technology starts to advance in a large step and is gradually accepted by the market, and the high reliability and the high speed of the isolator are far beyond the limit of the traditional optocoupler technology.

At present, a commonly used CMOS high-voltage isolation capacitor is prepared by adopting a surface dielectric lamination process, wherein a layer of metal is deposited on the surface of a silicon wafer to serve as a lower polar plate of the high-voltage isolation capacitor, a layer of silicon dioxide or a composite layer of silicon dioxide and silicon nitride is grown on the metal lower polar plate to serve as a dielectric layer of the high-voltage isolation capacitor, and finally a layer of metal is deposited on the dielectric layer to serve as an upper polar plate of the high-voltage isolation capacitor.

However, in the conventional high-voltage isolation capacitor, the dielectric layer at the edge of the upper plate is easily broken down in advance, reducing the service life of the high-voltage isolation capacitor.

Disclosure of Invention

Based on this, it is necessary to provide a semiconductor device and a method for manufacturing the same, aiming at the problem that the dielectric layer at the edge of the upper plate is easily broken down in advance in the conventional high-voltage isolation capacitor.

In order to achieve the above object, in a first aspect, the present application provides a semiconductor device including a substrate, the semiconductor device further comprising:

the first metal layer is arranged on the substrate;

the dielectric layer is arranged on one side of the first metal layer far away from the substrate;

the dielectric layer is internally provided with at least one metal ring; and

the second metal layer is arranged on one side of the dielectric layer away from the first metal layer; the second metal layer has a higher potential than the first metal layer.

The metal ring is projected on the substrate in a front mode, is located on the periphery of the front projection of the second metal layer on the substrate, and has a first interval between the front projection of the metal ring on the substrate and the front projection of the second metal layer on the substrate.

In the semiconductor device, the metal ring is arranged in the dielectric layer, so that the orthographic projection of the metal ring on the substrate surrounds the periphery of the orthographic projection of the second metal layer on the substrate, and a first interval is reserved between the orthographic projections of the metal ring and the second metal layer. Therefore, the electric field distribution at the edge of the second metal layer is optimized through the field plate effect of the metal ring, so that the electric field intensity at the edge of the second metal layer is reduced, the withstand voltage of the semiconductor device is improved, the dielectric layer is prevented from being broken down in advance, and the service life of the semiconductor device is prolonged.

In one embodiment, the semiconductor device comprises at least one metal ring group, wherein each metal ring group comprises a plurality of metal rings which are arranged at intervals in a direction perpendicular to the substrate;

wherein at least one metal ring in the metal ring group is arranged in the dielectric layer.

In one embodiment, in the same metal ring set, all orthographic projections of the metal rings on the substrate overlap each other.

In one embodiment, in the same metal ring set, all the metal rings are disposed in the dielectric layer.

In one embodiment, one metal ring in the same metal ring group is arranged on one side surface of the dielectric layer, which is far away from the first metal layer;

the rest metal rings are arranged in the dielectric layer.

In one embodiment, the semiconductor device includes a plurality of the metal ring sets;

and a plurality of orthographic projections of the metal ring groups on the substrate are arranged around orthographic projections of the second metal layer on the substrate and are spaced from each other.

In one embodiment, two adjacent sets of metal rings have a second spacing between orthographic projections on the substrate, the second spacing being equal to the first spacing.

In one embodiment, the first pitch is between 2-5 μm.

In one embodiment, the thickness of the metal ring is equal to the thickness of the second metal layer.

And/or the materials of the first metal layer, the second metal layer and the metal ring are the same.

In a second aspect, the present application further provides a method for manufacturing a semiconductor device, where the method for manufacturing a semiconductor device includes:

forming a first metal layer on a substrate;

forming a dielectric layer on the first metal layer; wherein, at least one metal ring is arranged in the dielectric layer;

forming a second metal layer on the dielectric layer; wherein the potential of the second metal layer is higher than the potential of the first metal layer; the orthographic projection of the metal ring on the substrate is positioned at the periphery of the orthographic projection of the second metal layer on the substrate, and a first interval is formed between the orthographic projection of the metal ring on the substrate and the orthographic projection of the second metal layer on the substrate.

According to the manufacturing method of the semiconductor device, the metal ring is arranged in the dielectric layer, so that the orthographic projection of the metal ring on the substrate surrounds the periphery of the orthographic projection of the second metal layer on the substrate, and a first interval is reserved between the orthographic projections of the metal ring and the second metal layer. Therefore, the electric field distribution at the edge of the second metal layer is optimized through the field plate effect of the metal ring, so that the electric field intensity at the edge of the second metal layer is reduced, the withstand voltage of the semiconductor device is improved, the dielectric layer is prevented from being broken down in advance, and the service life of the semiconductor device is prolonged.

Drawings

In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.

Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of another semiconductor device according to an embodiment of the present application;

fig. 3 is a schematic structural view of still another semiconductor device according to an embodiment of the present application;

fig. 4 is a schematic structural view of yet another semiconductor device provided in an embodiment of the present application;

fig. 5 is a schematic structural view of yet another semiconductor device provided in an embodiment of the present application;

fig. 6 is a schematic structural diagram of yet another semiconductor device provided in an embodiment of the present application;

fig. 7 is a schematic structural view of yet another semiconductor device provided in an embodiment of the present application;

fig. 8 is a perspective view of a portion of the structure of the semiconductor device of fig. 7;

FIG. 9 is a top view of FIG. 8;

fig. 10 is a schematic structural view of yet another semiconductor device provided in an embodiment of the present application;

FIG. 11 is a schematic diagram showing simulated electric field distribution of a semiconductor device without metal rings according to an embodiment of the present application;

FIG. 12 is a schematic diagram illustrating electric field distribution simulation of a semiconductor device with a metal ring on the surface of a dielectric layer according to an embodiment of the present application;

FIG. 13 is a schematic diagram illustrating electric field distribution simulation of a semiconductor device with a metal ring disposed in a dielectric layer according to an embodiment of the present application;

FIG. 14 is a schematic diagram illustrating electric field distribution simulation of a semiconductor device provided with metal rings on the surface of a dielectric layer and in the dielectric layer according to an embodiment of the present application;

fig. 15 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application;

FIG. 16 is a schematic view of a metal ring formed according to an embodiment of the present disclosure;

fig. 17 is a schematic structural diagram of a second metal layer formed according to an embodiment of the present application.

Reference numerals illustrate:

a 100-semiconductor device; 110-a substrate; 120-a first metal layer; 130-a dielectric layer; 131-a first dielectric layer; 132-a second dielectric layer; 140-a second metal layer; 150-metal rings; 160-metal ring sets; 170-a passivation layer; 180-isolation structures; 190-interconnect structure.

Detailed Description

In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Examples of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application, such that variations of the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.

It should be noted that the high electric field region at the edge of the plate forming the high-voltage capacitor limits the breakdown voltage of the high-voltage capacitor. Taking the example that the upper polar plate of the high-voltage capacitor is connected with high potential, on one hand, the electric field intensity between the upper polar plate and the lower polar plate is relatively uniform, and the electric field intensity at the edge of the upper polar plate is generally relatively high. On the other hand, the upper surface of the dielectric layer is easily defective due to the influence of the manufacturing process of the high-voltage capacitor, such as plasma bombardment or etching, especially near the edge of the upper polar plate. The two factors are overlapped, so that a dielectric layer at the edge of the upper polar plate is easy to break down in advance, and the service life of the high-voltage isolation capacitor is reduced.

In view of the problem that a dielectric layer at the edge of an upper polar plate is easy to break down in advance, the embodiment of the application provides a semiconductor device and a preparation method thereof.

In a first aspect, embodiments of the present application provide a semiconductor device, which may be a high voltage isolation capacitor. The semiconductor device 100 includes a substrate 110, and the substrate 110 may be made of monocrystalline Silicon, polycrystalline Silicon, amorphous Silicon, silicon germanium compound, silicon-On-Insulator (SOI) or low temperature polycrystalline Silicon (Low Temperature Poly-Silicon, LTPS) or the like, or other materials known to those skilled in the art, and the substrate 110 may provide a supporting base for structures On the substrate 110.

Referring to fig. 1, the semiconductor device 100 further includes:

a first metal layer 120 disposed on the substrate 110;

the dielectric layer 130 is disposed on a side of the first metal layer 120 away from the substrate 110; the dielectric layer 130 includes an insulating medium, and the material of the dielectric layer 130 may be silicon dioxide, silicon nitride, silicon oxynitride, or the like.

The metal ring 150, there is at least one metal ring 150 in the dielectric layer 130; and

the second metal layer 140 is disposed on a side of the dielectric layer 130 away from the first metal layer 120. The first metal layer 120 and the second metal layer 140 are both used for electrically connecting with an external circuit, and the potential of the second metal layer 140 is higher than that of the first metal layer 120.

The orthographic projection of the metal ring 150 on the substrate 110 is located at the periphery of the orthographic projection of the second metal layer 140 on the substrate 110, and a first distance L1 is between the orthographic projection of the metal ring 150 on the substrate 110 and the orthographic projection of the second metal layer 140 on the substrate 110. Taking the orientation in fig. 1 as an example, the thickness direction of the dielectric layer 130 refers to the vertical direction.

In this embodiment, the metal ring 150 is a dummy metal ring, and the metal ring 150 is in a floating state when the semiconductor device 100 is in operation, when the second metal layer 140 is connected to a high potential, the metal ring 150 can induce the potential, and the charge on the surface of the second metal layer 140 is shunted from between the first metal layer 120 and the second metal layer 140 to between the second metal layer 140 and the metal ring 150. In this way, by changing the flow of the electric charges, the electric field distribution at the edge of the second metal layer 140 is optimized, so that the electric field intensity at the edge of the second metal layer 140 is reduced, the withstand voltage of the semiconductor device 100 is improved, the dielectric layer 130 is prevented from being broken down in advance, and the service life of the semiconductor device 100 is prolonged.

It can also be understood that: a capacitor is formed between the metal ring 150 and the second metal layer 140, and the capacitor forms a field plate effect, and an electric field of the capacitor uniformly distributes a high-density electric field at the edge of the second metal layer 140, so that an electric field peak value at the edge of the second metal layer 140 is suppressed, the withstand voltage of the semiconductor device 100 is improved, the dielectric layer 130 is prevented from being broken down in advance, and the service life of the semiconductor device 100 is prolonged.

Note that, the first metal layer 120 and the second metal layer 140 are plates of the semiconductor device 100, where the first metal layer 120 may be any one of an upper plate or a lower plate, if the first metal layer 120 is an upper plate, the second metal layer 140 is a lower plate, and if the first metal layer 120 is a lower plate, the second metal layer 140 is an upper plate.

In one embodiment, as shown in fig. 2, the semiconductor device 100 includes at least one metal ring set 160, and each metal ring set 160 includes: a plurality of metal rings 150 spaced apart in a direction perpendicular to the substrate 110. Wherein at least one metal ring 150 of the metal ring set 160 is disposed in the dielectric layer 130.

Thus, it can be understood that: a plurality of "layers" of metal rings 150 are provided, and when the second metal layer 140 is connected to a high potential, each "layer" of metal rings 150 sequentially induces a potential, wherein the metal ring 150 closer to the second metal layer 140 induces the greatest potential. By providing a multi-layer metal ring 150, the flow of more charges can be changed, thereby better optimizing the electric field distribution at the edge of the second metal layer 140, further reducing the electric field strength at the edge of the second metal layer 140, improving the withstand voltage of the semiconductor device 100, avoiding the dielectric layer 130 from being broken down in advance, and improving the service life of the semiconductor device 100.

Specifically, in the same metal ring set 160, all orthographic projections of the metal rings 150 on the substrate 110 overlap each other. Taking the orientation in fig. 2 as an example, it can also be understood that: all the metal rings 150 in the same metal ring set 160 are arranged at intervals in the vertical direction. In this way, the electric field distribution at the edge of the second metal layer 140 can be optimized uniformly, so that the electric field intensity at the edge of the second metal layer 140 is more uniform, the withstand voltage of the semiconductor device 100 is improved, the dielectric layer 130 is prevented from being broken down in advance, and the service life of the semiconductor device 100 is prolonged.

The metal rings 150 in the same metal ring set 160 may have the following two arrangements:

in a first possible embodiment, all metal rings 150 in the same metal ring set 160 are disposed within the dielectric layer 130.

In a second possible embodiment, as shown in fig. 2, one metal ring 150 of the same metal ring set 160 is located on a side surface of the dielectric layer 130 away from the first metal layer 120. The remaining metal rings 150 are disposed within the dielectric layer 130. Thus, when the second metal layer 140 is connected to a high potential, the potential induced by the metal ring 150 on the surface of the dielectric layer 130 is the largest, and part of the charge on the surface of the second metal layer 140 is shunted from between the first metal layer 120 and the second metal layer 140 to between the second metal layer 140 and the metal ring 150, so that the electric field arrangement at the edge of the second metal layer 140 is optimized, the electric field intensity at the edge of the second metal layer 140 is reduced, the withstand voltage of the semiconductor device 100 is improved, the dielectric layer 130 is prevented from being broken down in advance, and the service life of the semiconductor device 100 is prolonged.

It should be noted that, when the metal ring 150 in the dielectric layer 130 is arranged, the metal ring 150 may be located closer to the second metal layer 140, that is: the distance between the metal ring 150 and the second metal layer 140 is smaller than the distance between the metal ring 150 and the first metal layer 120 in the thickness direction of the dielectric layer 130. In this way, the electric field arrangement at the edges of the second metal layer 140 may be better optimized.

In one embodiment, as shown in fig. 3, the semiconductor device 100 includes a plurality of metal ring sets 160, the orthographic projections of the plurality of metal ring sets 160 on the substrate 110, disposed around the orthographic projections of the second metal layer 140 on the substrate and spaced apart from each other. When the number of the metal ring sets 160 is plural, the first pitch L1 refers to: closer to the second metal layer 140 is the distance of the metal ring 150 from the second metal layer 140 in the metal ring set 160.

This arrangement is equivalent to "sleeving" the metal ring set 160 around the outside of the metal ring set 160, and enlarges the field plate effect range, so that the metal ring set 160 can optimize the electric field in a larger range, reduce the electric field strength in a larger range except the second metal layer 140, improve the withstand voltage of the semiconductor device 100, avoid the dielectric layer 130 from being broken down in advance, and improve the service life of the semiconductor device 100.

Specifically, if the number of metal rings 150 in each metal ring set 160 is the same, for example, each metal ring set 160 includes 2 metal rings 150, the metal rings 150 in all metal ring sets 160 that are adjacent to the second metal layer 140 may be located in the same "layer", and the metal rings 150 in all metal ring sets 160 that are adjacent to the first metal layer 120 may be located in the same "layer". Thus, in the fabrication of the semiconductor device 100, all the metal rings 150 located in the same "layer" can be formed at the same time, improving the fabrication efficiency of the semiconductor device 100.

As shown in fig. 4 and 5, the number of metal rings 150 in each metal ring set 160 may also be different. In addition, the metal rings 150 may be arranged in the direction of fig. 6. The arrangement of the metal ring 150 is not limited in this embodiment.

As shown in fig. 7, an isolation structure 180 may be further disposed on the substrate 110, and a capacitor formed by the first metal layer 120, the dielectric layer 130, and the second metal layer 140 may be disposed between adjacent isolation structures 180. Further, interconnect structures 190 may be provided on the substrate 110 for energizing electronic components on the substrate 110.

In one embodiment, two adjacent metal ring sets 160 have a second spacing L2 therebetween, and the second spacing L2 is equal to the first spacing L1. Thus, the electric field distribution at the edge of the second metal layer 140 can be more uniform, so that the electric field intensity at the edge of the second metal layer 140 is more uniform, the withstand voltage of the semiconductor device 100 is improved, the dielectric layer 130 is prevented from being broken down in advance, and the service life of the semiconductor device 100 is prolonged.

In one embodiment, the first pitch L1 is between 2-5 μm. The first pitch L1 may be 2 μm, 3 μm, 3.5 μm, 4.5 μm, or 5 μm, for example. The first interval L1 is within the above numerical range, so that the electric field distribution at the edge of the second metal layer 140 can be better optimized, the withstand voltage of the semiconductor device 100 can be improved, the dielectric layer 130 can be prevented from being broken down in advance, and the service life of the semiconductor device 100 can be prolonged.

In one embodiment, the thickness of the metal ring 150 may be equal to the thickness of the second metal layer 140. Wherein, the thickness of the metal ring 150 means: the distance from the upper surface of the metal ring 150 to the lower surface of the metal ring 150, and the thickness of the second metal layer 140 means: the distance from the upper surface of the second metal layer 140 to the lower surface of the second metal layer 140 (or the upper surface of the dielectric layer).

In addition, the materials of the first metal layer 120, the second metal layer 140, and the metal ring 150 may be the same. By way of example, the metal ring 150, the first metal layer 120, and the second metal layer 140 may be made of copper, aluminum, or any metal or metal alloy suitable for semiconductor processing.

In one embodiment, the semiconductor device 100 further includes a passivation layer 170, and the passivation layer 170 may cover the exposed surface of the dielectric layer 130, the exposed surface of the metal ring 150, and a portion of the surface of the second metal layer 140. The passivation layer 170 may perform an insulating and protecting function, on the one hand, preventing the metal ring 170 from being electrically connected with an external device, and on the other hand, preventing the metal ring 170 from being damaged by an external force. The material of the passivation layer 170 may be silicon oxide or silicon nitride, etc.

As shown in fig. 8, 9, and 10, the first metal layer 120 and the second metal layer 140 have the same shape, and the first metal layer 120 and the second metal layer 140 may have a rectangular shape, an elliptical shape, a circular shape, or the like. In addition, the first metal layer 120 and the second metal layer 140 may be the same or different in size.

Referring to fig. 11, 12, 13 and 14, the inventors respectively simulate electric field distribution of a semiconductor device without a metal ring, a semiconductor device with a metal ring 150 on the surface of the dielectric layer 130 and a semiconductor device with a metal ring 150 on the dielectric layer 130, wherein fig. 11 is a schematic diagram of electric field distribution simulation of a semiconductor device without a metal ring, fig. 12 is a schematic diagram of electric field distribution simulation of a semiconductor device with a metal ring 150 on the surface of the dielectric layer 130, fig. 13 is a schematic diagram of electric field distribution simulation of a semiconductor device with a metal ring 150 on the surface of the dielectric layer 130 and a semiconductor device with a metal ring 150 on the medium layer 130. As can be seen by comparison, the electric field intensity at the edge of the second metal layer 140 in fig. 12 is smaller than the electric field intensity at the edge of the second metal layer 140 in fig. 11, the electric field intensity at the edge of the second metal layer 140 in fig. 13 is smaller than the electric field intensity at the edge of the second metal layer 140 in fig. 12, and the electric field intensity at the edge of the second metal layer 140 in fig. 14 is smaller than the electric field intensity at the edge of the second metal layer 140 in fig. 13. Further, the simulation data shows that the breakdown voltage of the semiconductor device in fig. 11 is 60V, the breakdown voltage of the semiconductor device in fig. 12 is 66V, the breakdown voltage of the semiconductor device in fig. 13 is 71V, and the breakdown voltage of the semiconductor device in fig. 14 is 72V. It can be seen that the arrangement of the metal ring 150 in the dielectric layer 130 can significantly optimize the electric field distribution at the edge of the second metal layer 140, and improve the withstand voltage of the semiconductor device, and the arrangement of the metal ring 150 on the surface of the dielectric layer 130 and in the dielectric layer 130 can further improve the withstand voltage of the semiconductor device on the basis of the foregoing.

In a second aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, as shown in fig. 15, including:

s100: a first metal layer is formed on a substrate.

It is understood that the material of the substrate 110 may be single crystal Silicon, polycrystalline Silicon, amorphous Silicon, silicon germanium compound, silicon-On-Insulator (SOI) or low temperature polycrystalline Silicon (Low Temperature Poly-Silicon, LTPS) or the like, or other materials known to those skilled in the art, and the substrate 110 may provide a support base for the structures On the substrate 110. The material of the first metal layer 120 may be copper, aluminum, or any metal or metal alloy suitable for semiconductor processing. Specifically, the first metal layer 120 may be patterned by a mask, and then the first metal layer 120 is deposited.

S200: forming a dielectric layer on the first metal layer; wherein, at least one metal ring is arranged in the dielectric layer.

Specifically, the material of the dielectric layer 130 may be silicon dioxide, silicon nitride, silicon oxynitride, or the like. The material of the metal ring 150 may be the same as the material of the first metal layer 120.

S300: and forming a second metal layer on the dielectric layer. Specifically, the second metal layer 140 may be patterned by a mask, and then the second metal layer 140 is deposited. The material of the second metal layer 140 may be the same as the material of the first metal layer 120. The first metal layer 120 and the second metal layer 140 are both used for electrically connecting with an external circuit, and the potential of the second metal layer 140 is higher than that of the first metal layer 120.

Specifically, the substrate 110 is disposed perpendicular to the thickness direction of the dielectric layer 130, the orthographic projection of the metal ring 150 on the substrate 110 is located at the periphery of the orthographic projection of the second metal layer 140 on the substrate 110, and a first distance L1 is provided between the orthographic projection of the metal ring 150 on the substrate 110 and the orthographic projection of the second metal layer 140 on the substrate 110.

According to the manufacturing method of the semiconductor device provided by the embodiment of the application, the metal ring 150 is arranged in the dielectric layer 130, so that the orthographic projection of the metal ring 150 on the substrate 110 surrounds the periphery of the orthographic projection of the second metal layer 140 on the substrate 110, and a first interval L1 is reserved between the orthographic projections of the metal ring 150 and the second metal layer. In this way, the field plate effect of the metal ring 150 optimizes the electric field distribution at the edge of the second metal layer 140, thereby reducing the electric field intensity at the edge of the second metal layer 140, improving the withstand voltage of the semiconductor device 100, avoiding the dielectric layer 130 from being broken down in advance, and improving the service life of the semiconductor device 100.

The examples herein illustrate the preparation of a metal ring,

s200: forming a dielectric layer on the first metal layer; wherein, in the step of arranging at least one metal ring in the dielectric layer, the method specifically comprises the following steps:

s210: a first dielectric layer is formed over the first metal layer. The first dielectric layer 131 may be patterned by a mask plate, and then the first dielectric layer 131 is formed by deposition.

S220: a metal ring is formed on the first dielectric layer. Wherein the metal ring 150 may be patterned by a mask and then deposited to form the metal ring 150. The structure of the metal ring 150 after formation is shown in fig. 16.

S230: and forming a second dielectric layer on the surface of the first dielectric layer and the surface of the metal ring. Wherein the first dielectric layer 131 and the second dielectric layer 132 together form a dielectric layer.

After the dielectric layer 130 is formed, a second metal layer 140 may be formed on the surface of the dielectric layer 130, and the structure after the second metal layer 140 is formed is shown in fig. 17. It will be appreciated that if the metal ring 150 has multiple layers, the dielectric layer 130 may be divided into multiple sub-dielectric layers, with each sub-dielectric layer and the metal ring 150 on each sub-dielectric layer being formed in steps.

In one possible implementation, S300: after the step of forming the second metal layer on the dielectric layer, the method includes:

s400: and forming a passivation layer on part of the surface of the second metal layer and the surface of the exposed dielectric layer. The material of the passivation layer 170 may be silicon oxide or silicon nitride, etc. Wherein the passivation layer 170 may be patterned by a mask and then deposited to form the passivation layer 170.

It should be understood that, although the steps in the flowchart of fig. 15 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in fig. 15 may include a plurality of steps or stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily sequential, but may be performed in rotation or alternately with at least a portion of the steps or stages in other steps or other steps.

In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "ideal embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.

Claims (10)

1. A semiconductor device comprising a substrate, the semiconductor device further comprising:

the first metal layer is arranged on the substrate;

the dielectric layer is arranged on one side of the first metal layer far away from the substrate;

the dielectric layer is internally provided with at least one metal ring; and

the second metal layer is arranged on one side of the dielectric layer away from the first metal layer; the potential of the second metal layer is higher than that of the first metal layer;

the metal ring is projected on the substrate in a front mode, is located on the periphery of the front projection of the second metal layer on the substrate, and has a first interval between the front projection of the metal ring on the substrate and the front projection of the second metal layer on the substrate.

2. The semiconductor device of claim 1, wherein the semiconductor device comprises at least one metal ring set, each metal ring set comprising a plurality of metal rings arranged at intervals in a direction perpendicular to the substrate;

wherein at least one metal ring in the metal ring group is arranged in the dielectric layer.

3. The semiconductor device of claim 2, wherein the orthographic projections of all of the metal rings on the substrate in the same metal ring set coincide with each other.

4. The semiconductor device of claim 3, wherein all of the metal rings in the same set of metal rings are disposed within the dielectric layer.

5. The semiconductor device of claim 3, wherein one of the metal rings in the same metal ring set is disposed on a side surface of the dielectric layer remote from the first metal layer;

the rest metal rings are arranged in the dielectric layer.

6. The semiconductor device according to any one of claims 2 to 5, wherein the semiconductor device comprises a plurality of the metal ring groups;

and a plurality of orthographic projections of the metal ring groups on the substrate are arranged around orthographic projections of the second metal layer on the substrate and are spaced from each other.

7. The semiconductor device of claim 6, wherein adjacent two of the sets of metal rings have a second spacing between orthographic projections on the substrate, the second spacing being equal to the first spacing.

8. The semiconductor device according to any one of claims 1 to 5, wherein the first pitch is between 2 and 5 μm.

9. The semiconductor device according to any one of claims 1 to 5, wherein a thickness of the metal ring is equal to a thickness of the second metal layer;

and/or the materials of the first metal layer, the second metal layer and the metal ring are the same.

10. A method of manufacturing a semiconductor device, the method comprising:

forming a first metal layer on a substrate;

forming a dielectric layer on the first metal layer; wherein, at least one metal ring is arranged in the dielectric layer;

forming a second metal layer on the dielectric layer; wherein the potential of the second metal layer is higher than the potential of the first metal layer; the orthographic projection of the metal ring on the substrate is positioned at the periphery of the orthographic projection of the second metal layer on the substrate, and a first interval is formed between the orthographic projection of the metal ring on the substrate and the orthographic projection of the second metal layer on the substrate.