CN117316926A - Semiconductor structure - Google Patents

Semiconductor structure Download PDF

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Publication number
CN117316926A
CN117316926A CN202210706913.XA CN202210706913A CN117316926A CN 117316926 A CN117316926 A CN 117316926A CN 202210706913 A CN202210706913 A CN 202210706913A CN 117316926 A CN117316926 A CN 117316926A
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China
Prior art keywords
patterns
target patterns
pair
pattern
target
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CN202210706913.XA
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Chinese (zh)
Inventor
彭培修
魏宏谕
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Winbond Electronics Corp
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Winbond Electronics Corp
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Priority to CN202210706913.XA priority Critical patent/CN117316926A/en
Publication of CN117316926A publication Critical patent/CN117316926A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

The invention provides a semiconductor structure, comprising: a plurality of pairs of target patterns, first wires, and second wires. Each pair of target patterns includes a top pattern and a bottom pattern. The first conductive lines are disposed on a first side of the plurality of pairs of target patterns. The first conductive line is electrically connected with the top pattern of the aN+1th pair of target patterns in the plurality of pairs of target patterns, a is a fixed integer greater than or equal to 2, and N is aN integer greater than or equal to 0. The second conductive lines are disposed on a second side of the plurality of pairs of target patterns with respect to the first side. The second conductive line is electrically connected to the bottom pattern of the (aN+1) th pair of target patterns.

Description

Semiconductor structure
Technical Field
The present invention relates to a semiconductor structure.
Background
As the critical dimensions of semiconductor devices are scaled down, photolithography processes are becoming more difficult. In conventional photolithography processes, the method of shrinking critical dimensions includes using optical components with larger numerical apertures (numerical aperture, NA), shorter exposure wavelengths (e.g., EUV), or interface media other than air (e.g., water immersion). As the resolution of conventional photolithography approaches the theoretical limit, the current approach to double patterning approaches has been to overcome the optical limit, thereby increasing the integration density of semiconductor devices.
However, currently, a method for detecting a semiconductor structure after double patterning mostly adopts a spot-test manual visual inspection method. This method not only consumes a lot of manpower but also is not automated and is not amenable to a lot of inspection. Thus, current detection methods still face some challenges.
Disclosure of Invention
The invention provides a semiconductor structure, comprising: a plurality of pairs of target patterns, first wires, and second wires. Each pair of target patterns includes a top pattern and a bottom pattern. The first conductive lines are disposed on a first side of the plurality of pairs of target patterns. The first conductive line is electrically connected with the top pattern of the aN+1th pair of target patterns in the plurality of pairs of target patterns, a is a fixed integer greater than or equal to 2, and N is aN integer greater than or equal to 0. The second conductive lines are disposed on a second side of the plurality of pairs of target patterns with respect to the first side. The second conductive line is electrically connected to the bottom pattern of the (aN+1) th pair of target patterns.
The invention provides a semiconductor structure, comprising: a plurality of pairs of target patterns, first wires, and second wires. Each pair of target patterns includes a top pattern and a bottom pattern. The first conductive lines are disposed on a first side of the plurality of pairs of target patterns. The first conductive line is electrically connected with the top pattern of the aN+2 pairs of target patterns in the pairs of target patterns, a is a fixed integer greater than or equal to 2, and N is aN integer greater than or equal to 0. The second conductive lines are disposed on a second side of the plurality of pairs of target patterns with respect to the first side. The second conductive line is electrically connected to the bottom pattern of the (aN+1) th pair of target patterns.
Based on the above, in the embodiment of the invention, the first conductive line is electrically connected to the top pattern of the (an+1) th pair of target patterns among the plurality of pairs of target patterns, wherein a is a fixed integer greater than or equal to 2 and N is aN integer greater than or equal to 0. In addition, the second conducting wire is electrically connected with the bottom pattern of the (aN+1) th pair of target patterns in the plurality of pairs of target patterns. In this case, the uniformity of the core pattern structure can be detected by electrically detecting the core capacitance and/or the gap capacitance, so as to ensure the stability of the semiconductor process and the quality of the semiconductor wafer. In addition, the method for electrically inspecting semiconductor structures can automatically inspect semiconductor structures in large quantities, so that the yield is effectively improved and the yield is increased.
In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a schematic top view of a semiconductor wafer according to one embodiment of the present invention;
fig. 2A to 2F are schematic perspective views illustrating a manufacturing process of a semiconductor structure according to an embodiment of the invention;
fig. 3A to 3C are schematic top views of a semiconductor structure according to a first embodiment of the present invention;
fig. 4A and fig. 4B are schematic top views of a semiconductor structure according to a second embodiment of the invention;
fig. 5A and 5B are schematic top views of a semiconductor structure according to a third embodiment of the present invention;
fig. 6 is a schematic top view of a semiconductor structure according to a fourth embodiment of the present invention.
Detailed Description
The present invention will be described more fully with reference to the accompanying drawings of this embodiment. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The thickness of layers and regions in the drawings are exaggerated for clarity. The same or similar components are denoted by the same or similar components, and the following paragraphs will not be repeated.
Fig. 1 is a schematic top view of a semiconductor wafer according to an embodiment of the invention.
Referring to fig. 1, a semiconductor wafer 10 is provided in accordance with an embodiment of the present invention. In detail, the semiconductor wafer 10 has a plurality of dies 12, test pads 14, and test keys (test keys) 16. In some embodiments, the test pads 14 and the test keys 16 are arranged in alternating fashion in dicing lanes 18 between the die 12. The test pad 14 can be electrically connected to the test key 16 to measure the electrical property of the test key 16, thereby ensuring the stability of the semiconductor process and the quality of the semiconductor wafer, and further improving the yield. In some embodiments, wafer acceptance testing (wafer acceptable test, WAT) may be performed on the test pads 14 to test the quality of the semiconductor wafer 10.
Fig. 2A to 2F are schematic perspective views illustrating a manufacturing process of a semiconductor structure according to an embodiment of the invention.
In the present embodiment, a Self-aligned double patterning (SADP) method is taken as an example to describe the manufacturing process of the semiconductor structure, but the invention is not limited thereto. In other embodiments, a Self-aligned quad patterning (Self-Aligning Quadruple Patterning, SAQP) method may also be used to form the semiconductor structure to increase the layout density (or pattern density) of the semiconductor structure, thereby achieving a more flexible layout design. Additionally, in some embodiments, the semiconductor structure may include contacts for memory devices, landing pads, capacitors, buried word line structures, active areas for Dynamic Random Access Memory (DRAM), or a combination thereof.
Referring to fig. 2A, first, a target layer 102 is formed on a substrate 100. In some embodiments, the target layer 102 may be a polysilicon layer that may be used as a contact for a memory device. However, the present invention is not limited thereto, and in other embodiments, the target layer 102 may be a metal layer (e.g. tungsten layer), a silicon substrate, a dielectric layer, or a combination thereof.
Then, a core pattern 104 and a mask pattern 106 are sequentially formed on the target layer 102. In one embodiment, the material of the core pattern 104 may include a dielectric material, such as Tetraethoxysilane (TEOS), silicon oxide, or a combination thereof. In one embodiment, the mask pattern 106 may include a single layer structure or a multi-layer structure. For example, the mask pattern 106 may include a carbide layer and an anti-reflective layer on the carbide layer. The material of the carbide layer may include spin-on-carbon (SoC); and the material of the anti-reflection layer may include silicon oxynitride. As shown in fig. 2A, the core pattern 104 and the mask pattern 106 may have the same width. That is, the sidewalls of the core pattern 104 may be aligned with the sidewalls of the mask pattern 106. The width 104w of the core patterns 104 and/or the spacing 104p between adjacent core patterns 104 can be adjusted according to requirements, which is not limited to the present invention.
Referring to fig. 2B, a spacer material 108 is formed on the target layer 102, the core pattern 104 and the mask pattern 106. In detail, the spacer material 108 conformally covers the surfaces of the target layer 102, the core pattern 104, and the mask pattern 106. In one embodiment, the spacer material 108 may be a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.
Referring to fig. 2B and 2C, a portion of the spacer material 108 is removed to form spacers 118 on sidewalls of the core pattern 104 and sidewalls of the mask pattern 106. In one embodiment, the spacer material 108 on the top surface of the mask pattern 106 and on the top surface of the target layer 102 may be removed by an anisotropic etching process, such as a Reactive Ion Etching (RIE), thereby forming the spacers 118.
Referring to fig. 2D, the mask pattern 106 and the core pattern 104 are removed to form an opening 114 between the spacers 118. The opening 114 exposes the top surface of the target layer 102. In this case, as shown in fig. 2D, the opening 114 between the pair of spacers 118 can be regarded as the core opening 114; the openings 116 between adjacent pairs of spacers 118 may be referred to as the gap openings 116.
Referring to fig. 2D and 2E, a portion of the target layer 102 is removed using the spacer 118 as a mask, thereby forming a target pattern 112. In one embodiment, the target layer 102 not covered by the spacers 118 may be removed by an anisotropic etching process (e.g., RIE), thereby forming the target pattern 112.
Referring to fig. 2E and 2F, the spacers 118 are removed to leave the target pattern 112 on the substrate 100. In detail, as shown in fig. 2F, each pair of target patterns 112 has a core opening 114 therebetween; and adjacent pairs of target patterns 112 have gap openings 116 therebetween. In this embodiment, the layout density (or pattern density) of the target pattern 112 may be greater than the layout density (or pattern density) of the core pattern 104. That is, after the self-aligned double patterning (SADP) method of the present embodiment, the layout density (or pattern density) of the semiconductor structure can be increased or decreased to achieve a more flexible layout design.
In addition, the present embodiment can detect the uniformity of the structure of the core pattern 104 by measuring the core capacitance of the target pattern 112 on both sides of the core opening 114 or measuring the gap capacitance of the target pattern 112 on both sides of the gap opening 116. This structural uniformity may generally refer to the width 104w of the core pattern 104 and/or the spacing 104p between adjacent core patterns 104 in fig. 2A. How to measure the core capacitance of the target patterns 112 on both sides of the core opening 114 or the gap capacitance of the target patterns 112 on both sides of the gap opening 116 will be described in detail below.
Fig. 3A to 3C are schematic top views of a semiconductor structure according to a first embodiment of the present invention. In the present embodiment, the semiconductor structures 200a, 200b, 200c may be disposed in the test key 16 of fig. 1, and the electrical properties of the semiconductor structures 200a, 200b, 200c are measured by the test pads 14 electrically connected to the test key 16.
Referring to fig. 3A, the semiconductor structure 200a includes a plurality of pairs of target patterns 212. Each pair of target patterns 212 may include a top pattern 212T and a bottom pattern 212B. The top pattern 212T and the bottom pattern 212B have a core opening 114a therebetween; and adjacent pairs of target patterns 212 have gap openings 116a therebetween. In one embodiment, the target pattern 212 is formed by the SADP process described in fig. 2A-2F. Thus, the location of the core opening 114a may correspond to the location of the core pattern 204 a. Since the core pattern 204a does not actually exist in fig. 3A, it is indicated by a dotted line.
It should be noted that, in the present embodiment, the target patterns 212 may be electrically connected to the conductive lines 220 and 230, respectively, to measure the capacitance between the target patterns 212, thereby detecting the uniformity of the structure of the core pattern 204 a. Specifically, as shown in fig. 3A, the conductive line 220 may be disposed on the first side of the target pattern 212 and electrically connected to the top pattern 212T through the contact window 225. In one embodiment, the conductive wire 220 includes a main body 220b and a plurality of extension portions 220e connected to the main body 220 b. From the upper view of fig. 3A, the extension 220e extends from the sidewall of the body 220b and covers a portion of the top pattern 212T. The contact 225 is vertically disposed between the extension 220e and the top pattern 212T to couple the extension 220e and the top pattern 212T. Similarly, the conductive line 230 may be disposed on a second side of the target pattern 212 opposite to the first side and electrically connected to the bottom pattern 212B through the contact window 325. In one embodiment, the wire 230 includes a main body 230b and a plurality of extension portions 230e connected to the main body 230 b. The extension 230e extends from the sidewall of the body 230B and covers a portion of the bottom pattern 212B as seen in the upper view of fig. 3A. The contact window 235 is vertically disposed between the extension portion 230e and the bottom pattern 212B to couple the extension portion 230e and the bottom pattern 212B.
In the present embodiment, during electrical detection, a voltage V1 (e.g., 2V) may be applied to the conductive line 220, and a voltage V2 (e.g., 0V or ground) different from the voltage V1 may be applied to the conductive line 230. In this case, the plurality of extensions 220e and the plurality of extensions 230e, which are staggered, may measure the core capacitance value C1 between the top pattern 212T and the bottom pattern 212B, and may measure the gap capacitance value G1 between adjacent pairs of the target patterns 212.
Referring to fig. 3B, basically, the semiconductor structure 200B is similar to the semiconductor structure 200 a. The two are different in that: the width of the core pattern 204b of the semiconductor structure 200b is smaller than the width of the core pattern 204a of the semiconductor structure 200 a. That is, the width of the core opening 114b of the semiconductor structure 200b is smaller than the width of the core opening 114a of the semiconductor structure 200 a; and the width of the gap opening 116b of the semiconductor structure 200b is greater than the width of the gap opening 116a of the semiconductor structure 200 a. In this embodiment, the core capacitance value C2 between the top pattern 212T and the bottom pattern 212B of the semiconductor structure 200B is increased to be greater than the core capacitance value C1 of the semiconductor structure 200 a; the gap capacitance G2 between adjacent pairs of target patterns 212 of the semiconductor structure 200b is reduced to be smaller than the gap capacitance G1 of the semiconductor structure 200 a.
Since the core capacitance C2 increases and the gap capacitance G2 decreases accordingly, the total capacitance of the semiconductor structure 200b may be substantially equal to the total capacitance of the semiconductor structure 200 a. In this case, the electrical inspection does not substantially detect the structural uniformity of the core pattern.
Similarly, as shown in fig. 3C, the width of the core pattern 204C of the semiconductor structure 200C is greater than the width of the core pattern 204a of the semiconductor structure 200 a. That is, the width of the core opening 114c of the semiconductor structure 200c is greater than the width of the core opening 114a of the semiconductor structure 200 a; and the width of the gap opening 116c of the semiconductor structure 200c is smaller than the width of the gap opening 116a of the semiconductor structure 200 a. In this embodiment, the core capacitance value C3 between the top pattern 212T and the bottom pattern 212B of the semiconductor structure 200C is reduced to be smaller than the core capacitance value C1 of the semiconductor structure 200 a; the gap capacitance G3 between the adjacent pairs of target patterns 212 of the semiconductor structure 200c is increased to be greater than the gap capacitance G1 of the semiconductor structure 200 a. Since the core capacitance C3 decreases and the gap capacitance G3 increases accordingly, the total capacitance of the semiconductor structure 200C may be substantially equal to the total capacitance of the semiconductor structure 200 a. In this case, the electrical inspection does not substantially detect the structural uniformity of the core pattern.
Fig. 4A and fig. 4B are schematic top views of a semiconductor structure according to a second embodiment of the present invention. In the present embodiment, the semiconductor structures 300a, 300b may be disposed in the test key 16 of fig. 1, and the electrical properties of the semiconductor structures 300a, 300b are measured by the test pads 14 electrically connected to the test key 16.
Referring to fig. 4A, a semiconductor structure 300a is substantially similar to semiconductor structure 200 b. The two are different in that: the configuration of the wires 320, 330 of the semiconductor structure 300a is different from the configuration of the wires 220, 230 of the semiconductor structure 200 b. Specifically, the conductive lines 320 are disposed on a first side of the target pattern 212, and the conductive lines 330 are disposed on a second side of the target pattern 212 opposite the first side. From the top view of fig. 4A, the wire 320 (which may be considered as a first wire) includes a main body portion 320b and a plurality of extension portions 320e. The plurality of extension portions 320e extend from sidewalls of the body portion 320b, respectively, and cover the corresponding top patterns 212T. In addition, the wire 330 (may be regarded as a second wire) includes a main body portion 330b and a plurality of extension portions 330e. The plurality of extension portions 330e extend from the sidewalls of the main body portion 330B, respectively, and cover the corresponding bottom patterns 212B.
In the present embodiment, the conductive line 320 electrically connects the top pattern 212T of the 1 st pair of target patterns 212-1 and the top pattern 212T of the 3 rd pair of target patterns 212-3 in the target patterns 212; and the 2 nd pair of target patterns 212-2 and the 4 th pair of target patterns 212-4 are not electrically connected. That is, the conductive line 320 may be electrically connected to the top pattern 212t of the (an+1) th pair of target patterns 212, a being a fixed integer greater than or equal to 2 and N being aN integer greater than or equal to 0. In some embodiments, when a is 2, the conductive line 320 may electrically connect the top patterns 212T of the 1 st pair of target patterns, the top patterns 212T of the 3 rd pair of target patterns, and the top patterns 212T of the 5 th pair of target patterns to the top patterns 212T of the 2n+1 st pair of target patterns in the plurality of pairs of target patterns 212.
On the other hand, the conductive line 330 may electrically connect the bottom pattern 212B of the 1 st pair of target patterns 212-1 and the bottom pattern 212B of the 3 rd pair of target patterns 212-3 in the target patterns 212; and the 2 nd pair of target patterns 212-2 and the 4 th pair of target patterns 212-4 are not electrically connected. That is, the conductive line 330 is electrically connected to the bottom pattern 212b of the (an+1) th pair of target patterns among the plurality of pairs of target patterns, a is a fixed integer greater than or equal to 2 and N is aN integer greater than or equal to 0. In some embodiments, when a is 2, the conductive line 330 may electrically connect the bottom patterns 212B of the 1 st pair of target patterns, the bottom patterns 212B of the 3 rd pair of target patterns, the bottom patterns 212B of the 5 th pair of target patterns, and the bottom patterns 212B of the 2n+1 st pair of target patterns in the plurality of pairs of target patterns 212.
From another perspective, the extension portions 320e and 330e are electrically connected to the top patterns 212T and the bottom patterns 212B on both sides of the core pattern 304-1 and the core pattern 304-3 through the contact windows 325 and 335, respectively; but not to the top pattern 212T and the bottom pattern 212B on both sides of the core pattern 304-2 and the core pattern 304-4. That is, the extension portions 320e and 330e are electrically connected to the top pattern 212T and the bottom pattern 212b on both sides of the (an+1) th core pattern, respectively, a is a fixed integer greater than or equal to 2 and N is aN integer greater than or equal to 0. In some embodiments, when a is 2, the conductive lines 320, 330 may electrically connect the top patterns 212T and the bottom patterns 212B on both sides of the 1 st core pattern, the top patterns 212T and the bottom patterns 212B on both sides of the 3 rd core pattern, the top patterns 212T and the bottom patterns 212B on both sides of the 5 th core pattern, and the top patterns 212T and the bottom patterns 212B on both sides of the 2n+1 th core pattern.
In the present embodiment, during electrical detection, a voltage V1 (e.g., 2V) may be applied to the conductive line 320, and a voltage V2 (e.g., 0V or ground) different from the voltage V1 may be applied to the conductive line 330. In this case, the plurality of extending portions 320e and the plurality of extending portions 330e are configured alternately to measure the core capacitance value C4 of the 1 st pair of target patterns 212-1 and the core capacitance value C4 of the 3 rd pair of target patterns 212-3. It is noted that the distance W1 between the 1 st pair of target patterns 212-1 and the 3 rd pair of target patterns 212-3 is approximately equal to the sum of the widths 116W of the two gap openings 116B, the width 114W of one core opening 114B, the width 212Tw of one top pattern 212T, and the width 212Bw of one bottom pattern 212B. In this case, the gap capacitance value between the 1 st pair of target patterns 212-1 and the 3 rd pair of target patterns 212-3 is negligibly small due to the too large distance W1. Thus, the total capacitance of the semiconductor structure 300a may be substantially equal to the core capacitance C4. In this embodiment, the uniformity of the structure of the core pattern 304 can be detected by electrically detecting the core capacitance value C4. That is, the variation of the width 304w of the core pattern 304 and/or the variation of the pitch 304p between the neighboring core patterns 304 may be detected by electrically detecting the resulting core capacitance value C4. For example, as the core capacitance value C4 becomes larger, it is presumed that the width 304w of the core pattern 304 may become smaller. In this case, the structure of the different target pattern 212 may be inspected on-line (in-line) to ensure the stability of the semiconductor process and the quality of the semiconductor wafer. In addition, the method for electrically inspecting semiconductor structures can automatically inspect a large number of semiconductor structures, thereby effectively improving the yield and increasing the yield.
Referring to fig. 4B, semiconductor structure 300B is substantially similar to semiconductor structure 300 a. The two are different in that: the configuration of the conductive lines 320, 330 of the semiconductor structure 300b is different. Specifically, the conductive line 320 electrically connects the top pattern 212T of the 1 st pair of target patterns 212-1 and the top pattern 212T of the 4 th pair of target patterns 212-4 in the target patterns 212. That is, the conductive line 320 is electrically connected to the top pattern 212t of the (an+1) th pair of target patterns 212, a is a fixed integer greater than or equal to 3 and N is aN integer greater than or equal to 0. In some embodiments, when a is 3, the conductive line 320 may electrically connect the bottom patterns 212B of the 1 st pair of target patterns, the bottom patterns 212B of the 4 th pair of target patterns, the bottom patterns 212B of the 7 th pair of target patterns, and the bottom patterns 212B of the 3n+1 th pair of target patterns in the plurality of pairs of target patterns 212.
On the other hand, the conductive line 330 electrically connects the bottom pattern 212B of the 1 st pair of target patterns 212-1 and the bottom pattern 212B of the 4 th pair of target patterns 212-4 in the target patterns 212. That is, the conductive line 330 is electrically connected to the bottom pattern 212b of the (an+1) th pair of the target patterns, a is a fixed integer greater than or equal to 3 and N is aN integer greater than or equal to 0. In some embodiments, when a is 3, the conductive line 330 may electrically connect the bottom patterns 212B of the 1 st pair of target patterns, the bottom patterns 212B of the 4 th pair of target patterns, the bottom patterns 212B of the 7 th pair of target patterns, and the bottom patterns 212B of the 3n+1 th pair of target patterns in the plurality of pairs of target patterns 212.
It is noted that the distance W2 between the 1 st pair of target patterns 212-1 and the 4 th pair of target patterns 212-4 is approximately equal to the sum of the widths 116W of the three gap openings 116B, the widths 114W of the two core openings 114B, the widths 212Tw of the two top patterns 212T, and the widths 212Bw of the two bottom patterns 212B. In this case, the gap capacitance value between the 1 st pair of target patterns 212-1 and the 4 th pair of target patterns 212-4 is negligibly small due to the too large distance W2. Thus, the total capacitance of the semiconductor structure 300b may be substantially equal to the core capacitance C5. In this embodiment, the uniformity of the structure of the core pattern 304 can be detected by electrically detecting the core capacitance value C5. That is, the variation of the width 304w of the core pattern 304 and/or the variation of the pitch 304p between the neighboring core patterns 304 may be detected by electrically detecting the resulting core capacitance value C5.
Fig. 5A and 5B are schematic top views of a semiconductor structure according to a third embodiment of the present invention. In the present embodiment, the semiconductor structures 400a, 400b may be disposed in the test key 16 of fig. 1, and the electrical properties of the semiconductor structures 400a, 400b are measured by the test pads 14 electrically connected to the test key 16.
Basically, semiconductor structure 400a is similar to semiconductor structure 200 b. The two are different in that: the configuration of the wires 420, 430 of the semiconductor structure 400a is different from the configuration of the wires 220, 230 of the semiconductor structure 200 b. Specifically, the conductive lines 420 are disposed on a first side of the target pattern 212, and the conductive lines 430 are disposed on a second side of the target pattern 212 opposite the first side. From the top view of fig. 5A, the wire 420 (which may be considered a first wire) includes a main body portion 420b and a plurality of extension portions 420e. The plurality of extension portions 420e extend from the sidewalls of the main body portion 420b, respectively, and cover the corresponding top patterns 212T. In addition, the wire 430 (which may be regarded as a second wire) includes a main body portion 430b and a plurality of extension portions 430e. The plurality of extension portions 430e extend from sidewalls of the body portion 430B, respectively, and cover the corresponding bottom pattern 212B.
In the present embodiment, the conductive line 420 electrically connects the top pattern 212T of the 2 nd pair of target patterns 212-2 and the top pattern 212T of the 4 th pair of target patterns 212-4 in the target patterns 212. That is, the conductive line 420 is electrically connected to the top pattern 212t of the (an+2) th pair of target patterns 212, a is a fixed integer greater than or equal to 2 and N is aN integer greater than or equal to 0. In some embodiments, when a is 2, the conductive line 420 may electrically connect the top patterns 212T of the 2 nd pair of target patterns, the top patterns 212T of the 4 th pair of target patterns, and the top patterns 212T of the 6 th pair of target patterns to the top patterns 212T of the 2n+2 th pair of target patterns in the plurality of pairs of target patterns 212.
On the other hand, the conductive line 430 electrically connects the bottom pattern 212B of the 1 st pair of target patterns 212-1 and the bottom pattern 212B of the 3 rd pair of target patterns 212-3 in the target patterns 212. That is, the conductive line 430 is electrically connected to the bottom pattern 212b of the (an+1) th pair of the target patterns, a is a fixed integer greater than or equal to 2 and N is aN integer greater than or equal to 0. In some embodiments, when a is 2, the conductive line 430 may electrically connect the bottom patterns 212B of the 1 st pair of target patterns, the bottom patterns 212B of the 3 rd pair of target patterns, the bottom patterns 212B of the 5 th pair of target patterns, and the bottom patterns 212B of the 2n+1 st pair of target patterns in the plurality of pairs of target patterns 212.
In the present embodiment, during electrical detection, a voltage V1 (e.g., 2V) may be applied to the conductive line 420, and a voltage V2 (e.g., 0V or ground) different from the voltage V1 may be applied to the conductive line 430. In this case, the plurality of extending portions 420e and the plurality of extending portions 430e which are staggered may measure the gap capacitance value G4 between the 1 st pair of target patterns 212-1 and 2 nd pair of target patterns 212-2, and measure the gap capacitance value G4 between the 3 rd pair of target patterns 212-3 and 4 th pair of target patterns 212-4.
It is noted that the distance W3 between the top pattern 212T of the 2 nd pair of target patterns 212-2 and the bottom pattern 212B of the 3 rd pair of target patterns 212-3 is approximately equal to the sum of the widths 114W of the two core openings 114B, the width 116W of one gap opening 116B, the width 212Tw of one top pattern 212T, and the width 212Bw of one bottom pattern 212B. In this case, the core capacitance values of the 2 nd pair of target patterns 212-2 and the 3 rd pair of target patterns 212-3 are negligibly small due to the too large distance W3. Accordingly, the total capacitance of the semiconductor structure 400a may be substantially equal to the gap capacitance G4. In this embodiment, the uniformity of the structure of the core pattern 404 can be detected by electrically detecting the gap capacitance G4. That is, a change in the width 404w of the core pattern 404 and/or a change in the pitch 404p between adjacent core patterns 404 may be detected by electrically detecting the resulting gap capacitance value G4. For example, as the gap capacitance value G4 becomes larger, it is presumed that the pitch 404p between the adjacent core patterns 404 may become smaller. In this case, the structure of the different target pattern 212 may be inspected on-line (in-line) to ensure the stability of the semiconductor process and the quality of the semiconductor wafer. In addition, the method for electrically inspecting semiconductor structures can automatically inspect a large number of semiconductor structures, thereby effectively improving the yield and increasing the yield.
Referring to fig. 5B, semiconductor structure 400B is substantially similar to semiconductor structure 400 a. The two are different in that: the configuration of the conductive lines 420, 430 of the semiconductor structure 400b is different. Specifically, the conductive line 420 electrically connects the top pattern 212T of the 2 nd pair of target patterns 212-2 and the top pattern 212T of the 5 th pair of target patterns 212-5 in the target patterns 212. That is, the conductive line 420 is electrically connected to the top pattern 212t of the (an+2) th pair of target patterns 212, a is a fixed integer greater than or equal to 3 and N is aN integer greater than or equal to 0. In some embodiments, when a is 3, the conductive line 420 may electrically connect the bottom patterns 212B of the 2 nd pair of target patterns, the bottom patterns 212B of the 5 th pair of target patterns, the bottom patterns 212B of the 8 th pair of target patterns, and the bottom patterns 212B of the 3n+2 th pair of target patterns in the plurality of pairs of target patterns 212.
On the other hand, the conductive line 430 electrically connects the bottom pattern 212B of the 1 st pair of the target patterns 212-1 and the bottom pattern 212B of the 4 th pair of the target patterns 212-4 in the target patterns 212. That is, the conductive line 430 is electrically connected to the bottom pattern 212b of the (an+1) th pair of the target patterns, a is a fixed integer greater than or equal to 3 and N is aN integer greater than or equal to 0. In some embodiments, when a is 3, the conductive line 430 may electrically connect the bottom patterns 212B of the 1 st pair of target patterns, the bottom patterns 212B of the 4 th pair of target patterns, the bottom patterns 212B of the 7 th pair of target patterns, and the bottom patterns 212B of the 3n+1 th pair of target patterns in the plurality of pairs of target patterns 212.
It is noted that the distance W4 between the top pattern 212T of the 2 nd pair of target patterns 212-2 and the bottom pattern 212B of the 4 th pair of target patterns 212-4 is approximately equal to the sum of the widths 116W of the two gap openings 116B, the widths 114W of the three core openings 114B, the widths 212Tw of the two top patterns 212T, and the widths 212Bw of the two bottom patterns 212B. In this case, the core capacitance values of the 2 nd pair of target patterns 212-2, the 3 rd pair of target patterns 212-3, and the 4 th pair of target patterns 212-4 are negligibly small due to the too large distance W4. Accordingly, the total capacitance of the semiconductor structure 400b may be substantially equal to the gap capacitance G5. In this embodiment, the variation of the width 404w of the core pattern 404 and/or the variation of the pitch 404p between the adjacent core patterns 404 may be detected by electrically detecting the resulting gap capacitance value G5.
Fig. 6 is a schematic top view of a semiconductor structure according to a fourth embodiment of the present invention. In this embodiment, the semiconductor structure 500 may be disposed in the test key 16 of fig. 1, and the electrical property of the semiconductor structure 500 is measured by the test pad 14 electrically connected to the test key 16.
Referring to fig. 6, basically, a semiconductor structure 500 is a structure obtained by combining the semiconductor structure 300a of fig. 4A and the semiconductor structure 400a of fig. 5A. In one embodiment, semiconductor structure 300a and semiconductor structure 400a share conductive line 520. Specifically, the wire 520 includes a main body 520b, a plurality of extensions 330e, and a plurality of extensions 430e. The extension portions 330e extend from the first sidewalls of the main body portion 520B, respectively, and cover the corresponding bottom patterns 212B; and the extension portions 430e extend from the second sidewalls of the body portion 520b and cover the corresponding top patterns 212T, respectively. The extending portions 330e and the extending portions 430e are staggered with each other. In the present embodiment, the semiconductor structure 500 can save the chip area due to the sharing of the conductive lines 520. However, the present invention is not limited thereto, and in other embodiments, the conductive line 520 may not be shared, and the semiconductor structure 300a of fig. 4A and the semiconductor structure 400a of fig. 5A may be arranged side by side.
In summary, in the embodiment of the present invention, the first conductive line is electrically connected to the top pattern of the (an+1) th pair of target patterns among the plurality of pairs of target patterns, wherein a is a fixed integer greater than or equal to 2 and N is aN integer greater than or equal to 0. In addition, the second conducting wire is electrically connected with the bottom pattern of the (aN+1) th pair of target patterns in the plurality of pairs of target patterns. In this case, the uniformity of the core pattern structure can be detected by electrically detecting the core capacitance and/or the gap capacitance, so as to ensure the stability of the semiconductor process and the quality of the semiconductor wafer. In addition, the method for electrically inspecting semiconductor structures can automatically inspect semiconductor structures in large quantities, so that the yield is effectively improved and the yield is increased.
Although the invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather may be modified or altered somewhat by persons skilled in the art without departing from the spirit and scope of the invention.

Claims (10)

1. A semiconductor structure, comprising:
a plurality of pairs of target patterns, wherein each pair of target patterns comprises a top pattern and a bottom pattern;
a first conductive line disposed on a first side of the plurality of pairs of target patterns, wherein the first conductive line is electrically connected to a top pattern of aN (n+1) th pair of target patterns among the plurality of pairs of target patterns, a is a fixed integer of 2 or more and N is aN integer of 0 or more; and
and a second conductive line disposed on a second side of the plurality of pairs of target patterns with respect to the first side, wherein the second conductive line is electrically connected to a bottom pattern of the (an+1) th pair of target patterns among the plurality of pairs of target patterns.
2. The semiconductor structure of claim 1, wherein the first conductive line comprises:
a first body portion; and
the first extending parts extend from the side walls of the first main body part respectively and cover the corresponding top patterns, and the first extending parts are electrically connected with the corresponding top patterns through the first contact windows respectively.
3. The semiconductor structure of claim 1, wherein the second conductive line comprises:
a second body portion; and
the second extending parts extend from the side walls of the second main body part respectively and cover the corresponding bottom patterns, and the second extending parts are electrically connected with the corresponding bottom patterns through the second contact windows respectively.
4. The semiconductor structure of claim 1, wherein the first conductive line is configured to provide a first voltage to the top pattern of the an+1-th pair of target patterns of the plurality of pairs of target patterns, and the second conductive line is configured to provide a second voltage, different from the first voltage, to the bottom pattern of the an+1-th pair of target patterns of the plurality of pairs of target patterns, thereby measuring a core capacitance value of the an+1-th pair of target patterns.
5. The semiconductor structure of claim 1, wherein when a is 2, the first conductive line electrically connects the top pattern of the 1 st pair of target patterns, the top pattern of the 3 rd pair of target patterns, the top pattern of the 5 th pair of target patterns to the top pattern of the 2n+1 st pair of target patterns of the plurality of pairs of target patterns, and
the second conductive line is electrically connected to the bottom pattern of the 1 st pair of target patterns, the bottom pattern of the 3 rd pair of target patterns, and the bottom pattern of the 5 th pair of target patterns to the bottom pattern of the 2n+1 st pair of target patterns in the plurality of pairs of target patterns.
6. A semiconductor structure, comprising:
a plurality of pairs of target patterns, wherein each pair of target patterns comprises a top pattern and a bottom pattern;
a first conductive line disposed on a first side of the plurality of pairs of target patterns, wherein the first conductive line is electrically connected to a top pattern of aN (n+2) th pair of target patterns among the plurality of pairs of target patterns, a is a fixed integer of 2 or more and N is aN integer of 0 or more; and
and a second conductive line disposed on a second side of the plurality of pairs of target patterns with respect to the first side, wherein the second conductive line is electrically connected to a bottom pattern of aN (an+1) th pair of target patterns among the plurality of pairs of target patterns.
7. The semiconductor structure of claim 6, wherein the first conductive line comprises:
a first body portion; and
the first extending parts extend from the side walls of the first main body part respectively and cover the corresponding top patterns, and the first extending parts are electrically connected with the corresponding top patterns through the first contact windows respectively.
8. The semiconductor structure of claim 6, wherein the second conductive line comprises:
a second body portion; and
the second extending parts extend from the side walls of the second main body part respectively and cover the corresponding bottom patterns, and the second extending parts are electrically connected with the corresponding bottom patterns through the second contact windows respectively.
9. The semiconductor structure of claim 6, wherein the first conductive line is configured to provide a first voltage to the top pattern of the an+2-th pair of target patterns of the plurality of pairs of target patterns, and the second conductive line is configured to provide a second voltage different from the first voltage to the bottom pattern of the an+1-th pair of target patterns of the plurality of pairs of target patterns, thereby measuring a gap capacitance value between the an+2-th pair of target patterns and the an+1-th pair of target patterns.
10. The semiconductor structure of claim 6, wherein when a is 2, the first conductive line electrically connects the top pattern of the 2 nd pair of target patterns, the top pattern of the 4 th pair of target patterns, the top patterns of the 6 th pair of target patterns to the top patterns of the aN+2 th pair of target patterns, and
the second conductive line is electrically connected with the bottom patterns of the 1 st pair of target patterns, the bottom patterns of the 3 rd pair of target patterns, and the bottom patterns of the 5 th pair of target patterns to the bottom patterns of the aN+1 th pair of target patterns in the plurality of pairs of target patterns.
CN202210706913.XA 2022-06-21 2022-06-21 Semiconductor structure Pending CN117316926A (en)

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