CN117313642A

CN117313642A - Training method, device, equipment and storage medium for lithography mask generation model

Info

Publication number: CN117313642A
Application number: CN202210673969.XA
Authority: CN
Inventors: 马星宇; 郝少刚; 张胜誉
Original assignee: Tencent Technology Shenzhen Co Ltd
Current assignee: Tencent Technology Shenzhen Co Ltd
Priority date: 2022-06-14
Filing date: 2022-06-14
Publication date: 2023-12-29

Abstract

The embodiment of the application provides a training method, device and equipment for a lithography mask generation model and a storage medium, and relates to the technical field of chip and machine learning. The method comprises the following steps: obtaining a prediction mask map corresponding to each of a plurality of chip layouts; determining the prediction difficulty of each chip layout based on the prediction mask map corresponding to each chip layout; selecting a chip layout with the prediction difficulty meeting the condition from a plurality of chip layouts as a difficult chip layout; and training the first lithography mask generation model by adopting the difficult chip layout to obtain a trained first lithography mask generation model. According to the technical scheme provided by the embodiment of the application, the number of chip layouts required for training the photoetching mask generation model is reduced, and the training cost of the model is saved.

Description

Training method, device, equipment and storage medium for lithography mask generation model

Technical Field

The embodiment of the application relates to the technical field of chip and machine learning, in particular to a training method, device, equipment and storage medium of a lithography mask generation model.

Background

In the chip production process, mask patterns corresponding to all chip layouts are required to be obtained for photoetching process exposure.

In the related art, more chip layouts are required to be used as training data for training the lithography mask generation model, so that the lithography mask generation model with higher precision can be obtained.

In the related art, more chip layouts are required to train the lithography mask to generate the model, and a certain cost is required for each chip layout, so that the cost required in the training process of the model is higher.

Disclosure of Invention

The embodiment of the application provides a training method, device and equipment for a lithography mask generation model and a storage medium, which can reduce the number of chip layouts required for training the lithography mask generation model and save the training cost of the model. The technical scheme is as follows:

according to an aspect of an embodiment of the present application, there is provided a training method of a lithographic mask generation model, the method including:

obtaining a prediction mask map corresponding to each of a plurality of chip layouts;

determining the prediction difficulty of each chip layout based on the prediction mask map corresponding to each chip layout;

Selecting the chip layout with the prediction difficulty meeting the condition from the plurality of chip layouts as a difficult chip layout;

and updating and training the initially trained first lithography mask generation model by adopting the difficult chip layout to obtain a trained and updated first lithography mask generation model.

According to an aspect of an embodiment of the present application, there is provided a training apparatus for generating a model of a lithographic mask, the apparatus including:

the mask acquisition module is used for acquiring prediction mask graphs corresponding to the chip layouts respectively;

the difficulty determining module is used for determining the prediction difficulty corresponding to each chip layout based on the prediction mask map corresponding to each chip layout;

the layout selection module is used for selecting the chip layout with the prediction difficulty meeting the condition from the plurality of chip layouts as a difficult chip layout;

and the model updating module is used for updating and training the first lithography mask generating model after the preliminary training by adopting the difficult chip layout to obtain a first lithography mask generating model after the training and updating.

According to an aspect of an embodiment of the present application, there is provided a computer apparatus including a processor and a memory, the memory storing a computer program loaded and executed by the processor to implement the above-described training method of a lithographic mask generation model.

According to an aspect of embodiments of the present application, there is provided a computer readable storage medium having stored therein a computer program loaded and executed by a processor to implement the above-described training method of a lithographic mask generation model.

According to one aspect of embodiments of the present application, there is provided a computer program product comprising a computer program stored in a computer readable storage medium. A processor of a computer apparatus reads the computer program from a computer-readable storage medium, and the processor executes the computer program to cause the computer apparatus to perform the above-described training method of a lithographic mask generation model.

The technical scheme provided by the embodiment of the application can comprise the following beneficial effects:

because the difficult chip layout can rapidly improve the model precision of the lithography mask generation model, the number of chip layouts required for training the lithography mask generation model can be reduced by selecting the difficult chip layout and updating the lithography mask generation model by adopting the difficult chip layout, thereby saving the data marking cost and further saving the model training cost.

In addition, the model accuracy of the lithography mask generation model can be improved relatively quickly by training the difficult chip layout, so that the time required by model training is saved, and the training efficiency of the model is improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

FIG. 1 is a flow chart of a method for training a lithographic mask generation model provided in one embodiment of the present application;

FIG. 2 is a schematic illustration of an implementation environment provided by one embodiment of the present application;

FIG. 3 is a schematic diagram of a lithographic mask generation model provided in one embodiment of the present application;

FIG. 4 is a flowchart of a method for training a lithographic mask generation model provided in accordance with another embodiment of the present application;

FIG. 5 is a flowchart of a method for training a lithographic mask generation model provided in accordance with another embodiment of the present application;

FIG. 6 is a flowchart of a method for training a lithographic mask generation model provided in accordance with another embodiment of the present application;

FIG. 7 is a flowchart of a method for training a lithographic mask generation model provided in accordance with another embodiment of the present application;

FIG. 8 is a flowchart of a method for training a lithographic mask generation model provided in accordance with another embodiment of the present application;

FIG. 9 is a block diagram of a training apparatus for a lithographic mask generation model provided in one embodiment of the present application;

FIG. 10 is a block diagram of a training apparatus for a lithographic mask generation model provided in one embodiment of the present application;

FIG. 11 is a block diagram of a computer device provided in one embodiment of the present application.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of methods that are consistent with some aspects of the present application as detailed in the accompanying claims.

First, some terms involved in the present application will be described.

Chip layout: and can also be called as an integrated circuit layout, which is a planar geometry description of the physical condition of a real integrated circuit. An integrated circuit layout is the result of the physical design of the lowest level steps in the integrated circuit design. The physical design converts the result of logic synthesis into a layout file through a layout and wiring technology. The file contains the shape, area and location information of each hardware unit on the chip.

Optical proximity correction (optical proximity correction, OPC): the calculation method is used for correcting the graph on the mask plate, so that the graph projected onto the photoresist meets the design requirement as much as possible, and the method is a photoetching resolution enhancement technology. In the photolithography process, a pattern on a mask is projected on a photoresist by an exposure system, and the pattern on the photoresist and the pattern on the mask are not completely identical due to imperfections and diffraction effects of an optical system. These distortions, if not corrected, can greatly alter the electrical performance of the produced circuit. Optical proximity correction is a technique that enables imaging results in photoresist to be as close as possible to the mask pattern by adjusting the topology of the pattern of the light-transmitting region on the photolithographic mask, or adding fine sub-resolution auxiliary patterns on the mask. OPC is also a technique that compensates for degradation in the imaging quality of a lithography system by varying the amplitude of the transmitted light through a mask. OPC is mainly used in the production process of semiconductor devices.

And (3) photoetching mask: the mask is a masking film of light which acts like a photo, and through the mask, a portion of the light agent "under" the mask is sensitized to be insoluble in the organic drug and a portion of the light agent is not sensitized to be soluble in the organic drug, thereby producing the desired pattern. In the fabrication of planar transistors and integrated circuits, multiple photolithography is required. For this purpose, a set of photolithographic masks must be prepared having a specific geometry. The method is to prepare the mask pattern with required size and precision according to the geometric figure required by the parameters of the transistor and the integrated circuit, and repeatedly arrange the pattern on the mask substrate with a certain interval and layout, thereby producing the lithography mask in batch for exposure of the lithography process.

Artificial intelligence (Artificial Intelligence, AI) is the theory, method, technique and application system that uses a digital computer or a machine controlled by a digital computer to simulate, extend and extend human intelligence, sense the environment, acquire knowledge and use the knowledge to obtain optimal results. In other words, artificial intelligence is an integrated technology of computer science that attempts to understand the essence of intelligence and to produce a new intelligent machine that can react in a similar way to human intelligence. Artificial intelligence, i.e. research on design principles and implementation methods of various intelligent machines, enables the machines to have functions of sensing, reasoning and decision.

The artificial intelligence technology is a comprehensive subject, and relates to the technology with wide fields, namely the technology with a hardware level and the technology with a software level. Artificial intelligence infrastructure technologies generally include technologies such as sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, big data processing technologies, operation/interaction systems, mechatronics, and the like. The artificial intelligence software technology mainly comprises a computer vision technology, a voice processing technology, a natural language processing technology, machine learning/deep learning and other directions.

Machine Learning (ML) is a multi-domain interdisciplinary, involving multiple disciplines such as probability theory, statistics, approximation theory, convex analysis, algorithm complexity theory, etc. It is specially studied how a computer simulates or implements learning behavior of a human to acquire new knowledge or skills, and reorganizes existing knowledge structures to continuously improve own performance. Machine learning is the core of artificial intelligence, a fundamental approach to letting computers have intelligence, which is applied throughout various areas of artificial intelligence. Machine learning and deep learning typically include techniques such as artificial neural networks, confidence networks, reinforcement learning, transfer learning, induction learning, teaching learning, and the like.

According to the embodiment of the application, the machine learning technology is adopted to train the mask generation model, so that the mask generation model can generate a prediction mask map with higher precision, and a mask plate is provided for the subsequent chip lithography process.

The method provided by the embodiment of the application can be also applied to other links of integrated circuit design, such as chip logic circuit simulation, chip heat transport simulation, chip performance detection, chip dead spot detection, light source-mask collaborative optimization and other EDA (Electronic design automation ) fields.

Fig. 1 of the present application provides two training methods for generating a model by using a photolithography mask.

(1) Training method based on error reduction sampling strategy, as shown in fig. 1 (a), the method at least comprises the following steps (steps 11 to 13):

step 11, performing preliminary training on a photomask generating model by taking some marked chip layouts as marked data sets, and performing mask prediction on unmarked chip layouts by adopting the preliminarily trained photomask generating model to obtain predicted mask diagrams of all unmarked chip layouts;

step 12, obtaining wafer patterns of a predictive mask map through a photoetching physical model, determining the prediction difficulty corresponding to each unlabeled chip map based on the difference between the wafer patterns of the predictive mask map and the corresponding unlabeled chip map, and selecting the unlabeled chip map with the largest prediction difficulty as a difficult chip map;

And step 13, obtaining a standard mask map of the difficult chip layout, and adding the difficult chip layout as the marked chip layout into a marked data set to continuously train the photoetching mask to generate a model.

The steps can be circularly executed for a plurality of times, and the precision of generating the model by the photoetching mask is continuously improved.

(2) Training method based on voting inquiry sampling strategy, as shown in fig. 1 (b), the method at least comprises the following steps (step 14-step 16):

step 14, firstly, respectively performing preliminary training on a plurality of preliminary trained lithography mask generation models by taking some marked chip layouts as marked data sets, and then performing mask prediction on unmarked chip layouts by adopting the plurality of preliminary trained lithography mask generation models;

step 15, calculating uncertainty corresponding to each unlabeled chip layout based on a plurality of primarily trained photoetching mask generation models and on prediction mask diagrams generated by each unlabeled chip layout respectively, and selecting the unlabeled chip layout with the largest uncertainty as a difficult chip layout;

and step 16, obtaining a standard mask map of the difficult chip layout, and adding the difficult chip layout as the marked chip layout into a marked data set to continuously train the photoetching mask to generate a model.

Referring to fig. 2, a schematic diagram of an implementation environment provided in one embodiment of the present application is shown. The real-time environment may be implemented as a training system for a lithographic mask generation model. The system 30 may include a model training device 31 and a model use device 32.

Model training device 31 may be an electronic device such as a computer, server, intelligent robot, or some other electronic device with relatively high computing power. The model training device 31 is used for training a photomask generating model 33. In the embodiment of the present application, the mask generating model 33 is a neural network model for generating a predicted mask map, and the model training device 31 may train the mask generating model 33 in a machine learning manner, so that the mask generating model has better performance.

The above-trained lithographic mask generation model 33 may be deployed in the model using apparatus 32 to provide image processing results (i.e., auto-counting results). The model using device 32 may be a terminal device such as a PC (personal computer), a tablet computer, a smart phone, a wearable device, a smart robot, a smart voice interaction device, a smart home appliance, a vehicle-mounted terminal, an aircraft, a medical device, or a server, which is not limited in this application.

In some embodiments, as shown in FIG. 2, the lithography mask generation model 33 may include: an encoder 34 and a decoder 35. As shown in fig. 3, the encoder 34 is an encoder constituted by a convolutional neural network. Taking the number of convolution layers as 8 as an example, after the chip layout is input, through a multi-layer two-dimensional convolution neural network, the 8 convolution layers are respectively composed of 8, 16, 32, 64, 128, 256, 512, 1024 3×3 filters 36, a batch normalization layer 37 is established after each convolution layer, and a modified linear unit (ReLU) is used as an activation function. The final output of the 8-layer convolution described above (dimension (1,1,1024)) is taken as input to decoder 35, which decoder 35 is made up of a multi-layer deconvolution neural network. Taking the example of the number of deconvolution layers of 8, the first 7 convolution layers consist of 1024, 512, 256, 128, 64, 32, 16 3 x 3 filters 36, respectively, after each deconvolution layer a batch normalization layer 37 is built up, and a leak-modified linear unit (leak-ReLU) is used as the activation function. Finally, the deconvolution layer consisting of a 3 x 3 filter 36 and sigmoid activation function 38 gives a mask with dimensions (256, 1) and values of 0 to 1, and then binarizes the mask to obtain the final predicted mask.

Embodiments of the present application may be applied to a variety of scenarios including, but not limited to, chip involvement, cloud technology, artificial intelligence, chip manufacturing, intelligent transportation, assisted driving, and the like.

In the following, the technical solution of the present application will be described by several embodiments.

Referring to FIG. 4, a flowchart of a method for training a lithographic mask generation model is shown, according to another embodiment of the present application. In this embodiment, the method is applied to the model training apparatus described above for illustration. The method may comprise the following steps (401-404):

step 401, obtaining a prediction mask map corresponding to each of the plurality of chip layouts.

In some embodiments, the plurality of chip layouts includes a tagged chip layout. The chip layout with the label refers to a chip layout with a corresponding standard mask map, and the standard mask map is the label of the chip layout with the label.

In some embodiments, the plurality of chip layouts includes unlabeled chip layouts, which refers to chip layouts that do not generate corresponding standard mask patterns.

It should be noted that the plurality of chip layouts may be all chip layouts with labels; the plurality of chip layouts can be unlabeled chip layouts; the plurality of chip layouts may also include both tagged chip layouts and untagged chip layouts, which are not particularly limited in the embodiments of the present application.

In some embodiments, performing preliminary training on the second lithography mask generation model by using a plurality of chip layouts with labels to obtain a preliminarily trained second lithography mask generation model; the chip layout with the mark refers to a chip layout with a corresponding standard mask map; and performing mask prediction on the chip layouts by adopting the primarily trained second lithography mask generation model to obtain prediction mask diagrams corresponding to the chip layouts respectively.

In some embodiments, the initial second lithographic mask generation model is an initial first lithographic mask generation model, and the first lithographic mask generation model is a primarily trained second lithographic mask generation model. Performing preliminary training on the initial first lithography mask generation model by adopting a plurality of chip layouts with labels to obtain a first lithography mask generation model; and performing mask prediction on the plurality of chip layouts by adopting the first photoetching mask generation model to obtain prediction mask diagrams respectively corresponding to the chip layouts. Firstly, performing preliminary training on a first lithography mask generation model by adopting a chip layout with marks to obtain a first lithography mask generation model after the preliminary training; and performing mask prediction on the plurality of chip layouts by adopting the first photoetching mask generation model after preliminary training to obtain prediction mask diagrams corresponding to the plurality of chip layouts respectively. The model accuracy of the first lithographic mask generation model after the preliminary training may be lower than the model accuracy of the first lithographic mask generation model required to be obtained.

In some embodiments, a plurality of chip layouts respectively corresponding to the predictive mask map is generated using a second lithographic mask generation model different from the first lithographic mask generation model. The second lithography mask generation model is different from the first lithography mask generation model, but is the same type of model as the first lithography mask generation model, and is also a model capable of generating a corresponding prediction mask map based on the chip layout. In some embodiments, the second lithography mask generation model is a model which is already trained, the second lithography mask generation model may be directly adopted to generate the prediction mask graphs corresponding to the plurality of chip layouts respectively, and the model precision may be higher than that of the current first lithography mask generation model.

In some embodiments, the two modes of generating the prediction mask map corresponding to the plurality of chip layouts respectively may be combined. For example, under the condition that the model precision of the first photoetching mask generation model is low (such as the first photoetching mask generation model in an initialized state), a plurality of chip layouts are respectively corresponding to the prediction mask images by adopting the second photoetching mask generation model; under the condition that the model precision of the first photoetching mask generation model is high, the first photoetching mask generation model is adopted to generate a prediction mask map corresponding to the plurality of chip layouts respectively.

In some embodiments, the model accuracy may be determined from a penalty of the lithographic mask generation model, such as directly representing the model accuracy of the lithographic mask generation model in terms of the penalty. Wherein, the smaller the loss, the higher the model accuracy of the lithography mask generation model is; the greater the loss, the lower the model accuracy of the lithographic mask generation model.

Step 402, determining the prediction difficulty corresponding to each chip layout based on the prediction mask map corresponding to each chip layout.

In some embodiments, by performing analysis and calculation on the prediction mask diagrams respectively corresponding to the chip layouts, some calculation results can be obtained as indexes for measuring the prediction difficulty. If there is a large correlation (or strong correlation) between the index corresponding to the prediction mask map and the prediction difficulty of the chip layout, the prediction difficulty corresponding to the chip layout can be indicated based on the index, or the index can be directly used as the prediction difficulty corresponding to the chip layout.

And step 403, selecting a chip layout with the prediction difficulty meeting the condition from the plurality of chip layouts as a difficult chip layout.

In some embodiments, a difficult chip layout may be understood as a mask map that is less easy/difficult to predict by a lithography mask generation model and/or meets design requirements than other chip layouts.

In some embodiments, a chip layout for which the prediction difficulty reaches a difficulty threshold is selected from a plurality of chip layouts as a difficult chip layout.

In some embodiments, ordering the plurality of chip layouts according to the prediction difficulty from high to low, and selecting the first n chip layouts as difficult chip layouts; or ordering the chip layouts according to the prediction difficulty from low to high, selecting n chip layouts as difficult chip layouts, wherein n is a positive integer.

In some embodiments, the chip layout with the highest prediction difficulty is selected from the chip layouts as the difficult chip layout (i.e. the case that n is 1).

And step 404, training the first lithography mask generation model by adopting the difficult chip layout to obtain a trained first lithography mask generation model.

In some embodiments, if the difficult chip layout belongs to the tagged chip layout, the difficult chip layout may be directly used to train the first lithography mask generation model; if the difficult chip layout belongs to the unlabeled chip layout, acquiring a labeled mask map of the difficult chip layout, and training a first photoetching mask to generate a model by adopting the difficult chip layout.

In some embodiments, for the case that the plurality of chip layouts includes a tagged chip layout, the process of selecting a difficult chip layout is a screening process for the tagged chip layout. Optionally, selecting a difficult chip layout from a plurality of chip layouts with marks, and focusing on training a first photoetching mask by using the difficult chip layout to generate a model. For example, training the first lithography mask generation model using only the difficult chip layout; for another example, the frequency of training the first lithography mask generation model with the difficult chip layout is higher than the frequency of training the first lithography mask generation model with other chip layouts with labels. That is, the first lithography mask generation model is mainly trained by adopting the layout of the difficult chip, and the first lithography mask generation model is updated by assisting other chips locally so as to avoid overfitting of the first lithography mask generation model.

In some embodiments, after determining the difficult chip layout, the duty ratio of the difficult chip layout in the marked chip layout adopted for updating the first lithography mask generation model is ensured to be not lower than a threshold value.

In some embodiments, for the case that the plurality of chip layouts includes unlabeled chip layouts, the process of selecting a difficult chip layout is a process of selecting a chip layout from the unlabeled chip layouts for training the first lithographic mask generation model.

In summary, according to the technical scheme provided by the embodiment of the application, since the difficult chip layout can rapidly improve the model precision of the lithography mask generation model, the number of chip layouts required for training the lithography mask generation model can be reduced by selecting the difficult chip layout and training the lithography mask generation model by adopting the difficult chip layout, so that the data marking cost is saved, and the model training cost is further saved.

Referring to FIG. 5, a flowchart of a method for training a lithographic mask generation model is shown, according to another embodiment of the present application. In this embodiment, the method is applied to the model training apparatus described above for illustration. The method may comprise the following steps (501-505):

And step 501, performing preliminary training on the second lithography mask generation model by adopting a plurality of chip layouts with labels to obtain a preliminarily trained second lithography mask generation model.

The chip layout with the label refers to a chip layout with a corresponding standard mask map.

In some embodiments, obtaining a chip layout with labels by obtaining standard mask patterns respectively corresponding to a plurality of chip layouts; and then, adopting standard mask patterns corresponding to the chip layouts respectively to perform preliminary training on the second photoetching mask generation model. The standard mask pattern refers to an OPC-compliant mask pattern.

In the primary training process, the number of the marked chip layouts can be relatively small without too many marked chip layouts. If all the marked chip layouts are called as marked data sets of the second lithography mask generation model, new marked chip layouts are added in the marked data sets. In the preliminary training process, the second lithography mask generation model can adopt the annotation data set to carry out one or more rounds of training, and parameters in the second lithography mask generation model can be optimized and adjusted accordingly.

In some embodiments, the second lithographic mask generation model is a universal Networking (primary class network) deep learning model.

And 502, performing mask prediction on a plurality of unlabeled chip layouts by adopting a primarily trained second lithography mask generation model to obtain predicted mask diagrams corresponding to the unlabeled chip layouts respectively.

The unlabeled chip layout refers to a chip layout in which a corresponding standard mask map is not generated.

In some embodiments, after preliminary training of the chip layouts with labels, the lithography mask generation model performs mask prediction on the plurality of unlabeled chip layouts to obtain prediction masks respectively corresponding to the unlabeled chip layouts.

In some embodiments, the parameters of the second lithographic mask generation model may be fixed during this step 502 because there is no standard mask map reference and the second lithographic mask generation model has no optimization direction or optimization objective during this step.

And step 503, determining the prediction difficulty corresponding to each unlabeled chip layout based on the prediction mask map corresponding to each unlabeled chip layout.

In some embodiments, by performing analysis and calculation on the prediction mask diagrams corresponding to the unlabeled chip layouts respectively, some calculation results can be obtained as indexes for measuring the prediction difficulty. If there is a large correlation (or strong correlation) between the index corresponding to the prediction mask map and the prediction difficulty of the chip layout, the prediction difficulty corresponding to the unlabeled chip layout can be indicated based on the index, or the index can be directly used as the prediction difficulty corresponding to the unlabeled chip layout.

And step 504, selecting unlabeled chip layouts with the prediction difficulty meeting the conditions from a plurality of unlabeled chip layouts as difficult chip layouts.

The difficult chip layout is understood to be a mask diagram which is difficult to predict and obtain high quality and/or meets design requirements by generating a model through a photoetching mask compared with other chip layouts.

In some embodiments, an unlabeled chip layout with a prediction difficulty reaching a difficulty threshold is selected from a plurality of unlabeled chip layouts as a difficult chip layout.

In some embodiments, ordering the unlabeled chip layouts according to the prediction difficulty from high to low, and selecting the first n unlabeled chip layouts as difficult chip layouts; or ordering the unlabeled chip layouts according to the prediction difficulty from low to high, selecting n unlabeled chip layouts as difficult chip layouts, wherein n is a positive integer.

In some embodiments, an unlabeled chip layout with the highest prediction difficulty is selected from unlabeled chip layouts as a difficult chip layout (i.e., the case where n is 1).

And 505, training the first lithography mask generation model by adopting the difficult chip layout to obtain a trained first lithography mask generation model.

In some embodiments, because the prediction difficulty of the high-quality mask map of the difficult chip layout is high, the prediction accuracy of the first lithography mask generation model can be improved in a short time by training the first lithography mask generation model by using the difficult chip layout. If the first photoetching mask generation model can also generate a high-quality prediction mask map for a difficult chip layout, the high-quality prediction mask map can also be generated for other chip layouts.

In some embodiments, a standard mask diagram corresponding to the difficult chip layout is obtained, and the difficult chip layout is added into the existing labeling data set to obtain an updated labeling data set; the existing labeling data set comprises a plurality of chip layouts with labels; and training the first lithography mask generation model by adopting the updated marking data set to obtain a trained first lithography mask generation model. In the embodiment, after the difficult chip layout is determined, a standard mask diagram corresponding to the difficult chip layout is obtained, the difficult chip layout is used as a new marked chip layout to be added into an existing marked data set, and the newly added marked chip layout and the existing marked chip layout are adopted to train a first photoetching mask generation model.

In some embodiments, a lithographic mask generation model is trained using a public lithographic mask dataset (GAN-OPC: mask optimization withlithography-guided generative adversarial nets and Bentian Jiang, et al 2020. Nereal-ILT: migrating ILT to neural networks for mask printability and complexity co-optimization. In Proceedings of the IEEE/ACM International Conference on Computer-advanced Design (ICCA' 20). IEEE, 1-9.) with a total of 10271 chip layouts and corresponding standard mask patterns in both datasets, the chip layouts meeting 32nm process nodes and certain Design rules. In some embodiments, the dataset mask is obtained by a reverse mask optimization algorithm.

In summary, according to the technical scheme provided by the embodiment of the application, the mask generating model is initially trained by adopting the marked chip layout, then the difficult chip layout with larger prediction difficulty is selected from the unmarked chip layouts, and the mask generating model is updated by adopting the difficult chip layout, so that the model precision of the mask generating model can be rapidly improved by adopting fewer chip layouts, the number of marked chip layouts required for training the mask generating model is reduced, and the training cost of the model is saved.

Specifically, the number of chip layouts with labels required for training a photoetching mask generation model is reduced, so that the fund cost required by the model training process can be saved; on the other hand, the model accuracy of the lithography mask generation model can be improved relatively quickly by training the difficult chip layout, so that the time required by model training is saved, and the training efficiency of the model is improved.

As shown in fig. 6, step 503 in the embodiment of fig. 5 described above may include the following sub-steps (5031-5033):

step 5031, for each chip layout, obtaining a predicted mask map corresponding to the chip layout based on standard process parameters, and obtaining a target wafer pattern corresponding to the chip layout.

In some embodiments, a target wafer pattern of a predicted mask map corresponding to a chip layout under standard process parameters is obtained. In some embodiments, the standard process parameters include: reference exposure (e.g., 100% exposure), reference defocus (e.g., 100% defocus). In some embodiments, a model is used to generate a target wafer pattern of a predicted mask map corresponding to a chip layout under standard process parameters.

In some embodiments, a lithographic physical model (Lithography Simulation, LS) is used to generate a target wafer pattern corresponding to the chip layout based on the standard process parameters and a predictive mask map corresponding to the chip layout, the lithographic physical model being a mathematical physical simulation model based on optical principles. In some embodiments, the wafer pattern is generated based on a lithographic physical model. Optionally, inputting the selected process parameters (such as standard process parameters) and the mask map into a lithography physical model, and generating light intensity distribution corresponding to the process parameters and the chip layout by using a lithography indoor model; and then the light intensity distribution is converted into a wafer pattern corresponding to the technological parameter and the chip layout through a sigmoid function.

The lithography physical model is a Hopkins diffraction lithography physical model of a partial coherence imaging system, and the model obtains the light intensity distribution I imaged on a wafer; the light intensity distribution I is obtained by convolving a mask M and a kernel function h of a lithography system; the kernel function is obtained by singular value decomposition of the cross transfer coefficients of a lithography system (e.g., 193 nm annular light source or other sized annular light source). In some embodiments, the lithographic physical model is defined as follows:

wherein h is _k Is the kth kernel function after singular value decomposition, omega _k Is the weight coefficient corresponding to the kth kernel function. In some embodiments, the first 24 kernel functions and corresponding weight coefficients after decomposition by singular values are employed, i.e., k=24.

The final imaging pattern on the wafer is obtained by converting the light intensity distribution imaged on the wafer by the following distribution function (sigmoid function):

Z(x,y)＝1，I(x,y)≥I _th

Z(x,y)＝0，I(x,y)<I _th

wherein I is _th May be 0.225. In some embodiments, I _th Other [0,1 ] can also be taken]Values within the interval, I _th The specific values of (a) may be set by a person skilled in the relevant art according to the actual situation, and the embodiment of the present application is not particularly limited.

Because the lithography physical model is a simulation model, the accuracy of the wafer pattern generated based on the lithography physical model is high although the parameter quantity is large and the calculated quantity in the simulation process is large. In some embodiments, the operating efficiency of the lithographic physical model is optimized by means of GPU (Graphics Processing Unit, image processor) acceleration, or the like.

In some embodiments, a deep learning model may be used to generate a target wafer pattern corresponding to the chip layout based on the standard process parameters and a predicted mask map corresponding to the chip layout, where the deep learning model is a machine learning model constructed based on a neural network and is obtained by training a labeling data set of mask map-wafer pattern. That is, based entirely on machine learning, the deep learning model is enabled to predict the corresponding wafer pattern based on the mask map. In the mode, compared with a photoetching physical model, the parameter quantity of the deep learning model is smaller, the requirement on the operation capability (such as GPU) of equipment is lower, the generation speed of the wafer pattern is faster, and the efficiency is higher.

Step 5032, determining a first error corresponding to the chip layout according to the difference between the target wafer pattern corresponding to the chip layout and the chip layout.

In some embodiments, the higher the predicted mask quality, the smaller the difference between the corresponding wafer pattern and the chip layout; the lower the predicted mask quality, the greater the difference between the corresponding wafer pattern and the chip layout. Thus, the prediction difficulty corresponding to the chip layout can be represented based on the first error.

Step 5033, determining the prediction difficulty corresponding to the chip layout according to the first error corresponding to the chip layout.

In some embodiments, the larger the first error, the lower the quality of the prediction mask, and thus the greater the prediction difficulty corresponding to the chip layout; the smaller the first error is, the higher the quality of the prediction mask is, and the lower the prediction difficulty corresponding to the chip layout is.

In some embodiments, the method may further comprise the following steps (1.1-1.3):

1.1, for each chip layout, acquiring a plurality of wafer patterns corresponding to the obtained chip layout based on a plurality of different process parameters and a prediction mask map corresponding to the chip layout;

1.2, determining a second error corresponding to the chip layout according to differences among a plurality of wafer patterns corresponding to the chip layout;

1.3, determining the prediction difficulty corresponding to the chip layout according to the first error corresponding to the chip layout and the second error corresponding to the chip layout.

In some embodiments, the lower the complexity of the predictive mask, the less the differences between wafer patterns obtained under different process parameters; the higher the complexity of the predictive mask, the greater the difference between wafer patterns obtained under different process parameters. Therefore, the complexity of the prediction mask can be determined through the difference between wafer patterns obtained by the same prediction mask under different process parameter conditions, namely, the second error corresponding to the chip layout is determined. In some embodiments, the second error may be directly used as a prediction difficulty of the chip layout.

In some embodiments, the lithography physical model or the deep learning model may also be used to generate a plurality of wafer patterns corresponding to the chip layout based on a plurality of different process parameters and the prediction mask map corresponding to the chip layout.

In some embodiments, a first wafer pattern and a second wafer pattern, which are obtained by a first technological parameter and a second technological parameter, of a prediction mask image corresponding to a chip layout are obtained; wherein the exposure of the first process parameter is less than the exposure of the second process parameter, and the defocus of the first process parameter is less than the defocus of the second process parameter. In some embodiments, a second error corresponding to the chip layout is determined based on a difference between the first wafer pattern and the second wafer pattern.

That is, a first wafer pattern, which is obtained by a first process parameter, of a predictive mask map corresponding to a chip layout is obtained, and a second wafer pattern, which is obtained by a second process parameter, of the predictive mask map corresponding to the chip layout is obtained. In some embodiments, the exposure of the first process parameter is less than the exposure of the standard process parameter and the defocus of the first process parameter is less than the defocus of the standard process parameter. In some embodiments, the exposure of the second process parameter is higher than the exposure of the standard process parameter and the defocus of the second process parameter is higher than the defocus of the standard process parameter. Thus, the first process parameters may be referred to as low exposure and low defocus and the second process parameters may be referred to as high exposure and high defocus.

Many of the tiny structures of the mask (e.g., holes, protrusions, serrations, etc.) will not be exposed on the wafer (i.e., the wafer corresponding to the first wafer pattern) under low exposure and low defocus conditions; under high exposure and high defocus conditions, the micro structures are exposed on the wafer (i.e., the wafer corresponding to the second wafer pattern). Therefore, the smaller the difference between the first wafer pattern and the second wafer pattern (i.e. the smaller the second error), the smaller the micro structure of the predicted mask pattern, and the lower the complexity, the smaller the prediction difficulty corresponding to the chip layout; the larger the difference between the first wafer pattern and the second wafer pattern (i.e. the larger the second error), the more the micro structure and the higher the complexity of the prediction mask diagram are, the greater the prediction difficulty corresponding to the chip layout is.

In an exemplary embodiment, the first process parameters include: the exposure was 98% of the reference exposure and the defocus was 25 nm. In an exemplary embodiment, the second process parameter includes: the exposure amount was 102% of the reference exposure amount.

Of course, the above data are merely exemplary, and specific values of the exposure amount and defocus in the first process parameter and the second process parameter may be set by a skilled person according to actual situations, and the embodiment of the present application is not limited thereto in particular.

In some embodiments, the prediction difficulty of the chip layout is obtained by weighted summation of the first error and the second error. Illustratively, the prediction difficulty corresponding to the chip layout may be expressed by the following formula:

Target _candidate

＝argmax(|Target-LS(Mask _pred )| ² +α×|LS(Mask _pred ,Pmin)-LS(Mask _pred ,Pmax)| ² )

wherein Target _candidate Representing the prediction difficulty corresponding to the chip layout, argmax (I Target-LSMaskpred2 represents the first error, target represents the chip layout, LSMaskpred represents the Target wafer pattern (under standard technological parameter conditions) corresponding to the chip layout, and LS (Mask) _pred Pmin) -LSMaskpred, pmax2 represents the second error, α represents the coefficient/weight of the second error, LS (Mask _pred Pmin) represents a first wafer pattern, LS (Mask _pred Pmax) represents a second wafer pattern.

In the implementation manner, the wafer pattern of the prediction mask map is used for representing the prediction difficulty relative to the difference (namely the first error) of the chip layout, and the calculation of the first error is convenient and quick, so that the time required for obtaining the chip layout is saved, and the training efficiency of the generation model of the photoetching mask is further improved.

In addition, in the implementation manner, the second error is obtained based on the difference between wafer patterns corresponding to the prediction mask patterns under different process parameters, the second error can be regarded as the complexity of the prediction mask pattern, and the first error and the second error are combined to determine the prediction difficulty, so that the complexity of the prediction mask pattern generated by the lithography mask generation model can be reduced.

As shown in fig. 7, step 503 in the embodiment of fig. 5 described above may further include the following substeps (5034 to 5036):

step 5034, for each chip layout, determining an average predicted mask map of the plurality of predicted mask maps according to the plurality of predicted mask maps generated by the plurality of second lithographic mask generation models for the chip layout.

In some embodiments, a plurality of initialized second lithographic mask generation models are generated; wherein, the second photoetching mask which is initialized differently generates a model with different model parameters; and respectively performing preliminary training on each initialized second lithography mask generation model by adopting a plurality of chip layouts with labels to obtain a plurality of preliminarily trained second lithography mask generation models. The chip layout with the label refers to a chip layout with a corresponding standard mask map. The plurality of primarily trained second photoetching mask generation models are used for generating a plurality of prediction mask images corresponding to the chip layout. Because the model parameters of the second lithography mask generation models initialized differently are different, the model parameters and the generated prediction mask patterns are different after the second lithography mask generation models are trained by the same chip layout with marks, and therefore different prediction mask patterns of the same chip layout corresponding to different second lithography mask generation models are obtained. In some embodiments, the first lithographic mask generation model is a preliminary trained second lithographic mask generation model.

In some embodiments, the plurality of prediction mask maps have the same size, and an average value of element values at the same position in the plurality of prediction mask maps is used as an element value at a corresponding position in the average prediction mask map, so as to obtain the average prediction mask map.

Step 5035, determining uncertainty corresponding to the chip layout according to the differences between the plurality of prediction mask patterns and the average prediction mask pattern.

In some embodiments, for each chip layout, the prediction mask map and the average prediction mask map are respectively subjected to difference to obtain a plurality of mask map differences, and determinant squares of the plurality of mask map differences is then averaged to obtain uncertainty corresponding to the chip layout.

In some embodiments, the computational uncertainty may refer to the following formula:

wherein Target _candidate Representing the uncertainty of the correspondence of the chip layout,is the predictive mask of the ith second lithographic mask generation model,/for the mask generation model>Is an average of a plurality of second lithographic mask generation model predictive masks,<>meaning averaging.

Therefore, the layout with large uncertainty means that the deviation among the prediction results of the plurality of second lithography mask generation models is large, so that the chip layout with large uncertainty can be determined to be a difficult chip layout, and the difficult chip layout is taken as important data affecting the model accuracy.

Step 5036, determining the prediction difficulty corresponding to the chip layout according to the uncertainty corresponding to the chip layout.

In some embodiments, the true error of the predicted outcome (i.e., predicted map) of the lithographic mask generation model may be expressed by the following formula:

wherein Mask represents a mark Mask diagram, sigma obtained by OPC of a chip layout _true Representing the true error.

It can be seen that uncertainty delta is less than true error sigma _true Uncertainty gives the lower boundary of true error; that is, when the uncertainty is large, the true error may be larger than the uncertainty. Therefore, uncertainty can be adopted to approximately represent real errors, and can be directly used as the prediction difficulty corresponding to the chip layout.

In some embodiments, the prediction difficulty corresponding to the chip layout may be determined based on the uncertainty and the first error (e.g., by weighted summing the uncertainty and the first error); the prediction difficulty corresponding to the chip layout can also be determined based on the uncertainty and the second error (such as weighted summation of the uncertainty and the second error); the prediction difficulty corresponding to the chip layout can also be determined based on the uncertainty, the first error and the second error (such as by weighted summing the uncertainty, the first error and the second error). Of course, the prediction difficulty corresponding to the chip layout may also be obtained by integrating other parameters, and may be specifically set by related technicians according to actual conditions, which is not specifically limited in the embodiment of the present application.

In the implementation manner, the voting sampling of the chip layout by using the plurality of second photoetching mask generation models is avoided to a large extent, so that the accuracy of the selected difficult chip layout is higher.

In some possible implementations, as shown in fig. 8, after the step 505, the following steps (506-510) are further included:

and step 506, performing mask prediction on the marked chip layout by using the trained first lithography mask generation model to obtain a predicted mask map corresponding to the marked chip layout.

In some embodiments, the trained first lithographic mask generation model is a model that has been trained based on the first penalty. After the trained first lithography mask generation model is obtained, a prediction mask map with the marked chip layout in the marked data set can be generated by adopting the first lithography mask generation model.

And 507, determining a first loss according to the predicted mask map and the standard mask map corresponding to the chip layout with the label.

The first loss is used for measuring the difference between the prediction mask map and the standard mask map corresponding to the chip map with the label. Thus, the first penalty may be determined based on the difference between the predicted mask map and the standard mask map corresponding to the tagged chip layout.

In some embodiments, the calculation formula of the first loss may refer to the following formula:

L ₁ ＝|Mask-Mask _pred | ²

wherein, mask represents a standard Mask map corresponding to a chip layout with marks, and Mask _pred Representing a prediction mask diagram corresponding to a chip layout with labels, L ₁ Representing a first loss.

Step 508, obtaining a plurality of wafer patterns corresponding to the obtained marked chip layout based on a plurality of different process parameters and the predicted mask map corresponding to the marked chip layout.

In some embodiments, a plurality of wafer patterns for each predicted mask map based on a plurality of different process parameters are obtained by a lithography physical model or a deep learning model.

Step 509, determining a second loss according to the plurality of wafer patterns corresponding to the tagged chip layout,

the second loss is used for measuring consistency among a plurality of wafer patterns corresponding to the chip layout with the label.

In some embodiments, consistency among the plurality of wafer patterns is determined by differences among the plurality of wafer patterns corresponding to the tagged chip layout. The larger the difference between the plurality of wafer patterns, the worse the consistency between the plurality of wafer patterns is determined; the smaller the difference between the differences between the plurality of wafer patterns, the better the consistency between the plurality of wafer patterns is determined. For example, the calculation formula of the second loss may refer to the following formula:

Wherein L is ₂ Indicating a second loss, LS (Mask _pred ,P _i ) Wafer pattern representing a predicted Mask map with a tagged chip layout corresponding to the ith set of process parameters, LS (Mask _pred ,P _c ) Representing a reference wafer pattern corresponding to the layout of the chip with the mark; n represents a total of n groups of process parameters, n is a positive integer greater than 1, and i is a positive integer less than or equal to n. The reference wafer pattern may be a wafer pattern obtained based on standard process parameters, or may be an average wafer pattern of i wafer patterns corresponding to i groups of process parameters of a prediction mask map with a labeling chip layout, which is not particularly limited in the embodiment of the present application.

And step 510, updating the trained first lithography mask generation model according to the first loss and the second loss to obtain the trained first lithography mask generation model.

In some embodiments, the trained first lithographic mask generation model is updated based on the total loss resulting from the weighted sum of the first loss and the second loss to obtain the trained first lithographic mask generation model.

In the implementation manner, after the trained first lithography mask generation model is obtained based on the first loss, consistency among wafer patterns obtained under different process parameter conditions corresponding to the chip layout is considered, and the trained first lithography mask generation model is updated based on the first loss and the second loss, so that robustness of the lithography mask generation model is improved.

The following are device embodiments of the present application, which may be used to perform method embodiments of the present application. For details not disclosed in the device embodiments of the present application, please refer to the method embodiments of the present application.

Referring to FIG. 9, a block diagram of a training apparatus for generating a model of a lithographic mask according to one embodiment of the present application is shown. The device has the function of realizing the training method example of the mask generating model, and the function can be realized by hardware or can be realized by executing corresponding software by hardware. The apparatus 900 may be the model training device described above, or may be disposed on the model training device. The apparatus 900 may include: mask acquisition module 990, difficulty determination module 930, layout selection module 940, and model update module 950.

The mask obtaining module 990 is configured to obtain predicted mask maps corresponding to the plurality of chip layouts respectively.

The difficulty determining module 930 is configured to determine, based on the prediction mask diagrams corresponding to the unlabeled chip layouts, prediction difficulty corresponding to the unlabeled chip layouts.

The layout selection module 940 is configured to select, from the plurality of unlabeled chip layouts, an unlabeled chip layout with the prediction difficulty meeting the condition as a difficult chip layout.

The model updating module 950 is configured to train the first mask generating model by using the difficult chip layout, and obtain a trained first mask generating model.

In some embodiments, as shown in fig. 10, the difficulty determining module 930 includes: a pattern acquisition sub-module 931, an error determination sub-module 932, and a difficulty determination sub-module 933.

The pattern obtaining submodule 931 is configured to obtain, for each of the chip layouts, a target wafer pattern corresponding to the obtained chip layout based on standard process parameters and a prediction mask pattern corresponding to the chip layout.

The error determination submodule 932 is configured to determine a first error corresponding to the chip layout according to a difference between a target wafer pattern corresponding to the chip layout and the chip layout.

The difficulty determining submodule 933 is configured to determine a prediction difficulty corresponding to the chip layout according to a first error corresponding to the chip layout.

In some embodiments, as shown in fig. 10, the apparatus 900 further comprises: a pattern acquisition module 960 and an error determination module 970.

The pattern obtaining module 960 is configured to obtain, for each of the chip layouts, a plurality of wafer patterns corresponding to the obtained chip layout based on a plurality of different process parameters and a prediction mask map corresponding to the chip layout.

The error determining module 970 is configured to determine a second error corresponding to the chip layout according to differences between the plurality of wafer patterns corresponding to the chip layout.

The difficulty determining submodule 933 is configured to determine a prediction difficulty corresponding to the chip layout according to the first error corresponding to the chip layout and the second error corresponding to the chip layout.

In some embodiments, as shown in fig. 10, the pattern obtaining module 960 is configured to obtain a first wafer pattern and a second wafer pattern of the prediction mask map corresponding to the chip layout, where the first wafer pattern and the second wafer pattern are obtained by using a first process parameter and a second process parameter; wherein the exposure of the first process parameter is less than the exposure of the second process parameter, and the defocus of the first process parameter is less than the defocus of the second process parameter.

The error determining module 970 is configured to determine a second error corresponding to the chip layout according to a difference between the first wafer pattern and the second wafer pattern.

In some embodiments, the mask obtaining module 990 is configured to generate a target wafer pattern corresponding to the chip layout based on the standard process parameter and a predicted mask map corresponding to the chip layout by using a lithography physical model, where the lithography physical model is a mathematical physical simulation model based on an optical principle; or generating a target wafer pattern corresponding to the chip layout by adopting a deep learning model based on the standard technological parameters and a prediction mask map corresponding to the chip layout, wherein the deep learning model is a machine learning model constructed based on a neural network.

In some embodiments, the mask acquiring module 990 is configured to:

performing preliminary training on the second lithography mask generation model by adopting a plurality of chip layouts with labels to obtain a preliminarily trained second lithography mask generation model; the chip layout with the label refers to a chip layout with a corresponding standard mask map;

and performing mask prediction on the chip layouts by adopting the primarily trained second photoetching mask generation model to obtain prediction mask diagrams respectively corresponding to the chip layouts.

In some embodiments, the difficulty determination module 930 is configured to:

for each chip layout, determining an average prediction mask map of a plurality of prediction mask maps according to the plurality of prediction mask maps generated by the plurality of primarily trained second lithography mask generation models for the chip layout;

determining uncertainty corresponding to the chip layout according to the differences between the plurality of prediction mask patterns and the average prediction mask pattern;

and determining the prediction difficulty corresponding to the chip layout according to the uncertainty corresponding to the chip layout.

In some embodiments, the mask obtaining module 990 is configured to generate, for each of the chip layouts, a plurality of prediction mask maps corresponding to the chip layouts by generating a model through a plurality of the second lithography masks.

In some embodiments, as shown in fig. 10, the apparatus 900 further comprises: model generation module 910, model training module 920.

The model generating module 910 is configured to generate a plurality of initialized second lithography mask generating models; wherein, the second lithography mask generation model is different from the initialization, and has different model parameters;

the model training module 920 is configured to perform preliminary training on each of the initialized second lithography mask generating models by using a plurality of chip layouts with labels, so as to obtain a plurality of preliminarily trained second lithography mask generating models; the chip layout with the label refers to a chip layout with a corresponding standard mask map; the plurality of primarily trained second photoetching mask generation models are used for generating a plurality of prediction mask diagrams corresponding to the chip layout.

In some embodiments, the first lithographic mask generation model is the initially trained second lithographic mask generation model. In some embodiments, the model update module 950 is configured to:

obtaining a standard mask diagram corresponding to the difficult chip layout, and adding the difficult chip layout into the existing labeling data set to obtain an updated labeling data set; the existing marked data set comprises a plurality of marked chip layouts, wherein the marked chip layouts refer to chip layouts with corresponding standard mask patterns;

And training the first lithography mask generation model by adopting the updated marking data set to obtain the trained first lithography mask generation model.

In some embodiments, as shown in fig. 10, the apparatus 900 further comprises: a mask prediction module 995 and a loss determination module 980.

The mask prediction module 995 is configured to perform mask prediction on the layout with the marked chip by using the trained first lithography mask generation model, so as to obtain a predicted mask map corresponding to the layout with the marked chip.

The loss determination module 980 is configured to determine a first loss according to the prediction mask map and the standard mask map corresponding to the labeled chip layout, where the first loss is used to measure a difference between the prediction mask map and the standard mask map corresponding to the labeled chip layout.

The pattern obtaining module 960 is configured to obtain a plurality of wafer patterns corresponding to the labeled chip layout based on a plurality of different process parameters and a prediction mask map corresponding to the labeled chip layout;

the loss determination module 980 is further configured to determine a second loss according to the plurality of wafer patterns corresponding to the labeled chip layout, where the second loss is used to measure consistency between the plurality of wafer patterns corresponding to the labeled chip layout.

The model updating module 950 is further configured to update the trained first mask generation model according to the first loss and the second loss, to obtain an updated first mask generation model.

In summary, according to the technical scheme provided by the embodiment of the application, since the difficult chip layout can rapidly improve the model precision of the lithography mask generation model, the number of chip layouts required for training the lithography mask generation model can be reduced by selecting the difficult chip layout and updating the lithography mask generation model by adopting the difficult chip layout, so that the data marking cost is saved, and the model training cost is further saved.

It should be noted that, in the apparatus provided in the foregoing embodiment, when implementing the functions thereof, only the division of the foregoing functional modules is used as an example, in practical application, the foregoing functional allocation may be implemented by different functional modules, that is, the internal structure of the device is divided into different functional modules, so as to implement all or part of the functions described above. In addition, the apparatus and the method embodiments provided in the foregoing embodiments belong to the same concept, and specific implementation processes of the apparatus and the method embodiments are detailed in the method embodiments and are not repeated herein.

Referring to FIG. 11, a block diagram of a computer device according to one embodiment of the present application is shown. The computer apparatus is used to implement the training method of the lithographic mask generation model provided in the above embodiments. Specifically, the present invention relates to a method for manufacturing a semiconductor device.

The computer apparatus 1100 includes a CPU (Central Processing Unit ) 1101, a system Memory 1104 including a RAM (Random Access Memory ) 1102 and a ROM (Read-Only Memory) 1103, and a system bus 1105 connecting the system Memory 1104 and the central processing unit 1101. The computer device 1100 also includes a basic I/O (Input/Output) system 1106, which facilitates the transfer of information between various devices within the computer, and a mass storage device 1107 for storing an operating system 1113, application programs 1114, and other program modules 1115.

The basic input/output system 1106 includes a display 1108 for displaying information and an input device 1109, such as a mouse, keyboard, etc., for a user to input information. Wherein the display 1108 and the input device 1109 are both coupled to the central processing unit 1101 through an input-output controller 1110 coupled to the system bus 1105. The basic input/output system 1106 may also include an input/output controller 1110 for receiving and processing input from a number of other devices, such as a keyboard, mouse, or electronic stylus. Similarly, the input output controller 1110 also provides output to a display screen, a printer, or other type of output device.

The mass storage device 1107 is connected to the central processing unit 1101 through a mass storage controller (not shown) connected to the system bus 1105. The mass storage device 1107 and its associated computer-readable media provide non-volatile storage for the computer device 1100. That is, the mass storage device 1107 may include a computer-readable medium (not shown) such as a hard disk or CD-ROM (Compact Disc Read-Only Memory) drive.

The computer readable medium may include computer storage media and communication media without loss of generality. Computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes RAM, ROM, EPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory, erasable programmable read-only memory), flash memory or other solid state memory, CD-ROM, DVD (Digital Video Disc, high density digital video disc) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices. Of course, those skilled in the art will recognize that the computer storage medium is not limited to the one described above. The system memory 1104 and mass storage device 1107 described above may be collectively referred to as memory.

According to various embodiments of the present application, the computer device 1100 may also operate by being connected to a remote computer on a network, such as the Internet. I.e., the computer device 1100 may connect to the network 1112 through a network interface unit 1111 connected to the system bus 1105, or other types of networks or remote computer systems (not shown) may be connected using the network interface unit 1111.

In an exemplary embodiment, a computer readable storage medium is also provided, in which a computer program is stored which, when being executed by a processor, implements the above-described training method of a lithographic mask generation model.

Alternatively, the computer-readable storage medium may include: ROM (Read-Only Memory), RAM (Random-Access Memory), SSD (Solid State Drives, solid State disk), optical disk, or the like. The random access memory may include ReRAM (Resistance Random Access Memory, resistive random access memory) and DRAM (Dynamic Random Access Memory ), among others.

In an exemplary embodiment, a computer program product is also provided, the computer program product comprising a computer program stored in a computer readable storage medium. The processor of the computer apparatus reads the computer program from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer apparatus performs the above-described training method of the lithographic mask generation model.

It should be understood that references herein to "a plurality" are to two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.

The foregoing description of the exemplary embodiments of the present application is not intended to limit the invention to the particular embodiments disclosed, but on the contrary, the intention is to cover all modifications, equivalents, alternatives, and alternatives falling within the spirit and scope of the invention.

Claims

1. A method for training a lithographic mask generation model, the method comprising:

and training the first lithography mask generation model by adopting the difficult chip layout to obtain a trained first lithography mask generation model.

2. The method of claim 1, wherein determining the prediction difficulty for each of the chip layouts based on the prediction mask map for each of the chip layouts, respectively, comprises:

for each chip layout, acquiring a predicted mask diagram based on standard process parameters and corresponding to the chip layout, and acquiring a target wafer pattern corresponding to the chip layout;

determining a first error corresponding to the chip layout according to the difference between the target wafer pattern corresponding to the chip layout and the chip layout;

and determining the prediction difficulty corresponding to the chip layout according to the first error corresponding to the chip layout.

3. The method according to claim 2, wherein the method further comprises:

for each chip layout, acquiring a plurality of wafer patterns corresponding to the chip layout based on a plurality of different process parameters and a prediction mask map corresponding to the chip layout;

determining a second error corresponding to the chip layout according to the difference among the wafer patterns corresponding to the chip layout;

the determining the prediction difficulty corresponding to the chip layout according to the first error corresponding to the chip layout comprises the following steps:

And determining the prediction difficulty corresponding to the chip layout according to the first error corresponding to the chip layout and the second error corresponding to the chip layout.

4. The method of claim 3, wherein the obtaining a plurality of wafer patterns corresponding to the chip layout based on a plurality of different process parameters and a prediction mask map corresponding to the chip layout comprises:

acquiring a first wafer pattern and a second wafer pattern, which are obtained by a first process parameter and a second process parameter, of a prediction mask map corresponding to the chip layout; wherein the exposure of the first process parameter is less than the exposure of the second process parameter, and the defocus of the first process parameter is less than the defocus of the second process parameter;

the determining the second error corresponding to the chip layout according to the difference between the wafer patterns corresponding to the chip layout comprises:

and determining a second error corresponding to the chip layout according to the difference between the first wafer pattern and the second wafer pattern.

5. The method according to claim 2, wherein the obtaining a target wafer pattern corresponding to the chip layout based on the standard process parameters and the predicted mask map corresponding to the chip layout includes:

Generating a target wafer pattern corresponding to the chip layout based on the standard process parameters and a prediction mask diagram corresponding to the chip layout by adopting a photoetching physical model, wherein the photoetching physical model is a mathematical physical simulation model based on an optical principle;

or,

and generating a target wafer pattern corresponding to the chip layout by adopting a deep learning model based on the standard technological parameters and a prediction mask map corresponding to the chip layout, wherein the deep learning model is a machine learning model constructed based on a neural network.

6. The method according to claim 2, wherein the obtaining the prediction mask map corresponding to each of the plurality of chip layouts includes:

7. The method of claim 1, wherein determining the prediction difficulty for each of the chip layouts based on the prediction mask map for each of the chip layouts, respectively, comprises:

For each chip layout, determining an average prediction mask map of a plurality of prediction mask maps according to the plurality of prediction mask maps generated by a plurality of second photoetching mask generation models for the chip layout;

8. The method of claim 7, wherein the obtaining a plurality of prediction mask patterns respectively corresponding to the chip layouts:

and generating a model for each chip layout through a plurality of second photoetching masks, and generating a plurality of prediction mask diagrams corresponding to the chip layout.

9. The method of claim 7, wherein the method further comprises:

generating a plurality of initialized second lithography mask generation models; wherein, the second lithography mask generation model is different from the initialization, and has different model parameters;

performing preliminary training on each initialized second lithography mask generation model by adopting a plurality of chip layouts with labels to obtain a plurality of preliminarily trained second lithography mask generation models; the chip layout with the label refers to a chip layout with a corresponding standard mask map;

The plurality of primarily trained second photoetching mask generation models are used for generating a plurality of prediction mask diagrams corresponding to the chip layout.

10. The method according to claim 6 or 9, wherein the first lithographic mask generation model is the initially trained second lithographic mask generation model.

11. The method according to any one of claims 1 to 9, wherein training the first lithography mask generation model using the difficult chip layout to obtain a trained first lithography mask generation model comprises:

12. The method according to any one of claims 1 to 9, wherein training the first lithography mask generation model using the difficult chip layout, after obtaining a trained first lithography mask generation model, further comprises:

Performing mask prediction on the chip layout with the mark by adopting the trained first photoetching mask generation model to obtain a predicted mask map corresponding to the chip layout with the mark, wherein the chip layout with the mark refers to a chip layout with a corresponding standard mask map;

determining a first loss according to the predicted mask map and the standard mask map corresponding to the marked chip layout, wherein the first loss is used for measuring the difference between the predicted mask map and the standard mask map corresponding to the marked chip layout;

acquiring a plurality of wafer patterns corresponding to the marked chip layout based on a plurality of different process parameters and the predicted mask diagram corresponding to the marked chip layout;

determining a second loss according to the wafer patterns corresponding to the marked chip layout, wherein the second loss is used for measuring the consistency among the wafer patterns corresponding to the marked chip layout;

and updating the trained first lithography mask generation model according to the first loss and the second loss to obtain an updated first lithography mask generation model.

13. A lithographic mask generation model training apparatus, the apparatus comprising:

and the model updating module is used for training the first lithography mask generation model by adopting the difficult chip layout to obtain a trained first lithography mask generation model.

14. A computer device comprising a processor and a memory, the memory having stored therein a computer program that is loaded and executed by the processor to implement a method of training a lithographic mask generation model according to any of the preceding claims 1 to 12.

15. A computer readable storage medium having stored therein a computer program to be loaded and executed by a processor to implement a method of training a lithographic mask generation model according to any of the preceding claims 1 to 12.

16. A computer program product, characterized in that it comprises a computer program stored in a computer readable storage medium, from which a processor reads and executes the computer program to implement a method of training a lithographic mask generation model according to any of claims 1 to 12.