CN117313637A - Training method of recommended region generation algorithm model, PCB wiring method and system - Google Patents

Abstract

The disclosure provides a training method, a PCB wiring method and a system for generating an algorithm model in a recommended region, wherein the training method of the algorithm model comprises the following steps: generating PCB test questions with different constraint parameters by using a PCB question generation tool; wiring the PCB test problem by using an Astar algorithm; randomly selecting a line from the wiring result as a line to be learned, and generating a recommended region suitable for being connected with the line to be learned by using a recommended region generating tool based on a Lee algorithm to obtain a recommended region-line to be learned data set; and dividing the data set into a training set and a testing set, inputting the training set and the testing set into the deep recommended region generating network for training, and obtaining the optimized deep recommended region generating network. The training method of the algorithm model can be applied to the field of printed circuit board wiring, and can improve wiring efficiency and reduce labor cost.

Description

Training method of recommended region generation algorithm model, PCB wiring method and system

Technical Field

The present disclosure relates to the field of printed circuit board (Printed Circuit Board, PCB) routing, and in particular to a training method, PCB routing method, system, device, storage medium and program product for a recommended region generation algorithm model.

Background

With the rapid development of electronic information technology, integrated circuit technology has entered the nanoera, the integration level of components on a printed circuit board has been continuously improved, the number of pins has been increased, the connection relationship between components has become more and more complex, and wiring tasks in PCB design have become difficult. However, the existing automatic routing algorithm has a certain limitation in terms of routing success rate and speed, and the current industrial application still relies heavily on engineers to manually route PCBs, which causes routing work to consume a great deal of time and manpower resources. Therefore, there is an urgent need for an intelligent automatic routing algorithm that can be practically applied to modern large-scale electronic circuit designs to improve the design efficiency of electronic design automation (Electronic Design Automation, EDA).

In recent years, many researches have been made in this field. These studies have focused mainly on both area wiring and escape wiring. The area wiring refers to a process of connecting a pin wiring located inside a component to an edge of the component, and the escape wiring refers to a process of wiring between two components.

However, according to our observations of an actual PCB design, a large number of non-BGA packaged components are typically included in the design, such as passive devices, decoupling capacitors, and via pin arrays. These non-BGA packaged components are typically distributed in an irregular manner in the PCB design, resulting in uneven routing congestion distribution, making routing tasks more difficult. Therefore, there is an urgent need to develop a PCB routing algorithm capable of coping with such problems.

In related studies, lin et al first proposed a unified wiring method based on the Astar algorithm, which was able to accomplish this task. However, this algorithm still has a large room for improvement in terms of wiring speed, and cannot fully utilize the current increasingly powerful GPU power resources. Therefore, there is a need for further improvements in routing algorithms to increase routing speed and efficiency, leveraging modern computing resources.

Disclosure of Invention

In view of the foregoing, the present disclosure provides a training method, a PCB routing method, a system, an apparatus, a storage medium, and a program product for a recommended region generation algorithm model.

According to a first aspect of the present disclosure, there is provided a training method of a recommended region generation algorithm model, including: generating PCB test questions with different constraint parameters by using a PCB question generation tool; wiring the PCB test problem by using an Astar algorithm; randomly selecting a line from the wiring result as a line to be learned, and generating a recommended region suitable for being connected with the line to be learned by using a recommended region generating tool based on a Lee algorithm to obtain a recommended region-line to be learned data set; and dividing the data set into a training set and a testing set, inputting the training set and the testing set into the deep recommended region generating network for training, and obtaining the optimized deep recommended region generating network.

According to an embodiment of the present disclosure, generating a PCB test question with different constraint parameters using a PCB question generation tool includes: inputting parameters required for generating PCB test problems; randomly generating bonding pads by using uniform distribution; the positions of the bonding pads are adjusted through a gravity potential field method so as to reduce the probability of contacting with adjacent bonding pads; randomly generating obstacles by using uniform distribution; and connecting the bonding pads through random selection to form complete PCB wiring, and generating PCB test problems with different constraint parameters.

In accordance with an embodiment of the present disclosure, routing PCB test problems using the Astar algorithm includes: initial PCB test problems; wherein the PCB test problems include pad locations, routing areas, and constraints; according to the initial state of the current PCB test problem, performing path searching and optimizing by using an Astar algorithm; generating an optimal path according to physical limitation of wiring, signal transmission requirements and constraint conditions; updating the state of PCB test problems, including routed lines and connection states; repeating the wiring steps until all the circuits are successfully wired, and finishing the wiring operation.

According to an embodiment of the present disclosure, generating a recommended region suitable for connecting to a line to be learned using a Lee algorithm-based recommended region generation tool includes: randomly selecting a line from the wiring result as a line to be learned, and marking the line to be learned as a state to be learned; using a recommended region generating tool based on a Lee algorithm, taking undeleted circuits and bonding pads as input, and generating a recommended region suitable for connecting the circuits to be learned; taking the recommended area and the line to be learned as the output of training data, and ensuring that the corresponding relation between the recommended area and the line to be learned is accurate; selecting different lines to be learned, and repeating the step of generating the recommended region to generate the required number of data sets.

According to an embodiment of the present disclosure, dividing the data set into a training set and a test set, inputting the deep recommendation area generation network for training includes: randomly selecting a part of the generated data set as a training set, and randomly selecting a part of the generated data set as a test set, so as to ensure that the quantity of the training set and the quantity of the test set are in a preset proportion; generating a network processing training set by using the deep recommendation region, training parameters of the deep recommendation region generating network by using a back propagation and optimization algorithm according to the processing result of the training set, and obtaining a trained deep recommendation region generating network; generating a network processing test set by using the trained deepsunet recommended region, obtaining the score of each trained deepsunet recommended region generation network, and obtaining an optimized deepsunet recommended region generation network according to the score; the convolution layer number of the deep recommended region generation network is 28 layers, and the total connection layer number is 3 layers.

A second aspect of the present disclosure provides a PCB routing method, comprising: acquiring a wiring problem to be processed, and inputting a current line and other bonding pads in the wiring problem to be processed as barriers into an optimized deep recommendation area generating network to obtain a recommendation area; the optimized deep recommended region generation network is obtained according to the training method of the recommended region generation algorithm model; inputting the recommended area and the current line into an Astar algorithm to obtain an updated line, and completing the wiring process.

A third aspect of the present disclosure provides a training system of a recommended region generation algorithm model, comprising: the test problem generating module is used for generating PCB test problems with different constraint parameters by utilizing the PCB problem generating tool; the wiring module is used for wiring the PCB test problem by using an Astar algorithm; the recommendation area generating module is used for randomly selecting a line from the wiring result as a line to be learned, generating a recommendation area suitable for being connected with the line to be learned by using a recommendation area generating tool based on a Lee algorithm, and obtaining a recommendation area-line to be learned data set; the training module is used for dividing the data set into a training set and a testing set, inputting the training set into the deep recommended region generation network for training, and obtaining the optimized deep recommended region generation network.

A fourth aspect of the present disclosure provides an electronic device, comprising: one or more processors; and a memory for storing one or more programs, wherein the one or more programs, when executed by the one or more processors, cause the one or more processors to perform the training method of the recommended region generation algorithm model described above.

The fifth aspect of the present disclosure also provides a computer-readable storage medium having stored thereon executable instructions that, when executed by a processor, cause the processor to perform the training method of the recommended region generation algorithm model described above.

A sixth aspect of the present disclosure also provides a computer program product comprising a computer program which, when executed by a processor, implements the training method of the above-described recommended region generation algorithm model.

Drawings

The foregoing and other objects, features and advantages of the disclosure will be more apparent from the following description of embodiments of the disclosure with reference to the accompanying drawings, in which:

FIG. 1 schematically illustrates an application scenario diagram of a training method, PCB routing method, system, device, storage medium, and program product of a recommended region generation algorithm model according to an embodiment of the disclosure;

FIG. 2 schematically illustrates a flowchart of a training method of a recommended region generation algorithm model, according to an embodiment of the disclosure;

fig. 3 schematically illustrates a structural diagram of a deep recommendation area generation network according to an embodiment of the present disclosure;

FIG. 4 schematically illustrates a structural schematic of a Unet-Astar algorithm in accordance with an embodiment of the present disclosure;

FIG. 5 schematically illustrates a block diagram of a training system of a recommended region generation algorithm model in accordance with an embodiment of the disclosure; and

fig. 6 schematically shows a block diagram of an electronic device adapted to implement the method described above, according to an embodiment of the disclosure.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.

In the technical scheme of the disclosure, the acquisition, storage, application and the like of the related personal information of the user all conform to the regulations of related laws and regulations, necessary security measures are taken, and the public order harmony is not violated.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The terms "comprises," "comprising," and/or the like, as used herein, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.

All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. It should be noted that the terms used herein should be construed to have meanings consistent with the context of the present specification and should not be construed in an idealized or overly formal manner.

Where expressions like at least one of "A, B and C, etc. are used, the expressions should generally be interpreted in accordance with the meaning as commonly understood by those skilled in the art (e.g.," a system having at least one of A, B and C "shall include, but not be limited to, a system having a alone, B alone, C alone, a and B together, a and C together, B and C together, and/or A, B, C together, etc.). Where a formulation similar to at least one of "A, B or C, etc." is used, in general such a formulation should be interpreted in accordance with the ordinary understanding of one skilled in the art (e.g. "a system with at least one of A, B or C" would include but not be limited to systems with a alone, B alone, C alone, a and B together, a and C together, B and C together, and/or A, B, C together, etc.).

Some of the block diagrams and/or flowchart illustrations are shown in the figures. It will be understood that some blocks of the block diagrams and/or flowchart illustrations, or combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the instructions, when executed by the processor, create means for implementing the functions/acts specified in the block diagrams and/or flowchart. The techniques of this disclosure may be implemented in hardware and/or software (including firmware, microcode, etc.). Additionally, the techniques of this disclosure may take the form of a computer program product on a computer-readable storage medium having instructions stored thereon, the computer program product being for use by or in connection with an instruction execution system.

The current manual routing task is time consuming and complex due to the problems of increased pin count, high pin density, physical limitations, and the like. To solve these problems, previous studies have decomposed the wiring task into escape routing and area routing, and have been studied separately. However, there is a gap between these two problems, requiring a lot of manpower to fine tune the algorithm. In addition, past area routing efforts have focused on escape routing between Ball Grid Arrays (BGAs), while omitting other forms of components such as passive devices, decoupling capacitors, and via pin arrays. Accordingly, the present disclosure provides a new unified routing scheme and related algorithms that can be applied in the printed circuit board routing area, improving routing efficiency and reducing labor costs.

Fig. 1 schematically illustrates an application scenario diagram of a training method of a recommended region generation algorithm model, a PCB routing method according to an embodiment of the present disclosure.

As shown in fig. 1, an application scenario 100 according to this embodiment may include terminal devices 101, 102, 103, a network 104, and a server 105. The network 104 is used as a medium to provide communication links between the terminal devices 101, 102, 103 and the server 105. The network 104 may include various connection types, such as wired, wireless communication links, or fiber optic cables, among others.

The user may interact with the server 105 via the network 104 using the terminal devices 101, 102, 103 to receive or send messages or the like. Various communication client applications, such as shopping class applications, web browser applications, search class applications, instant messaging tools, mailbox clients, social platform software, etc. (by way of example only) may be installed on the terminal devices 101, 102, 103.

The terminal devices 101, 102, 103 may be a variety of electronic devices having a display screen and supporting web browsing, including but not limited to smartphones, tablets, laptop and desktop computers, and the like.

The server 105 may be a server providing various services, such as a background management server (by way of example only) providing support for websites browsed by users using the terminal devices 101, 102, 103. The background management server may analyze and process the received data such as the user request, and feed back the processing result (e.g., the web page, information, or data obtained or generated according to the user request) to the terminal device.

It should be noted that, the training method of the recommended region generation algorithm model provided in the embodiment of the disclosure may be generally executed by the server 105. Accordingly, the training apparatus of the recommended region generation algorithm model provided by the embodiments of the present disclosure may be generally provided in the server 105. The training method of the recommended region generation algorithm model provided by the embodiments of the present disclosure may also be performed by a server or a server cluster that is different from the server 105 and is capable of communicating with the terminal devices 101, 102, 103 and/or the server 105. Accordingly, the training apparatus of the recommended region generation algorithm model provided by the embodiments of the present disclosure may also be provided in a server or a server cluster that is different from the server 105 and is capable of communicating with the terminal devices 101, 102, 103 and/or the server 105.

It should be understood that the number of terminal devices, networks and servers in fig. 1 is merely illustrative. There may be any number of terminal devices, networks, and servers, as desired for implementation.

The training method and the PCB routing method of the recommended region generation algorithm model according to the disclosed embodiment will be described in detail below with reference to fig. 2 to 6 based on the scenario described in fig. 1.

FIG. 2 schematically illustrates a flowchart of a training method of a recommended region generation algorithm model, according to an embodiment of the disclosure.

As shown in fig. 2, the training method of the recommended region generation algorithm model of this embodiment includes operations S210 to S240 by performing inference calculation of the recommended region of the wiring using the GPU.

In operation S210, PCB test questions having different constraint parameters are generated using the PCB question generation tool.

In operation S220, PCB test problems are routed using the Astar algorithm.

In operation S230, a line is randomly selected from the result of the wiring as a line to be learned, and a recommended region suitable for connecting to the line to be learned is generated by using a Lee algorithm-based recommended region generating tool, thereby obtaining a recommended region-line to be learned dataset.

In operation S240, the data set is divided into a training set and a test set, and the training is performed by inputting the deep recommendation area generating network, so as to obtain an optimized deep recommendation area generating network.

In one aspect, the present disclosure provides a PCB problem generation tool for generating a parameterized global routing problem set with different sizes and constraints to evaluate different routing algorithms and generate training data sets for future data driven routing methods; on the other hand, a deep recommendation area generating network is also provided for generating recommendation areas of wiring algorithms, and the new network structure provides more context information, so that wiring efficiency is improved.

On the basis of the above embodiment, generating the PCB test questions with different constraint parameters using the PCB question generation tool includes: inputting parameters required for generating PCB test problems; randomly generating bonding pads by using uniform distribution; the positions of the bonding pads are adjusted through a gravity potential field method so as to reduce the probability of contacting with adjacent bonding pads; randomly generating obstacles by using uniform distribution; and connecting the bonding pads through random selection to form complete PCB wiring, and generating PCB test problems with different constraint parameters.

Parameters required by PCB test problems are first generated, and pads are randomly generated with uniform distribution. In order not to violate the design rule, the gravity potential field method is used to reduce the connection probability of adjacent pads to increase the feasibility of the problem. Meanwhile, the same method is used to generate an obstacle to simulate the obstacle situation in the wiring. Finally, the bonding pads are connected in a random selection mode to form a complete PCB wiring. The PCB problem generation tool is capable of generating PCB problems with different parameters and randomness, providing a diverse set of test data for subsequent routing algorithms.

Based on the above embodiments, using the Astar algorithm to route PCB test problems includes: initializing a PCB test problem; wherein the PCB test problems include pad locations, routing areas, and constraints; according to the initial state of the current PCB test problem, performing path searching and optimizing by using an Astar algorithm; generating an optimal path according to physical limitation of wiring, signal transmission requirements and constraint conditions; updating the state of PCB test problems, including routed lines and connection states; repeating the wiring steps until all the circuits are successfully wired, and finishing the wiring operation.

On the basis of the above embodiment, generating a recommended region suitable for connecting to a line to be learned using a Lee algorithm-based recommended region generation tool includes: randomly selecting a line from the wiring result as a line to be learned, and marking the line to be learned as a state to be learned; using a recommended region generating tool based on a Lee algorithm, taking undeleted circuits and bonding pads as input, and generating a recommended region suitable for connecting the circuits to be learned; taking the recommended area and the line to be learned as the output of training data, and ensuring that the corresponding relation between the recommended area and the line to be learned is accurate; selecting different lines to be learned, and repeating the step of generating the recommended region to generate the required number of data sets.

This step details how a large number of training data sets are generated for use in subsequent learning and training processes. Firstly, randomly selecting a line from the completed wiring result as a line to be learned; the selected line is marked as a state to be learned for a subsequent training data generation process. Then, using a recommended region generating tool based on the Lee algorithm, and taking undeleted lines and pads as inputs; based on the positional relationship of the line and the pad, a recommended region is generated, wherein the recommended region represents a potential path suitable for connecting the line to be learned. Then, taking the generated recommended region and the line to be learned as output of training data; and ensuring that the corresponding relation between the recommended area and the line to be learned is accurate. Finally, returning to the step of randomly selecting the line, selecting another line as the line to be learned, and repeating the steps until the training data sets with the required number are generated. Through this process, a large amount of training data with different wiring conditions can be generated for learning and training of the model.

On the basis of the above embodiment, dividing the data set into a training set and a test set, inputting the deep recommendation area generating network for training includes: randomly selecting a part of the generated data set as a training set, and randomly selecting a part of the generated data set as a test set, so as to ensure that the quantity of the training set and the quantity of the test set are in a preset proportion; generating a network processing training set by using the deep recommendation region, training parameters of the deep recommendation region generating network by using a back propagation and optimization algorithm according to the processing result of the training set, and obtaining a trained deep recommendation region generating network; generating a network processing test set by using the trained deepsunet recommended region, obtaining the score of each trained deepsunet recommended region generation network, and obtaining an optimized deepsunet recommended region generation network according to the score; the convolution layer number of the deep recommended region generation network is 28 layers, and the total connection layer number is 3 layers.

Firstly, randomly dividing the training set into a training set and a testing set, wherein the quantity of the training set and the testing set is a preset proportion, such as 7: and 3, performing a training process of generating a network by using the deep recommended region. The input data of the training set (including the undeleted lines and pads) is then provided to the deep recommendation area generation network for training. The deep recommendation area generation network is trained through a back propagation and optimization algorithm, so that the deep recommendation area generation network can learn and generate an accurate recommendation area. And finally, verifying by using the test set, and evaluating the performance and accuracy of the deep recommended area generation network. Through the process, the capability of generating the network in the deep recommended area can be trained and verified, and the accuracy and efficiency of a wiring algorithm are further improved.

Fig. 3 is a schematic diagram of a deep recommended region generation network, and the conventional U-net is limited to only short-range spatial information due to the use of a local acceptance domain in the conventional convolution. To enable remote reasoning, a larger acceptance field is required. Therefore, the method improves on the basis of increasing the convolution layer number, increases 3 full connection layers on the last layer to improve the remote reasoning capability, and the modified network is called a deep recommendation area generation network.

The present disclosure also provides a PCB routing method, comprising: acquiring a wiring problem to be processed, and inputting a current line and other bonding pads in the wiring problem to be processed as barriers into an optimized deep recommendation area generating network to obtain a recommendation area; the optimized deep recommended region generation network is obtained according to the training method of the recommended region generation algorithm model; inputting the recommended area and the current line into an Astar algorithm to obtain an updated line, and completing the wiring process.

The step of obtaining the recommended region details the reasoning process of how the recommended region is done for the new wiring problem. Firstly, preparing a new wiring problem, and determining the number, layout and constraint conditions of lines and bonding pads; meanwhile, the current line and other pads are used as the wired barrier to simulate the limitation and constraint in the actual wiring. Next, the new wiring problem and the wired obstacle are input into the deep recommended area generation network. And (3) reasoning through a deep recommendation area generation network to obtain potential recommendation areas, wherein the recommendation areas represent potential paths suitable for connecting lines. Through this process, new wiring problems can be inferred using the learned model, providing references and guidance for wiring.

This routing step details the routing of the recommended section and the current line input Astar algorithm. First, information of a current route and a recommended region is prepared. And acquiring a starting point, an ending point and a path of the connected line of the current line, and simultaneously acquiring a potential connection path and an available space of the recommended area. The current route and recommended region are then provided as inputs to the Astar algorithm. And carrying out path searching and optimizing on the current line by using an Astar algorithm to obtain a new line. Finally, the wiring state, including the wired line and connection state, is updated according to the result of the Astar algorithm. Then, it is checked whether there are wires not yet wired, and if so, the wiring step is returned until all wires are wired. Through the process, the Astar algorithm can be effectively utilized to route the current line and the recommended area, and the whole wiring process is completed.

The present disclosure has described in detail a training method of a recommended region generation algorithm model and a PCB wiring method, and a complete algorithm for realizing wiring acceleration by a machine learning model-guided method is called a Unet-Astar, and the steps thereof include:

Step 1: a number of PCB test questions are generated using a PCB question generation tool.

Step 2: the Astar algorithm was used to route the test questions.

Step 3: after wiring is completed, randomly deleting a line as a line to be learned, taking the undeleted line and a bonding pad as inputs, generating a recommended region by using a recommended region generating tool based on a Lee algorithm, taking the recommended region and the line to be learned as outputs, and repeatedly iterating to generate a large number of training data sets;

step 4: the training set is randomly divided into a training set and a testing set, and the training set and the testing set are sent into a recommended area generating network deep for training.

Step 5: for the new wiring problem, the current line and other bonding pads are used as barriers to be input into a model, and a recommended area is obtained by reasoning; and utilizing the GPU to perform reasoning calculation on the recommended region of the wiring.

Step 6: and then taking the recommended area and the current line as inputs, wiring by an Astar algorithm to obtain a new line, and repeating the process until all the lines are wired.

Fig. 4 is a schematic diagram of the structure of the unate-Astar algorithm aimed at obtaining remote context information from the PCB layout and predicting feasible regions to speed up the routing process. The benchmark test shows that compared with the most advanced Astar unified routing algorithm, the Unet-Astar realizes remarkable speed improvement and can complete wiring tasks more quickly. Experimental results show that the algorithm proposed by the present disclosure is effective and efficient, and in particular, the router of the present disclosure can increase the operation speed by about 70% in all test cases, compared to the conventional router.

Compared with the prior art, the technical scheme has the following beneficial effects:

(1) The wiring efficiency is improved: the traditional algorithm mainly adopts a CPU to calculate, and the advantage of the modern GPU calculation power cannot be fully utilized, so that the algorithm has lower efficiency. The algorithm provided by the disclosure calculates the recommended region of the wiring in a GPU reasoning mode, and the time consumption of wiring tasks is obviously reduced. By fully utilizing the powerful parallel computing capability of the GPU, an efficient wiring algorithm is realized, and the processing speed and efficiency of wiring tasks are improved.

(2) Solve the unified wiring problem of PCB: the existing machine learning model method is widely applied in the wiring field, but only a few papers apply the method directly to the guidance of wiring. Moreover, these studies have focused mainly on global routing of VLSI routing problems, and have not been fully studied for uniform routing problems of PCBs. The present disclosure fills this research gap, providing a model-based acceleration scheme that optimizes the unified routing problem for PCBs. Through the scheme, the challenges in PCB wiring can be better solved, and the quality and consistency of wiring results are improved.

In summary, implementations of the present disclosure have significant beneficial effects, including improving routing efficiency and solving PCB uniform routing problems. By adopting GPU reasoning and a model-based acceleration scheme, the advantages of modern computing resources can be fully exerted, the efficiency and accuracy of a wiring algorithm are improved, and the progress in the field of electronic design automation is promoted.

FIG. 5 schematically illustrates a block diagram of a training system of a recommended region generation algorithm model according to an embodiment of the disclosure.

As shown in fig. 5, the training system 500 of the recommended region generation algorithm model includes: a test question generation module 510, a routing module 520, a recommended region generation module 530, and a training module 540.

A test question generation module 510 for generating PCB test questions with different constraint parameters using a PCB question generation tool. According to an embodiment of the present disclosure, the test problem generating module 510 may be used to perform the step S210 described above with reference to fig. 2, for example, and will not be described herein.

A routing module 520 for routing PCB test problems using the Astar algorithm. The routing module 520 may be used, for example, to perform the step S220 described above with reference to fig. 2, according to an embodiment of the present disclosure, which is not described herein.

The recommended region generating module 530 is configured to randomly select a line from the result of the wiring as a line to be learned, generate a recommended region suitable for connecting to the line to be learned by using a recommended region generating tool based on the Lee algorithm, and obtain a recommended region-line to be learned data set. The recommended region generation module 530 may be used, for example, to perform the step S230 described above with reference to fig. 2 according to an embodiment of the present disclosure, which is not described herein.

The training module 540 is configured to divide the data set into a training set and a testing set, input the training set into the deep recommendation area generation network, and perform training to obtain an optimized deep recommendation area generation network. The training module 540 may be used, for example, to perform the step S240 described above with reference to fig. 2, according to an embodiment of the present disclosure, which is not described herein.

It should be noted that any number of modules, sub-modules, units, sub-units, or at least some of the functionality of any number of the modules, sub-modules, units, or sub-units may be implemented in one module according to embodiments of the present disclosure. Any one or more of the modules, sub-modules, units, sub-units according to embodiments of the present disclosure may be implemented as split into multiple modules. Any one or more of the modules, sub-modules, units, sub-units according to embodiments of the present disclosure may be implemented at least in part as a hardware circuit, such as a Field Programmable Gate Array (FPGA), a Programmable Logic Array (PLA), a system-on-chip, a system-on-substrate, a system-on-package, an Application Specific Integrated Circuit (ASIC), or in any other reasonable manner of hardware or firmware that integrates or encapsulates the circuit, or in any one of or a suitable combination of three of software, hardware, and firmware. Alternatively, one or more of the modules, sub-modules, units, sub-units according to embodiments of the present disclosure may be at least partially implemented as computer program modules, which when executed, may perform the corresponding functions.

For example, any of the test question generation module 510, the wiring module 520, the recommended region generation module 530, and the training module 540 may be combined in one module to be implemented, or any of the modules may be split into a plurality of modules. Alternatively, at least some of the functionality of one or more of the modules may be combined with at least some of the functionality of other modules and implemented in one module. According to embodiments of the present disclosure, at least one of the test problem generation module 510, the routing module 520, the recommended region generation module 530, and the training module 540 may be implemented at least in part as hardware circuitry, such as a Field Programmable Gate Array (FPGA), a Programmable Logic Array (PLA), a system on a chip, a system on a substrate, a system on a package, an Application Specific Integrated Circuit (ASIC), or may be implemented in hardware or firmware in any other reasonable manner of integrating or packaging the circuitry, or in any one of or a suitable combination of three of software, hardware, and firmware. Alternatively, at least one of the test question generation module 510, the wiring module 520, the recommended region generation module 530, and the training module 540 may be at least partially implemented as a computer program module that, when executed, may perform the corresponding functions.

Fig. 6 schematically shows a block diagram of an electronic device adapted to implement the method described above, according to an embodiment of the disclosure. The electronic device shown in fig. 6 is merely an example and should not be construed to limit the functionality and scope of use of the disclosed embodiments.

As shown in fig. 6, the electronic device 600 described in the present embodiment includes: a processor 601 which can execute various appropriate actions and processes according to a program stored in a Read Only Memory (ROM) 602 or a program loaded from a storage section 608 into a Random Access Memory (RAM) 603. The processor 601 may include, for example, a general purpose microprocessor (e.g., a CPU), an instruction set processor and/or an associated chipset and/or a special purpose microprocessor (e.g., an Application Specific Integrated Circuit (ASIC)), or the like. Processor 601 may also include on-board memory for caching purposes. The processor 601 may comprise a single processing unit or a plurality of processing units for performing different actions of the method flows according to embodiments of the disclosure.

In the RAM 603, various programs and data required for the operation of the system 600 are stored. The processor 601, the ROM 602, and the RAM 603 are connected to each other through a bus 604. The processor 601 performs various operations of the method flow according to the embodiments of the present disclosure by executing programs in the ROM 602 and/or the RAM 603. Note that the program may be stored in one or more memories other than the ROM 602 and the RAM 603. The processor 601 may also perform various operations of the method flow according to embodiments of the present disclosure by executing programs stored in one or more memories.

According to an embodiment of the present disclosure, the electronic device 600 may also include an input/output (I/O) interface 605, the input/output (I/O) interface 605 also being connected to the bus 604. The system 600 may also include one or more of the following components connected to the I/O interface 605: an input portion 606 including a keyboard, mouse, etc.; an output portion 607 including a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), and the like, a speaker, and the like; a storage section 608 including a hard disk and the like; and a communication section 609 including a network interface card such as a LAN card, a modem, or the like. The communication section 609 performs communication processing via a network such as the internet. The drive 610 is also connected to the I/O interface 605 as needed. Removable media 611 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is installed as needed on drive 610 so that a computer program read therefrom is installed as needed into storage section 608.

According to embodiments of the present disclosure, the method flow according to embodiments of the present disclosure may be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable storage medium, the computer program comprising program code for performing the method shown in the flowcharts. In such an embodiment, the computer program may be downloaded and installed from a network through the communication portion 609, and/or installed from the removable medium 611. The above-described functions defined in the system of the embodiments of the present disclosure are performed when the computer program is executed by the processor 601. The systems, devices, apparatus, modules, units, etc. described above may be implemented by computer program modules according to embodiments of the disclosure.

The present disclosure also provides a computer-readable storage medium that may be embodied in the apparatus/device/system described in the above embodiments; or may exist alone without being assembled into the apparatus/device/system. The computer-readable storage medium carries one or more programs that, when executed, implement a training method of a recommended region generation algorithm model according to an embodiment of the present disclosure.

According to embodiments of the present disclosure, the computer-readable storage medium may be a non-volatile computer-readable storage medium, which may include, for example, but is not limited to: a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In an embodiment of the present disclosure, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. For example, according to embodiments of the present disclosure, the computer-readable storage medium may include ROM602 and/or RAM 603 and/or one or more memories other than ROM602 and RAM 603 described above.

Embodiments of the present disclosure also include a computer program product comprising a computer program containing program code for performing the methods shown in the flowcharts. The program code, when executed in a computer system, is operative to cause the computer system to implement a training method for a recommended region generation algorithm model provided by embodiments of the present disclosure.

The above-described functions defined in the system/apparatus of the embodiments of the present disclosure are performed when the computer program is executed by the processor 601. The systems, apparatus, modules, units, etc. described above may be implemented by computer program modules according to embodiments of the disclosure.

In one embodiment, the computer program may be based on a tangible storage medium such as an optical storage device, a magnetic storage device, or the like. In another embodiment, the computer program may also be transmitted, distributed in the form of signals over a network medium, and downloaded and installed via the communication section 609, and/or installed from the removable medium 611. The computer program may include program code that may be transmitted using any appropriate network medium, including but not limited to: wireless, wired, etc., or any suitable combination of the foregoing.

In such an embodiment, the computer program may be downloaded and installed from a network through the communication portion 609, and/or installed from the removable medium 611. The above-described functions defined in the system of the embodiments of the present disclosure are performed when the computer program is executed by the processor 601. The systems, devices, apparatus, modules, units, etc. described above may be implemented by computer program modules according to embodiments of the disclosure.

According to embodiments of the present disclosure, program code for performing computer programs provided by embodiments of the present disclosure may be written in any combination of one or more programming languages, and in particular, such computer programs may be implemented in high-level procedural and/or object-oriented programming languages, and/or assembly/machine languages. Programming languages include, but are not limited to, such as Java, c++, python, "C" or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, partly on a remote computing device, or entirely on the remote computing device or server. In the case of remote computing devices, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., connected via the Internet using an Internet service provider).

It should be noted that, each functional module in each embodiment of the present disclosure may be integrated into one processing module, or each module may exist alone physically, or two or more modules may be integrated into one module. The integrated modules may be implemented in hardware or in software functional modules. The integrated modules, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present disclosure may be embodied in the form of a software product, either in essence or as a part of the prior art or all or part of the technical solution.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Those skilled in the art will appreciate that the features recited in the various embodiments of the disclosure and/or in the claims may be combined in various combinations and/or combinations, even if such combinations or combinations are not explicitly recited in the disclosure. In particular, the features recited in the various embodiments of the present disclosure and/or the claims may be variously combined and/or combined without departing from the spirit and teachings of the present disclosure. All such combinations and/or combinations fall within the scope of the present disclosure.

While the present disclosure has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. The scope of the disclosure should, therefore, not be limited to the above-described embodiments, but should be determined not only by the following claims, but also by the equivalents of the following claims.

Claims (10)

1. A training method of a recommended region generation algorithm model, comprising:

generating PCB test questions with different constraint parameters by using a PCB question generation tool;

Wiring the PCB test problem by using an Astar algorithm;

randomly selecting a line from the wiring result as a line to be learned, and generating a recommended region suitable for being connected with the line to be learned by using a recommended region generating tool based on a Lee algorithm to obtain a recommended region-line to be learned data set;

and dividing the data set into a training set and a testing set, inputting the training set and the testing set into a deep recommended region generating network for training, and obtaining an optimized deep recommended region generating network.

2. The method of claim 1, wherein generating PCB test questions with different constraint parameters using a PCB question generation tool comprises:

inputting parameters required for generating the PCB test problem;

randomly generating bonding pads by using uniform distribution;

the positions of the bonding pads are adjusted through a gravity potential field method so as to reduce the probability of contact with adjacent bonding pads;

randomly generating obstacles by using uniform distribution;

and connecting the bonding pads through random selection to form complete PCB wiring, and generating PCB test problems with different constraint parameters.

3. The method of training a recommended region generation algorithm model of claim 1, wherein the routing the PCB test problem using the Astar algorithm comprises:

Initializing the PCB test problem; wherein the PCB test problem includes pad locations, routing areas, and constraints;

according to the initial state of the current PCB test problem, performing path searching and optimizing by utilizing the Astar algorithm;

generating an optimal path according to the physical limitation of the wiring, the signal transmission requirement and the constraint condition;

updating the status of the PCB test problem, including routed lines and connection status;

repeating the wiring steps until all the circuits are successfully wired, and finishing the wiring operation.

4. The training method of the recommended region generation algorithm model according to claim 1, wherein the generating a recommended region suitable for connecting the line to be learned using a Lee algorithm-based recommended region generation tool includes:

randomly selecting a line from the wiring result as a line to be learned, and marking the line to be learned as a state to be learned;

using a recommended region generating tool based on a Lee algorithm, taking undeleted circuits and bonding pads as input, and generating a recommended region suitable for connecting the circuits to be learned;

taking the recommended region and the line to be learned as the output of training data, and ensuring that the corresponding relationship between the recommended region and the line to be learned is accurate;

Selecting different lines to be learned, and repeating the step of generating the recommended region to generate the required number of data sets.

5. The training method of the recommended region generation algorithm model according to claim 1, wherein the dividing the data set into a training set and a test set, and inputting the recommended region generation network for training comprises:

randomly selecting a part of the generated data set as a training set, and randomly selecting a part of the generated data set as a test set, so as to ensure that the quantity of the training set and the quantity of the test set are in a preset proportion;

processing the training set by using the deep recommended region generation network, and training parameters of the deep recommended region generation network by using a back propagation and optimization algorithm according to the processing result of the training set to obtain a trained deep recommended region generation network;

processing the test set by using the trained deep recommendation area generating network to obtain the score of each trained deep recommendation area generating network, and obtaining an optimized deep recommendation area generating network according to the score;

the convolution layer number of the deep recommended region generation network is 28 layers, and the total connection layer number is 3 layers.

6. A PCB routing method, comprising:

acquiring a wiring problem to be processed, and inputting a current line and other bonding pads in the wiring problem to be processed as barriers into an optimized deep recommendation area generating network to obtain a recommendation area; wherein the optimized deep recommended region generation network is obtained according to the training method of the recommended region generation algorithm model according to any one of claims 1-5;

inputting the recommended area and the current line into an Astar algorithm to obtain an updated line, and completing the wiring process.

7. A training system for a recommended region generation algorithm model, comprising:

the test problem generating module is used for generating PCB test problems with different constraint parameters by utilizing the PCB problem generating tool;

the wiring module is used for wiring the PCB test problem by using an Astar algorithm;

the recommendation area generating module is used for randomly selecting a line from the wiring result as a line to be learned, and generating a recommendation area suitable for being connected with the line to be learned by using a recommendation area generating tool based on a Lee algorithm to obtain a recommendation area-line to be learned data set;

The training module is used for dividing the data set into a training set and a testing set, inputting the training set and the testing set into the deep recommended region generating network for training, and obtaining the optimized deep recommended region generating network.

8. An electronic device, comprising:

one or more processors;

storage means for storing one or more programs,

wherein the one or more programs, when executed by the one or more processors, cause the one or more processors to perform the training method of the recommended region generation algorithm model of any of claims 1-5.

9. A computer readable storage medium having stored thereon executable instructions which when executed by a processor cause the processor to perform a training method of a recommended region generation algorithm model according to any of claims 1 to 5.

10. A computer program product comprising a computer program which when executed by a processor implements a training method of a recommended region generation algorithm model according to any one of claims 1 to 5.