CN117313603A - Timing violation processing method, device and medium - Google Patents
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Abstract
The invention relates to the technical field of integrated circuit design, and discloses a method, a device and a medium for processing time sequence violations. Compared with the problem that time is wasted because the position of the bounding box needs to be adjusted for many times when the time sequence problem is solved by limiting the position of the register in the related art, different time sequence convergence distances are set for different clock sizes in the method, after the target repair path is confirmed, the time sequence convergence distance between the transmitting point register and the receiving point register corresponding to the clock size of the target repair path is determined based on the corresponding relation between the clock size and the time sequence convergence distance, so that the bounding box is created at the position that the distance between the transmitting point register and the receiving point register is smaller than the time sequence convergence distance, and the time sequence violation processing is realized. According to the invention, multiple attempts are not required to be made on the positions of the bounding boxes, and the distance relation between the bounding boxes and the register for different clock sizes is confirmed according to the corresponding relation table, so that the experimental and debugging processes are reduced, and the processing efficiency is improved.
Description
Technical Field
The present invention relates to the field of integrated circuit design technologies, and in particular, to a method, an apparatus, and a medium for processing timing violations.
Background
Logic synthesis is the process of converting a behavioral level description of a circuit, in particular a register transfer level (Register Transfer Level, RTL) description, into a gate level representation. Logic synthesis is driven by various constraints including operating environment, time, area, power consumption, etc. The ultimate goal of the synthesis is to produce results that meet these constraints, most importantly timing constraints, often referred to as timing closure, which is the most important goal of the synthesis.
In the related art, when the timing violation is solved, the designated logic units are placed in the created unit constraint boxes through instructions in a matched electronic design automation (Electronic Design Automation, EDA) tool, so that the layout is optimized, and the timing problem is solved. However, due to the problem of the distance between the transmitting point register and the receiving point register, the distance between the unit constraint frame and the transmitting point register and the receiving point register needs to be adjusted step by step when the position of the unit constraint frame is set, and the method requires a great deal of experiments and debugging and consumes great time and energy.
It can be seen that how to implement a simpler timing violation solution is a problem to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a method, a device and a medium for processing time sequence violations, which are used for solving the problem that time is consumed because the positions of constraint frames need to be adjusted for a plurality of times when the positions of registers are limited to solve the time sequence problem in the related art.
In order to solve the above technical problems, the present invention provides a method for processing timing violations, including:
acquiring a time sequence path of each time sequence unit;
confirming a target repair path from each of the timing paths;
acquiring a corresponding relation between the clock size of the target repair path and the distance between an emission point register and a receiving point register, and determining the time sequence convergence distance between the emission point register and the receiving point register corresponding to the clock size of the target repair path based on the corresponding relation;
creating a bounding box at a position where the distance between the transmitting point register and the receiving point register is smaller than the timing sequence convergence distance according to the timing sequence convergence distance;
wherein the distance between the transmitting point register and the receiving point register comprises: the direct distance between the transmitting point register and the receiving point register, or the sum of the distances between the transmitting point register and the receiving point register and the logic unit passing between the transmitting point register and the receiving point register.
In some implementations, the bounding boxes include a cell bounding box and a logical cell bounding box;
further, the creating a bounding box at a distance between the transmitting point register and the receiving point register that is less than the timing convergence distance according to the timing convergence distance comprises:
judging whether the direct distance between the transmitting point register and the receiving point register exceeds the timing sequence convergence distance;
if the time sequence convergence distance exceeds the time sequence convergence distance, creating the unit constraint frame to place the receiving point register;
if the time sequence convergence distance is not exceeded, judging whether the sum of the distances between the logic unit passing through the middle of the transmitting point register and the receiving point register and the transmitting point register exceeds the time sequence convergence distance; if yes, creating the logic unit bounding box at the position that the sum of the distances does not exceed the timing convergence distance so as to place a target logic unit.
In one aspect, validating the target repair path includes:
obtaining the corresponding violation value of each time sequence unit;
sorting the violation values;
confirming that the time sequence unit with the maximum violation value is a target time sequence unit;
And confirming the path in the target time sequence unit as the target repair path.
In another aspect, placing the target logical unit in the logical unit bounding box includes:
confirming the hierarchy name of a target hierarchy in a logic unit passing through the middle of the transmitting point register and the receiving point register;
and placing the logic units with the same hierarchical name as the target logic units in the logic unit bounding box.
In some implementations, the size of the cell bounding box is a first preset multiple of the size of the receive point register area;
the size of the logic unit constraint frame is a second preset multiple of the area size of the target logic unit; the values of the first preset multiple and the second preset multiple are both larger than or equal to 1.
In other implementations, after the step of creating a bounding box at a distance between the transmit point register and the receive point register that is less than the timing convergence distance according to the timing convergence distance, further comprising:
judging whether the time sequence of the target repair path is converged or not;
if not, moving the unit constraint frame to the direction of the emission point register according to the minimum moving distance, and returning to the step of judging whether the time sequence of the target repair path is converged;
If yes, determining that the creation position of the constraint frame meets the requirement.
In one aspect, after the step of creating a bounding box at a distance between the transmit point register and the receive point register that is less than the timing convergence distance according to the timing convergence distance, the method further comprises:
judging whether a violation exists between the transmitting point register and the logic unit constraint frame or between the logic unit constraint frame and the receiving point register;
if yes, moving the logic unit constraint frame to one side with more buffers according to the minimum moving distance, and returning to the step of judging whether a violation exists between the transmitting point register and the logic unit constraint frame or between the logic unit constraint frame and the receiving point register;
if not, determining that the creation position of the bounding box meets the requirement.
On the other hand, in the case where there is still a violation in the timing path through the logical unit bounding box, it further includes:
judging whether the time sequence of a path opposite to the time sequence path of the violation is positive or not;
if yes, moving the logic unit bounding box to the direction of the emission point register according to the minimum moving distance; returning to the step of judging whether the time sequence of the path opposite to the time sequence path of the violation is positive or not until the violation is cleared;
If negative, readjust the floor plan.
In some embodiments, the timing path includes a setup time path and a hold time path;
the time formula for the data to reach in the established time path is as follows:
T arrive ＝T launch +T ck2q +T dp ；
wherein T is arrive Data arrival time, T launch For the time required for the clock source to reach the first register, T ck2q For the time of data transfer in the first register, T dp Time required for data to be sent from the first register to the second register;
the time required to establish the time path is:
T require ＝T capture +T cycle -T setup ；
wherein T is require To require time, T capture Data acquisition time, T cycle For cycle time, T setup Setting time for the data;
the time formula is established as follows:
T launch +T ck2q +T dp ＝T capure +T cycle -T setup ；
T setup slack ＝T require -T arrive ＞0；
the time required to maintain the time path is:
T arrive ＝T launch +T ck2q +T dp ；
T require ＝T capture +T hold ；
T hold_slack ＝T arrive -T require ＞0；
wherein T is setup slack To establish a time margin, T hold Data retention time, T hold_slack To maintain a time margin.
In order to solve the above technical problem, the present invention further provides a timing violation processing device, including:
the acquisition module is used for acquiring the time sequence path of each time sequence unit;
a confirmation module for confirming a target repair path from each of the timing paths;
the processing module is used for acquiring the corresponding relation between the clock size of the target repair path and the distance between the transmitting point register and the receiving point register, and determining the time sequence convergence distance between the transmitting point register and the receiving point register corresponding to the clock size of the target repair path based on the corresponding relation; wherein the distance between the transmitting point register and the receiving point register comprises: the direct distance between the transmitting point register and the receiving point register, or the sum of the distances between the transmitting point register and the receiving point register and the logic unit passing through between the transmitting point register and the receiving point register;
And the creation module is used for creating a bounding box at a position where the distance between the transmitting point register and the receiving point register is smaller than the timing sequence convergence distance according to the timing sequence convergence distance.
In order to solve the technical problem, the invention also provides another timing violation processing device, which comprises a memory for storing a computer program;
and a processor for implementing the steps of the timing violation processing method as described above when executing the computer program.
To solve the above technical problem, the present invention further provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor, implements the steps of the timing violation processing method as described above.
The time sequence violation processing method provided by the invention comprises the following steps: acquiring a time sequence path of each time sequence unit; confirming a target repair path from each time sequence path; acquiring a corresponding relation between the clock size of the target repair path and the distance between the transmitting point register and the receiving point register, and determining the time sequence convergence distance between the transmitting point register and the receiving point register corresponding to the clock size of the target repair path based on the corresponding relation; creating a bounding box at a position where the distance between the transmitting point register and the receiving point register is smaller than the timing sequence convergence distance according to the timing sequence convergence distance; wherein, the distance between the emission point register and the receiving point register includes: the direct distance between the transmitting point register and the receiving point register, or the sum of the distances between the transmitting point register and the receiving point register and the logic unit passing through between the transmitting point register and the receiving point register.
Compared with the related art, the invention has the following beneficial effects: according to the method, different time sequence convergence distances are set for different clock sizes, after the target repair path is confirmed, the time sequence convergence distance between the transmitting point register and the receiving point register corresponding to the clock size of the target repair path is determined based on the corresponding relation between the clock size and the time sequence convergence distance, so that a constraint frame is created at the position where the distance between the transmitting point register and the receiving point register is smaller than the time sequence convergence distance, and time sequence violation processing is realized. According to the invention, multiple attempts are not required to be made on the positions of the bounding boxes, and the distance relation between the bounding boxes and the register for different clock sizes is confirmed according to the corresponding relation table, so that the experimental and debugging processes are reduced, the data processing amount is reduced, and the processing efficiency is improved.
In addition, the timing violation processing device and the medium provided by the invention correspond to the timing violation processing method and have the same effects.
Drawings
For a clearer description of embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1 is a flow chart of a timing violation processing method according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a path according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a violation path provided by an embodiment of the present invention;
FIG. 4 is a schematic view of the bounding box setup position of the path shown in FIG. 3;
FIG. 5 is a schematic diagram of another exemplary offending path provided by an embodiment of the present invention;
FIG. 6 is a schematic view of the bounding box setup position of the path shown in FIG. 5;
FIG. 7 is a block diagram of a timing violation processing device according to an embodiment of the present invention;
fig. 8 is a block diagram of another timing violation processing device according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without making any inventive effort are within the scope of the present invention.
Logic synthesis is the process of converting an RTL level circuit in hardware description language into a circuit level netlist from a library of basic circuit cells provided by the chip manufacturer using a synthesis tool Design Compiler. Logic synthesis is driven by various constraints including operating environment, time, area, power consumption, etc. The ultimate goal of the synthesis is to produce results that meet these constraints, most importantly timing constraints, often referred to as timing closure, which is the most important goal of the synthesis. The quality of logic synthesis directly affects the performance, area and power consumption of the digital system.
In the whole digital back-end implementation process, various verifications are required to be performed to ensure the final normal operation of the chip. Timing convergence is a very important feature to ensure that the chip can achieve a given performance index for a product definition under specific process, voltage, temperature (Process, voltage, temperature, PVT) conditions. For synchronous digital circuits, the paths and delays of clocks reaching each time sequence unit are ensured to be consistent, so the position of a time sequence problem in the back-end design is very important, and the main work of the link is to check two time sequence parameters of the setup time and the hold time.
In the related art, the time sequence problem caused by the fact that the position of a register for transmitting data starting point is too far away from the position of a register for receiving data end point occurs in the logic synthesis process aiming at digital back-end tape floor planning can be solved by limiting the position of the register by adopting an instruction create_bound in a Design Compiler tool. However, a number of different timing path violations may occur in a set of timing problems, which can be divided into two cases. The first case is that the transmitting point register and the receiving point register are at the same position, and the logic passing through in the middle is at a far position, so that the path of the transmitting point register which is firstly transmitted to the middle logic and then returned to the receiving point register is too long, and the second case is that the transmitting point register and the receiving point register are far away, and the receiving point register has a data transmission relation with a far distance, so that the time sequence requirements of two sides are required to be met. In summary, it is difficult to solve all the path problems only by one time create_bound, and a designer often can solve the timing problem by adjusting the position and size of the unit bounding box multiple times. And according to the time sequence result analysis after each adjustment, the position and the size of the next unit bounding box are optimized, and the process consumes time and energy of designers.
The core of the invention is to provide a method, a device and a medium for processing time sequence violations, which are used for solving the problem of time consumption caused by the fact that the positions of constraint frames need to be adjusted for many times when the positions of registers are limited to solve the time sequence problem in the related art.
In order to better understand the aspects of the present invention, the present invention will be described in further detail with reference to the accompanying drawings and detailed description.
Fig. 1 is a flowchart of a timing violation processing method according to an embodiment of the present invention, where, as shown in fig. 1, the method includes:
s10: acquiring a time sequence path of each time sequence unit;
s11: confirming a target repair path from each time sequence path;
s12: acquiring a corresponding relation between the clock size of the target repair path and the distance between the transmitting point register and the receiving point register, and determining the time sequence convergence distance between the transmitting point register and the receiving point register corresponding to the clock size of the target repair path based on the corresponding relation;
s13: creating a bounding box at a position where the distance between the transmitting point register and the receiving point register is smaller than the timing sequence convergence distance according to the timing sequence convergence distance;
wherein, the distance between the emission point register and the receiving point register includes: the direct distance between the transmitting point register and the receiving point register, or the sum of the distances between the transmitting point register and the receiving point register and the logic unit passing through between the transmitting point register and the receiving point register.
The timing violation processing method provided by the invention is applied to the timing violation processing device, and an execution main body of the timing violation processing device is a processor, and is used for realizing the design of an integrated circuit. The timing violation processing method provided by the invention can be applied to the inspection stage of an integrated circuit such as a chip and is used for inspecting and correcting the timing problem of the chip. The above embodiments describe that the checking for timing problems is achieved by checking both the setup time and the hold time timing parameters. The definition of Setup Time (Setup Time) is: for the units of timing analysis, the data must remain stable for a minimum time before the clock trigger edge arrives. The checking of the setup time is to ensure that the timing unit can stably collect the data sent by the previous timing unit. The path for establishing time inspection is divided into a transmitting path and a capturing path, wherein the transmitting path is from a clock source to a D end of a second-stage register, the capturing path is from the clock source to the clock end of the second-stage register, the time inspection can be met only by ensuring that the capturing path delay of the second-stage register is longer than the transmitting path delay, and the establishing time is calculated in the delay of the capturing path as a subtraction. The check of the hold time means that the data input signal has to remain stable for a minimum time after the clock active edge. The data signal needs to remain stable for a while after the instant clock signal arrives. Hold time checking to ensure that new data does not reach the receiving register D-side too early before the flip-flop stabilizes the output of the initial data.
Fig. 2 is a schematic diagram of a path provided by an embodiment of the present invention, as shown in the drawing, for establishing a time path, a formula of time required for data arrival is:
T arrive ＝T launch +T ck2q +T dp ；
wherein T is arrive Data arrival time, T launch For the time required for the clock source to reach the first register, T ck2q For the time of data transfer in the first register, T dp Time required for data to be sent from the first register to the second register;
the time required to establish the time path is:
T require ＝T capture +T cycle -T setup ；
wherein T is require To require time, T capture Data acquisition time, T cycle For cycle time, T setup A time is set for the data.
The time formula is established as follows:
T launch +T ck2q +T dp ＝T capture +T chcle -T setup ；
T setup slack ＝T require -T arrive ＞0；
for the check of hold time, the time required to hold the time path is:
T arrive ＝T launch +T ck2q +T dp ；
T require ＝T capture +T hold ；
T hold_slack ＝T arrive -T require ＞0；
wherein T is setup slack To establish a time margin, T hold Data retention time, T hold_slack To maintain a time margin.
As can be seen from the above, when the setup time margin and the hold time margin are negative, a timing violation occurs, thereby affecting the performance of the chip, and possibly causing a problem in the actual operation of the chip.
The setup time violation is typically caused by the combinational logic being too long or the distance between the transmit point register that sent the data and the receive point register that received the data being too long. Evaluating whether the path meets the setup Time requirement may calculate a Time margin (Time slot) that includes a setup Time margin and a hold Time margin (setup slot and hold slot). The time margin is regular to meet timing convergence, negative meaning that a timing violation occurs, which is a risk, although individual violations do not represent a fatal problem for the chip. When the number of violations is large, the probability that the design will have a problem in the actual environment is also larger.
The target repair path in this embodiment is a path with timing violations. It will be appreciated that for a chip comprising a plurality of sequential cells, there are a plurality of paths in each sequential cell, the paths in each sequential cell may be interleaved with the paths in other sequential cells, and timing violations of one path may affect the operation of other cells. Therefore, in the implementation, when the violations of the chip are eliminated, the timing sequence units with the most violations can be repaired first, and the timing sequence units are sequentially subjected to the violations according to the sequence of at least more violations, so that the influence on other paths when the violations are eliminated is reduced. Specifically, before processing, statistics and ordering of the violations in each sequential unit are required to identify the first sequential unit to be processed. In this embodiment, the timing violation processing method further includes: obtaining the corresponding violation value of each time sequence unit; sorting the violation values; confirming that the time sequence unit with the maximum violation value is a target time sequence unit; and confirming the path in the target time sequence unit as a target repair path. The violation value in this embodiment may be a number characterizing the violation paths that occur in the timing unit, and the sorting is achieved by comparing the values. After the target time sequence unit is confirmed, the violation path is the target repair path, and in the implementation, the target repair path can be ordered according to specific conditions of the violation path, such as path length, the number of passing logic units, and the like.
Compared with the problem that time is wasted because the position of a binding frame needs to be adjusted for many times when the position of a register is limited to solve the time sequence problem in the related art, different time sequence convergence distances are set for different clock sizes, after a target repair path is confirmed, the time sequence convergence distance between a transmitting point register and a receiving point register corresponding to the clock size of the target repair path is determined based on the corresponding relation between the clock size and the time sequence convergence distance, and therefore the binding frame is created at the position that the distance between the transmitting point register and the receiving point register is smaller than the time sequence convergence distance, and time sequence violation processing is achieved. According to the invention, multiple attempts are not required to be made on the positions of the bounding boxes, and the distance relation between the bounding boxes and the register for different clock sizes is confirmed according to the corresponding relation table, so that the experimental and debugging processes are reduced, the data processing amount is reduced, and the processing efficiency is improved.
As can be seen from the description of the above embodiments, the reason why the timing violation is caused in the implementation may be that the direct distance between the transmitting point register and the receiving point register is too long, or that the path required by the logic unit passing between the transmitting point register and the receiving point register is too long, so that the position setting needs to be performed according to different situations when the bounding box is created. The embodiment provides a specific creation method, in which the bounding box includes a unit bounding box and a logic unit bounding box; further, creating the bounding box at a distance between the transmit point register and the receive point register that is less than the timing closure distance according to the timing closure distance comprises: judging whether the direct distance between the transmitting point register and the receiving point register exceeds the timing sequence convergence distance; if the time sequence convergence distance exceeds the time sequence convergence distance, a unit constraint frame is established to place a receiving point register; if the time sequence convergence distance is not exceeded, judging whether the sum of the distances between the logic unit passing through the middle of the transmitting point register and the receiving point register and the transmitting point register exceeds the time sequence convergence distance; if so, creating a logic unit bounding box at a position where the sum of the distances does not exceed the timing convergence distance to place the target logic unit.
In this embodiment, after the target repair path is confirmed, the corresponding clock size may also be determined, based on the corresponding relationship between the clock size and the distance between the transmitting point register and the receiving point register, the timing sequence convergence distance between the transmitting point register and the receiving point register may be determined, and the timing sequence violation may be eliminated by setting the bounding box within the timing sequence convergence distance. Wherein, the distance between the emission point register and the receiving point register includes: the direct distance between the transmitting point register and the receiving point register, or the sum of the distances between the transmitting point register and the receiving point register and the logic unit passing through between the transmitting point register and the receiving point register. Fig. 3 is a schematic diagram of an offending path provided by the embodiment of the present invention, as shown in fig. 3, for example, a clock corresponding to a path between a transmitting point register and a receiving point register is 500M, and according to a corresponding relationship, it is obtained that a timing convergence distance between the transmitting point register and the receiving point register should be 2000 micrometers, and then the timing convergence distance is created within 2000 micrometers when creating a bounding box to place the receiving point register, and fig. 4 is a schematic diagram of a bounding box setting position of the path shown in fig. 3. Fig. 5 is a schematic diagram of another violation path provided by an embodiment of the present invention, in which a logic unit passing between an emission point register and a receiving point register and a sum of distances between the emission point register and the receiving point register exceeds 2000 micrometers, and the distances are created within 2000 micrometers after creating a bounding box to place the logic unit. FIG. 6 is a schematic view of the bounding box setup position of the path shown in FIG. 5.
It will be appreciated that there may be a plurality of logic cells between the transmit point register and the receive point register, and that different logic cells form different logic levels, wherein a portion of the logic cells are the underlying cells that must pass between the transmit point register and the receive point register, and that the portion of the logic cells need to be placed within the logic cell bounding box when the logic cell bounding box is set. Specifically, based on the above embodiment, in this embodiment, placing the target logical unit in the logical unit bounding box includes: confirming the hierarchy name of a target hierarchy in a logic unit passing through the middle of the transmitting point register and the receiving point register; and placing the logic units with the same hierarchical name as target logic units in a logic unit bounding box.
In this embodiment, when the logic units are placed, the logic units at the bottom layer are placed in the logic unit constraint frame, instead of placing all the logic units inside, so that the area setting in the logic unit constraint frame is reduced. When the size of the constraint frame is actually set, the size of the unit constraint frame is a first preset multiple of the area size of the register of the receiving point; the size of the logic unit constraint frame is a second preset multiple of the area size of the target logic unit; the values of the first preset multiple and the second preset multiple are both greater than or equal to 1.
After the step of creating a bounding box at a distance between the transmitting point register and the receiving point register that is less than the timing closure distance according to the timing closure distance, further comprising, as the registers may also have violations with other paths after the bounding box is set: judging whether the time sequence of the target repair path is converged or not; if not, moving the unit constraint frame to the direction of the transmitting point register according to the minimum moving distance, and returning to the step of judging whether the time sequence of the target repair path is converged; if so, determining that the creation position of the bounding box meets the requirement.
In the path of the transmitting point register passing through the logic unit and the receiving point register, after the position of the logic unit constraint frame is set, the violation may occur between the transmitting point register and the logic unit constraint frame or between the logic unit constraint frame and the receiving point register, and at this time, the position of the logic unit constraint frame needs to be adjusted to eliminate the violation in two directions. Specifically, after the step of creating the bounding box at the position where the distance between the transmitting point register and the receiving point register is smaller than the timing convergence distance according to the timing convergence distance, the method further includes: judging whether a violation exists between the transmitting point register and the logic unit constraint frame or between the logic unit constraint frame and the receiving point register; if yes, moving the logic unit constraint frame to one side with more buffers according to the minimum moving distance, and returning to the step of judging whether the violation exists between the transmitting point register and the logic unit constraint frame or between the logic unit constraint frame and the receiving point register; if not, determining that the creation position of the bounding box meets the requirement.
It will be appreciated that the presence of the buffer increases the time to transmit the data path, which can cause timing violations, and thus moves the logic unit bounding box to the more side of the buffer after a violation occurs, thereby eliminating the violation.
In the event that there is still a violation in the timing path through the logical unit bounding box, further comprising: judging whether the time sequence of a path opposite to the time sequence path of the violation is positive or not; if yes, moving the logic unit constraint frame to the direction of the transmitting point register according to the minimum moving distance; returning to the step of judging whether the time sequence of the path opposite to the time sequence path of the violation is positive or not until the violation is cleared; if negative, readjust the floor plan.
In the above embodiments, the detailed description is given to the timing violation processing method, and the invention also provides a corresponding embodiment of the timing violation processing device. It should be noted that the present invention describes an embodiment of the device portion from two angles, one based on the angle of the functional module and the other based on the angle of the hardware.
Fig. 7 is a block diagram of a timing violation processing device according to an embodiment of the present invention, where, as shown in fig. 7, the timing violation processing device includes:
An acquisition module 10, configured to acquire a timing path of each timing unit;
a confirming module 11 for confirming a target repair path from among the timing paths;
the processing module 12 is configured to obtain a corresponding relationship between a clock size of the target repair path and a distance between the transmitting point register and the receiving point register, and determine a timing sequence convergence distance between the transmitting point register and the receiving point register corresponding to the clock size of the target repair path based on the corresponding relationship; wherein, the distance between the emission point register and the receiving point register includes: the direct distance between the transmitting point register and the receiving point register, or the sum of the distances between the logic unit passing through the middle of the transmitting point register and the receiving point register and the transmitting point register and the receiving point register;
the creating module 13 is configured to create a bounding box at a position where the distance between the transmitting point register and the receiving point register is smaller than the timing convergence distance according to the timing convergence distance.
In some embodiments, the creation module includes:
the first judging module is used for judging whether the direct distance between the transmitting point register and the receiving point register exceeds the timing sequence convergence distance; if the time sequence convergence distance exceeds the time sequence convergence distance, a unit constraint frame is established to place a receiving point register; if the first judgment module is not exceeded, entering a second judgment module;
The second judging module is used for judging whether the sum of the distances between the logic unit passing through the middle of the transmitting point register and the receiving point register and the transmitting point register exceeds the timing sequence convergence distance; if so, creating a logic unit bounding box at a position where the sum of the distances does not exceed the timing convergence distance to place the target logic unit.
In other embodiments, the validation module includes:
the violation value acquisition module is used for acquiring violation values corresponding to the time sequence units;
the ordering module is used for ordering the violation values;
the target time sequence unit confirming module is used for confirming that the time sequence unit with the maximum violation value is the target time sequence unit;
and the target repair path confirming module is used for confirming that the path in the target time sequence unit is a target repair path.
Since the embodiments of the apparatus portion and the embodiments of the method portion correspond to each other, the embodiments of the apparatus portion are referred to the description of the embodiments of the method portion, and are not repeated herein.
Compared with the problem that time is wasted because the position of a binding frame needs to be adjusted for many times when the position of a register is limited to solve the time sequence problem in the related art, the time sequence violation processing device provided by the embodiment of the invention sets different time sequence convergence distances for different clock sizes, and after a target repair path is confirmed, the time sequence convergence distance between a transmitting point register and a receiving point register corresponding to the clock size of the target repair path is determined based on the corresponding relation between the clock size and the time sequence convergence distance, so that the binding frame is created at the position that the distance between the transmitting point register and the receiving point register is smaller than the time sequence convergence distance, and the time sequence violation processing is realized. According to the invention, multiple attempts are not required to be made on the positions of the bounding boxes, and the distance relation between the bounding boxes and the register for different clock sizes is confirmed according to the corresponding relation table, so that the experimental and debugging processes are reduced, the data processing amount is reduced, and the processing efficiency is improved.
Fig. 8 is a block diagram of another timing violation processing device according to an embodiment of the present invention, as shown in fig. 8, where the device includes: a memory 20 for storing a computer program;
the processor 21 is configured to implement the steps of the timing violation processing method described in the above embodiment when executing the computer program.
The timing violation processing device provided in the embodiment may include, but is not limited to, a smart phone, a tablet computer, a notebook computer, a desktop computer, or the like.
Processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 may be implemented in hardware in at least one of a digital signal processor (Digital Signal Processor, DSP), a Field programmable gate array (Field-Programmable Gate Array, FPGA), a programmable logic array (Programmable Logic Array, PLA). The processor 21 may also comprise a main processor, which is a processor for processing data in an awake state, also called central processor (Central Processing Unit, CPU), and a coprocessor; a coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 21 may be integrated with an image processor (Graphics Processing Unit, GPU) for taking care of rendering and rendering of the content that the display screen is required to display. In some embodiments, the processor 21 may also include an artificial intelligence (Artificial Intelligence, AI) processor for processing computing operations related to machine learning.
Memory 20 may include one or more computer-readable storage media, which may be non-transitory. Memory 20 may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 20 is at least used for storing a computer program 201, which, when loaded and executed by the processor 21, is capable of implementing the relevant steps of the timing violation processing method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may further include an operating system 202, data 203, and the like, where the storage manner may be transient storage or permanent storage. The operating system 202 may include Windows, unix, linux, among others. The data 203 may include, but is not limited to, timing closure distances, and the like.
In some embodiments, the timing violation processing device may further include a display 22, an input-output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.
Those skilled in the art will appreciate that the structure shown in fig. 8 does not constitute a limitation of the timing violation processing device and may include more or less components than illustrated.
The device for processing the time sequence violation provided by the embodiment of the invention comprises a memory and a processor, wherein the processor can realize the following method when executing a program stored in the memory: acquiring a time sequence path of each time sequence unit; confirming a target repair path from each time sequence path; acquiring a corresponding relation between the clock size of the target repair path and the distance between the transmitting point register and the receiving point register, and determining the time sequence convergence distance between the transmitting point register and the receiving point register corresponding to the clock size of the target repair path based on the corresponding relation; creating a bounding box at a position where the distance between the transmitting point register and the receiving point register is smaller than the timing sequence convergence distance according to the timing sequence convergence distance; wherein, the distance between the emission point register and the receiving point register includes: the direct distance between the transmitting point register and the receiving point register, or the sum of the distances between the transmitting point register and the receiving point register and the logic unit passing through between the transmitting point register and the receiving point register.
Finally, the invention also provides a corresponding embodiment of the computer readable storage medium. The computer-readable storage medium has stored thereon a computer program which, when executed by a processor, performs the steps as described in the method embodiments above.
It will be appreciated that the methods of the above embodiments, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored on a computer readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a storage medium for performing all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The method, the device and the medium for processing the time sequence violation provided by the invention are described in detail. In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the invention can be made without departing from the principles of the invention and these modifications and adaptations are intended to be within the scope of the invention as defined in the following claims.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Claims (12)
1. A method of timing violation processing, comprising:
acquiring a time sequence path of each time sequence unit;
confirming a target repair path from each of the timing paths;
acquiring a corresponding relation between the clock size of the target repair path and the distance between an emission point register and a receiving point register, and determining the time sequence convergence distance between the emission point register and the receiving point register corresponding to the clock size of the target repair path based on the corresponding relation;
Creating a bounding box at a position where the distance between the transmitting point register and the receiving point register is smaller than the timing sequence convergence distance according to the timing sequence convergence distance;
wherein the distance between the transmitting point register and the receiving point register comprises: the direct distance between the transmitting point register and the receiving point register, or the sum of the distances between the transmitting point register and the receiving point register and the logic unit passing between the transmitting point register and the receiving point register.
2. The timing violation processing method of claim 1, wherein the bounding box comprises a cell bounding box and a logical cell bounding box;
further, the creating a bounding box at a distance between the transmitting point register and the receiving point register that is less than the timing convergence distance according to the timing convergence distance comprises:
judging whether the direct distance between the transmitting point register and the receiving point register exceeds the timing sequence convergence distance;
if the time sequence convergence distance exceeds the time sequence convergence distance, creating the unit constraint frame to place the receiving point register;
if the time sequence convergence distance is not exceeded, judging whether the sum of the distances between the logic unit passing through the middle of the transmitting point register and the receiving point register and the transmitting point register exceeds the time sequence convergence distance; if yes, creating the logic unit bounding box at the position that the sum of the distances does not exceed the timing convergence distance so as to place a target logic unit.
3. The timing violation processing method of claim 2, wherein validating the target repair path comprises:
obtaining the corresponding violation value of each time sequence unit;
sorting the violation values;
confirming that the time sequence unit with the maximum violation value is a target time sequence unit;
and confirming the path in the target time sequence unit as the target repair path.
4. The timing violation processing method of claim 2, wherein placing the target logical unit in the logical unit bounding box comprises:
confirming the hierarchy name of a target hierarchy in a logic unit passing through the middle of the transmitting point register and the receiving point register;
and placing the logic units with the same hierarchical name as the target logic units in the logic unit bounding box.
5. The timing violation processing method according to any one of claims 2 to 4, wherein a size of the cell bounding box is a first preset multiple of an area size of the reception point register;
the size of the logic unit constraint frame is a second preset multiple of the area size of the target logic unit; the values of the first preset multiple and the second preset multiple are both larger than or equal to 1.
6. The timing violation processing method of claim 2, further comprising, after the step of creating a bounding box at a distance between the transmitting point register and the receiving point register that is less than the timing convergence distance according to the timing convergence distance:
judging whether the time sequence of the target repair path is converged or not;
if not, moving the unit constraint frame to the direction of the emission point register according to the minimum moving distance, and returning to the step of judging whether the time sequence of the target repair path is converged;
if yes, determining that the creation position of the constraint frame meets the requirement.
7. The timing violation processing method of claim 2, further comprising, after the step of creating a bounding box at a distance between the transmitting point register and the receiving point register that is less than the timing convergence distance according to the timing convergence distance:
judging whether a violation exists between the transmitting point register and the logic unit constraint frame or between the logic unit constraint frame and the receiving point register;
if yes, moving the logic unit constraint frame to one side with more buffers according to the minimum moving distance, and returning to the step of judging whether a violation exists between the transmitting point register and the logic unit constraint frame or between the logic unit constraint frame and the receiving point register;
If not, determining that the creation position of the bounding box meets the requirement.
8. The timing violation processing method of claim 2, further comprising, in the event that a violation still exists in a timing path through the logic unit bounding box:
judging whether the time sequence of a path opposite to the time sequence path of the violation is positive or not;
if yes, moving the logic unit bounding box to the direction of the emission point register according to the minimum moving distance; returning to the step of judging whether the time sequence of the path opposite to the time sequence path of the violation is positive or not until the violation is cleared;
if negative, readjust the floor plan.
9. The timing violation processing method of claim 1, wherein the timing path includes a setup time path and a hold time path;
the time formula for the data to reach in the established time path is as follows:
T arrive ＝T launch +T ck2q +T dp ；
wherein T is arrive Data arrival time, T launch For the time required for the clock source to reach the first register, T ck2q For the time of data transfer in the first register, T dp Time required for data to be sent from the first register to the second register;
the time required to establish the time path is:
T require ＝T capture +T cycle -T setup ；
wherein T is require To require time, T capture Data acquisition time, T cycle For cycle time, T setup Setting time for the data;
the time formula is established as follows:
T launch +T ck2q +T dp ＝T capture +T cycle -T setup ；
T setup slack ＝T require -T arrive ＞0；
the time required to maintain the time path is:
T arrive ＝T launch +T ck2q +T dp ；
T require ＝T capture +T hold ；
T hold_slack ＝T arrive -T require ＞0；
wherein T is setup slack To establish a time margin, T hold Data retention time, T hold_slack To maintain a time margin.
10. A timing violation processing apparatus, comprising:
the acquisition module is used for acquiring the time sequence path of each time sequence unit;
a confirmation module for confirming a target repair path from each of the timing paths;
the processing module is used for acquiring the corresponding relation between the clock size of the target repair path and the distance between the transmitting point register and the receiving point register, and determining the time sequence convergence distance between the transmitting point register and the receiving point register corresponding to the clock size of the target repair path based on the corresponding relation; wherein the distance between the transmitting point register and the receiving point register comprises: the direct distance between the transmitting point register and the receiving point register, or the sum of the distances between the transmitting point register and the receiving point register and the logic unit passing through between the transmitting point register and the receiving point register;
And the creation module is used for creating a bounding box at a position where the distance between the transmitting point register and the receiving point register is smaller than the timing sequence convergence distance according to the timing sequence convergence distance.
11. A timing violation processing device, comprising a memory for storing a computer program;
a processor for implementing the steps of the timing violation processing method according to any of the claims 1 to 9 when executing said computer program.
12. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program which, when executed by a processor, implements the steps of the timing violation processing method according to any of the claims 1 to 9.
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