CN117312187A - Method for improving operation efficiency of cache consistency mechanism - Google Patents
Method for improving operation efficiency of cache consistency mechanism Download PDFInfo
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- CN117312187A CN117312187A CN202311418036.7A CN202311418036A CN117312187A CN 117312187 A CN117312187 A CN 117312187A CN 202311418036 A CN202311418036 A CN 202311418036A CN 117312187 A CN117312187 A CN 117312187A
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- 230000007246 mechanism Effects 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title claims abstract description 15
- 230000008859 change Effects 0.000 claims description 7
- 230000007704 transition Effects 0.000 claims description 4
- 230000002427 irreversible effect Effects 0.000 claims description 2
- 238000012544 monitoring process Methods 0.000 claims description 2
- 238000012545 processing Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
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- 238000011084 recovery Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
- G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
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Abstract
The invention discloses a method for improving the operation efficiency of a cache consistency mechanism, and belongs to the field of data processing. The invention adds corresponding status bits in the directory of LLC, including private read, private read-write, shared read and shared read-write, and only carries out consistency operation for shared read-write status. The method and the device provide switching conditions among four states and a starting scheme of the consistency operation, and improve the operation efficiency of the multi-core consistency mechanism.
Description
Technical Field
The invention relates to the technical field of data processing, in particular to a method for improving the operation efficiency of a cache consistency mechanism.
Background
Modern computers often have multi-core processors, and multi-core consistency problems of data are involved when the multi-cores perform read-write operations on data stored in the same area. In general, each processor has a corresponding private cache, and how to synchronize data of each private cache when necessary is a core problem of multi-core consistency research.
Modern computers place higher demands on the operating efficiency of the multi-core coherency mechanism, which depends on the design of the cache coherency protocol. Unlike broadcast protocols, conventional cache coherency protocols track each block of cache. In that way, a backup of each cached block of data may be more easily located, but may also be redundant for many unnecessary operations. The consistency operation of deleting the cache blocks without consistency requirements is an effective means for improving the operation efficiency of a cache consistency mechanism.
Disclosure of Invention
The invention aims to provide a method for improving the operation efficiency of a cache consistency mechanism, so as to solve the problems in the background technology.
In order to solve the technical problems, the invention provides a method for improving the operation efficiency of a cache consistency mechanism, which comprises the following steps:
adding a 2bit LS state bit into a Tag RAM of LLC, indicating four states of private reading, private reading and writing, shared reading and writing, checking consistency request things initiated by LLC according to each processor to update state bit information in real time, and determining whether the block needs to execute consistency operations such as monitoring or not according to the state bit;
adding an FR bit into a Tag RAM of LLC, and indicating the ID of a first core for performing read or write operation on the block, wherein the ID is used for judging whether the core for performing subsequent operation on the block is the same core or not, so as to judge whether the state bit needs to be modified or not;
adding a 1bit C bit in the Tag RAM of the LLC to indicate whether the block is written into the private cache or not, and whether the block is started or not;
and for the private read, private read and write and shared read, the data tracking of multi-core consistency is not carried out, and only the shared read and write state is subjected to a consistency flow.
In one embodiment, a 2bit status bit is added to the block of the LLC, and the status changes according to the read-write requests of the LLC in different checks.
In one embodiment, the state change mechanism between the four states is irreversible, and when the state is transferred to the shared read-write state, the block is always in the shared read-write state unless the block is replaced or the cache is reset.
In one embodiment, the state change mechanism between the four states identifies, for each request, whether its source is consistent with the core of the first request, and whether to read or write when the request is screened, as a basis for state transition.
In one embodiment, in the state change mechanism between the four states, a consistency flow is required to be performed in the shared read-write state; before the buffer memory block is changed from other states to the shared read-write state, the starting of the consistency flow is needed.
In one embodiment, the bit width of the FR bits depends on the number of cores.
The method for improving the operation efficiency of the cache consistency mechanism provided by the invention simultaneously provides the conversion conditions among four states and the starting scheme of the consistency operation, and improves the operation efficiency of the multi-core consistency mechanism.
Drawings
Fig. 1 is a block diagram of the structure of the present invention.
Fig. 2 is a state jump diagram of the present invention.
Detailed Description
The method for improving the operation efficiency of the cache consistency mechanism provided by the invention is further described in detail below with reference to the accompanying drawings and the specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
In order to improve the operation efficiency of the multi-core consistency mechanism, the invention provides a mechanism for selective consistency operation based on additional status bits, which can effectively reduce unnecessary consistency operation, reduce resource consumption and increase less hardware cost.
As shown in FIG. 1, the invention utilizes spare bits to add 2bit status bits in the Tag RAM of LLC, indicating the status of the block, and there are four status in total:
private read (PL): only one check that the block is operating and only a read operation;
private read-write (PS): only one check of the block is operated, and the operation comprises a writing operation;
shared read (SL): a plurality of checks that the block has been operated and only a read operation;
shared read-write (SS): a plurality of cores operate on the block, and at least one of the cores includes a write operation.
The state transitions between the four states are shown in fig. 2. All blocks will be in a non-uniform state after the first cold start (bit C in clear state), miss-fill. The initial state is PL when cold start is a read operation, and PS when cold start is a write operation; while the FR records the core ID that operates on the block for the first time (hereinafter this core will be referred to simply as the FR core).
When there is a hit again to check that the block has issued a request, the system will determine the state transition in combination with whether the new request is a read or a write, comparing whether the core's ID matches the FR's recorded ID.
In the PL state, if the FR core issues a read request, the block state is unchanged; if the FR core issues a write request, the block state becomes PS; if other cores send out read requests, the block state becomes SL; if other cores send out write requests, the block starts a consistency flow and changes the state into SS;
in the SL state, if FR or other core issues a read request, the block state is unchanged; if FR or other cores send out a write request, starting a consistency flow and changing the state into SS;
in the PS state, if the FR core sends out a read request or a write request, the block state is unchanged; if other cores send out a read request or a write request, starting a consistency flow and changing the state into SS;
in the SS state, any request does not change the state of the block.
When there is a check again that the block is requesting but missing, non-coherency processing is performed (cache directory is not tracked) if the block is in one of the PL/SL/PS states, and coherency processing is performed if the block is in the SS state.
When the cache block needs to be converted from other states to the SS state, the FR core locks the cache block first, and other cores send out a request for recovering consistency. After the FR core receives the request, if the block is currently in the SL state, the request needs to be broadcast to other nodes, and if the block is currently in the PL or PS state, the request does not need to be broadcast. The FR and (possibly) other cores that received the broadcast then flush their private caches and check for missing records, and clean up the missing problem that has not been handled. Subsequently, each other core issues a "resume consistency request complete" signal to the FR core. After the FR core receives signals of all other cores, the FR core replies done signals to all other cores, then the recovery consistency flow is completed, the state of the cache block is changed to the SS state, and the FR core is unlocked.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (6)
1. The method for improving the operation efficiency of the cache consistency mechanism is characterized by comprising the following steps:
adding a 2bit LS state bit into a Tag RAM of LLC, indicating four states of private reading, private reading and writing, shared reading and writing, checking consistency request things initiated by LLC according to each processor to update state bit information in real time, and determining whether the block needs to execute consistency operations such as monitoring or not according to the state bit;
adding an FR bit into a Tag RAM of LLC, and indicating the ID of a first core for performing read or write operation on the block, wherein the ID is used for judging whether the core for performing subsequent operation on the block is the same core or not, so as to judge whether the state bit needs to be modified or not;
adding a 1bit C bit in the Tag RAM of the LLC to indicate whether the block is written into the private cache or not, and whether the block is started or not;
and for the private read, private read and write and shared read, the data tracking of multi-core consistency is not carried out, and only the shared read and write state is subjected to a consistency flow.
2. The method of claim 1, wherein 2bit status bits are added to the block of the LLC, the status changing with different requests to read from and write to the LLC.
3. The method for improving the operation efficiency of the cache coherency mechanism according to claim 1, wherein the state change mechanism between the four states is irreversible, and is always in the shared read/write state unless the block is replaced or the cache is reset after the state is transferred to the shared read/write.
4. The method as set forth in claim 1, wherein the state change mechanism between the four states identifies, for each request, whether its source is consistent with the core of the first request, and selects whether the request is read or written as a basis for state transition.
5. The method for improving the operation efficiency of a cache coherency mechanism according to claim 1, wherein in a state change mechanism between the four states, a coherency flow is required for a shared read-write state; before the buffer memory block is changed from other states to the shared read-write state, the starting of the consistency flow is needed.
6. The method for improving the efficiency of cache coherency mechanism operation of claim 1, wherein the bit width of the FR bits depends on the number of cores.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311418036.7A CN117312187A (en) | 2023-10-30 | 2023-10-30 | Method for improving operation efficiency of cache consistency mechanism |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311418036.7A CN117312187A (en) | 2023-10-30 | 2023-10-30 | Method for improving operation efficiency of cache consistency mechanism |
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