CN117310563A - Detection circuit for detecting N line loss in three-phase four-wire and detection method thereof - Google Patents

Abstract

The invention discloses a detection circuit for detecting N line loss in three-phase four lines and a detection method thereof, wherein the detection circuit comprises: the first terminal is electrically connected to the second end of switch RY2, the second terminal is electrically connected to the second end of switch RY4, and the second end of switch RY3 is electrically connected to the first end of switch RY 4; the first end of switch RY4 is electrically connected to the second end of capacitor C1; the second end of the inductor L is electrically connected to the first end of the switch RY 1; the E pole of the triode Q1, the E pole of the triode Q3 and the C pole of the triode Q4 are all electrically connected to the first end of the inductor L, and the second end of the capacitor C3 and the second end of the capacitor C5 are all electrically connected to a third wiring terminal; the first end of the capacitor C6 is electrically connected to the first end of the capacitor C4, and the second end of the capacitor C6 is electrically connected to the third terminal. The detection circuit can monitor whether N lines in three-phase four-wire are lost.

Description

Detection circuit for detecting N line loss in three-phase four-wire and detection method thereof

Technical Field

The invention relates to the technical field of electricity, in particular to a detection circuit and a detection method for detecting N line loss in three-phase four lines.

Background

Three-phase four-wire is a typical distribution system version of a low-voltage power supply system that includes four lines L1, L2, L3, and N, with the power side N connected to ground, and the three phases L1, L2, and L3 having voltages relative to the N lines that differ in spatial arrangement by 120 ° in electrical angle. This power supply supplies power to the three-phase load, and the three-phase four-wire flow vector sum flows through the N-wire back to the transformer power supply neutral. When the three phases balance the load, the vector sum of the three phases four-wire flow is 0; but the current vector sum generated by unbalanced load returns to the neutral point of the transformer power supply through N lines, after N lines are lost, the neutral point of the power supply is separated from the neutral line of the load, and in a line with larger unbalanced load degree, the load voltage drop with small load is increased too much, so that the service life of the power distribution equipment can be greatly shortened, and even the power distribution equipment is in danger of burning.

Therefore, how to detect N-line loss in three-phase four-line becomes a problem to be solved.

Disclosure of Invention

In view of the above, the present invention is directed to a detection circuit and a detection method for detecting N-wire loss in three-phase four-wire.

In order to achieve the above purpose, the technical scheme of the invention is realized as follows: a detection circuit for detecting N-line loss in three-phase four-line, comprising: a first terminal, a second terminal, a third terminal, a switch RY1, a switch RY2, a switch RY3, a switch RY4, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, an inductor L, a triode Q1, a triode Q2, a triode Q3 and a triode Q4; the triode Q1, the triode Q2, the triode Q3 and the triode Q4 are NPN type triodes with damping diodes, the switch RY1, the switch RY2, the switch RY3, the switch RY4, the capacitor C1, the capacitor C2, the inductor L, the capacitor C3, the capacitor C4, the capacitor C5, the capacitor C6 and the capacitor C7 are respectively provided with different terminals at the first end and the second end; the first terminal is electrically connected to the second end of switch RY2, and the second end of switch RY1 is electrically connected to the first end of switch RY 2; the second terminal is electrically connected to the second end of switch RY4, and the second end of switch RY3 is electrically connected to the first end of switch RY 4; the first end of the switch RY1 is electrically connected to the first end of the capacitor C2, and the first end of the switch RY3 is electrically connected to the second end of the capacitor C2; the first end of switch RY2 is electrically connected to the first end of capacitor C1, and the first end of switch RY4 is electrically connected to the second end of capacitor C1; the second end of the inductor L is electrically connected to the first end of the switch RY 1; the E pole of the triode Q1, the E pole of the triode Q3 and the C level of the triode Q4 are all electrically connected to the first end of the inductor L, the first end of the capacitor C7 is electrically connected to the C pole of the triode Q1, the second end of the capacitor C7 is electrically connected to the E pole of the triode Q2, and the C level of the triode Q2 is electrically connected to the C level of the triode Q3; the first end of the capacitor C4 and the first end of the switch RY3 are electrically connected to the second end of the capacitor C7, and the second end of the capacitor C4 is electrically connected to the E pole of the triode Q4; a first end of the capacitor C3 is electrically connected to the second end of the switch RY3, a first end of the capacitor C5 is electrically connected to the E pole of the transistor Q4, and both the second end of the capacitor C3 and the second end of the capacitor C5 are electrically connected to the third terminal; the first end of the capacitor C6 is electrically connected to the first end of the capacitor C4, and the second end of the capacitor C6 is electrically connected to the third terminal.

As an improvement of the embodiment of the present invention, the method further includes: an amplifier OPA having two input terminals electrically connected to the first and second terminals of the capacitor C3, respectively.

As an improvement of the embodiment of the present invention, the method further includes: the first end of resistor R1, switch RY2 is electrically connected to the first end of resistor R1, and the first end of switch RY4 is electrically connected to the second end of resistor R1.

As an improvement of the embodiment of the present invention, the capacitance value of the capacitor C5 and the capacitance value of the capacitor C6 are the same.

As an improvement of the embodiment of the invention, the third wiring terminal is grounded.

As an improvement of the embodiment of the present invention, the switch RY1, the switch RY2, the switch RY3, and the switch RY4 are all internal control switches.

As an improvement of the embodiment of the present invention, the switch RY1, the switch RY2, the switch RY3, and the switch RY4 are all internal control relays.

The embodiment of the invention also provides a detection method for the detection circuit, which comprises the following steps: the first wiring terminal is electrically connected to any one of an L1 line, an L2 line and an L3 line in three-phase four lines, the second wiring terminal is electrically connected to an N line in the three-phase four lines, the third wiring terminal is electrically connected to one end of a resistor R2 through being connected to the other end of the resistor R2, and the other end of the resistor R2 is electrically connected to the N line in the three-phase four lines; inputting a first PWM signal to the B pole of the triode Q1, inputting a second PWM signal to the B pole of the triode Q2, and when the first PWM signal is at a high level, the second PWM signal is at a low level; when the first PWM signal is at a low level, the second PWM signal is at a high level; a high level is input to the B pole of the triode Q3, and a low level is input to the B pole of the triode Q4; and acquiring the voltage difference between the first end and the second end of the capacitor C3, wherein the N line is not lost when the voltage difference is zero, and otherwise, the N line is lost.

As an improvement of the embodiment of the invention, the resistance value of the resistor R2 is smaller than 4 ohms.

The embodiment of the invention also provides a detection method for the detection circuit, which comprises the following steps: the first wiring terminal is electrically connected to any one of an L1 line, an L2 line and an L3 line in three-phase four lines, the second wiring terminal is electrically connected to an N line in the three-phase four lines, the third wiring terminal is electrically connected to one end of a resistor R2 through being connected to the other end of the resistor R2, and the other end of the resistor R2 is electrically connected to the N line in the three-phase four lines; inputting a first PWM signal to the B pole of the triode Q3, inputting a second PWM signal to the B pole of the triode Q4, and when the first PWM signal is at a high level, the second PWM signal is at a low level; when the first PWM signal is at a low level, the second PWM signal is at a high level; a high level is input to the B pole of the triode Q2, and a low level is input to the B pole of the triode Q1; and acquiring the voltage difference between the first end and the second end of the capacitor C3, wherein the N line is not lost when the voltage difference is zero, and otherwise, the N line is lost.

The detection circuit and the detection method for detecting N line loss in three-phase four lines provided by the embodiment of the invention have the following advantages: the embodiment of the invention discloses a detection circuit for detecting N line loss in three-phase four lines and a detection method thereof, wherein the detection circuit comprises the following components: the first terminal is electrically connected to the second end of switch RY2, the second terminal is electrically connected to the second end of switch RY4, and the second end of switch RY3 is electrically connected to the first end of switch RY 4; the first end of switch RY4 is electrically connected to the second end of capacitor C1; the second end of the inductor L is electrically connected to the first end of the switch RY 1; the E pole of the triode Q1, the E pole of the triode Q3 and the C pole of the triode Q4 are all electrically connected to the first end of the inductor L, and the second end of the capacitor C3 and the second end of the capacitor C5 are all electrically connected to a third wiring terminal; the first end of the capacitor C6 is electrically connected to the first end of the capacitor C4, and the second end of the capacitor C6 is electrically connected to the third terminal. The detection circuit can monitor whether N lines in three-phase four-wire are lost.

Drawings

FIG. 1 is a block diagram of a detection circuit provided in an embodiment of the present invention;

fig. 2, fig. 3 and fig. 4 are schematic diagrams of a detection circuit according to an embodiment of the present invention.

Detailed Description

The present invention will be described in detail below with reference to embodiments shown in the drawings. The embodiment is not intended to limit the present invention, and structural, methodological, or functional modifications of the invention according to the embodiment are included in the scope of the invention.

The following description and the drawings sufficiently illustrate specific embodiments herein to enable those skilled in the art to practice them. Portions and features of some embodiments may be included in, or substituted for, those of others. The scope of the embodiments herein includes the full scope of the claims, as well as all available equivalents of the claims. The terms "first," "second," and the like herein are used merely to distinguish one element from another element and do not require or imply any actual relationship or order between the elements. Indeed the first element could also be termed a second element and vice versa. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a structure, apparatus, or device that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such structure, apparatus, or device. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a structure, apparatus or device comprising the element. Various embodiments are described herein in a progressive manner, each embodiment focusing on differences from other embodiments, and identical and similar parts between the various embodiments are sufficient to be seen with each other.

The terms "longitudinal," "transverse," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like herein refer to an orientation or positional relationship based on that shown in the drawings, merely for ease of description herein and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operate in a particular orientation, and thus are not to be construed as limiting the invention. In the description herein, unless otherwise specified and limited, the terms "mounted," "connected," and "coupled" are to be construed broadly, and may be, for example, mechanically or electrically coupled, may be in communication with each other within two elements, may be directly coupled, or may be indirectly coupled through an intermediary, as would be apparent to one of ordinary skill in the art.

An embodiment of the present invention provides a detection circuit for detecting N-line loss in three-phase four-line, as shown in fig. 1, including:

a first terminal E, a second terminal N, a third terminal PE, a switch RY1, a switch RY2, a switch RY3, a switch RY4, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, an inductance L, a transistor Q1, a transistor Q2, a transistor Q3, and a transistor Q4; the triode Q1, the triode Q2, the triode Q3 and the triode Q4 are NPN type triodes with damping diodes, the switch RY1, the switch RY2, the switch RY3, the switch RY4, the capacitor C1, the capacitor C2, the inductor L, the capacitor C3, the capacitor C4, the capacitor C5, the capacitor C6 and the capacitor C7 are respectively provided with different terminals at the first end and the second end;

the first terminal E is electrically connected to the second end of the switch RY2, and the second end of the switch RY1 is electrically connected to the first end of the switch RY 2; the second terminal N is electrically connected to the second end of the switch RY4, and the second end of the switch RY3 is electrically connected to the first end of the switch RY 4; the first end of the switch RY1 is electrically connected to the first end of the capacitor C2, and the first end of the switch RY3 is electrically connected to the second end of the capacitor C2; the first end of switch RY2 is electrically connected to the first end of capacitor C1, and the first end of switch RY4 is electrically connected to the second end of capacitor C1; the second end of the inductor L is electrically connected to the first end of the switch RY 1;

the E pole of the triode Q1, the E pole of the triode Q3 and the C level of the triode Q4 are all electrically connected to the first end of the inductor L, the first end of the capacitor C7 is electrically connected to the C pole of the triode Q1, the second end of the capacitor C7 is electrically connected to the E pole of the triode Q2, and the C level of the triode Q2 is electrically connected to the C level of the triode Q3; the first end of the capacitor C4 and the first end of the switch RY3 are electrically connected to the second end of the capacitor C7, and the second end of the capacitor C4 is electrically connected to the E pole of the triode Q4; a first end of the capacitor C3 is electrically connected to the second end of the switch RY3, a first end of the capacitor C5 is electrically connected to the E pole of the transistor Q4, and both the second end of the capacitor C3 and the second end of the capacitor C5 are electrically connected to the third terminal PE; the first end of the capacitor C6 is electrically connected to the first end of the capacitor C4, and the second end of the capacitor C6 is electrically connected to the third terminal PE.

Here, as shown in fig. 2, in use, the first terminal E is electrically connected to the L1, L2 or L3 line, the second terminal N is electrically connected to the N line, and the third terminal PE is electrically connected to the N line through a resistor R2 connected in series.

The working principle of the detection circuit is as follows:

as shown in fig. 3, before grid connection or disconnection, the voltage between bus+ and BUS-is a first voltage value (e.g., 800V), since the values of capacitor C5 and capacitor C6 are connected in series between bus_n and BUS-, the voltage on capacitor C5 is a second voltage value (e.g., 200V), the voltage on capacitor C6 is a third voltage value, the detection target is the voltage across capacitor C3, and since capacitor C3 has no loop, transistor Q1, transistor Q2, transistor Q3 and transistor Q4 need to operate, switch RY1 is closed, and switch RY4 is closed. The BUS_N, the switch RY1, the capacitor C1 and the capacitor C3 form a loop. The voltage on the capacitor C3 is a third voltage value (e.g., 200V), when the voltage between the N line connected to the N and the third terminal PE is 0V, i.e., when the voltage across the capacitor C3 is zero, the N line is not lost, otherwise the N line is lost.

In fig. 3, the switch SW simulates a switch connected to the third terminal PE. Fig. 3 shows the timing sequence of transistor Q1, transistor Q2, transistor Q3, and transistor Q4.

The square waves of the triode Q1, the triode Q2, the triode Q3 and the triode Q4 output sine waves, and the square waves of the triode Q1, the triode Q2, the triode Q3 and the triode Q4 aim to enable the capacitor C3 and the three-level topology to form a loop. The purpose of switch RY4 closure is to connect capacitor C3 to the N line to form a loop, via inductor, switch RY1, capacitor C1, switch SW, resistor R2 and capacitor C6 back to BUS_N.

When the N line is connected to the third terminal PE, the capacitor C3 is shorted by the switch SW, and the voltage between the two ends is zero. Since the resistance of the resistor R2 is very small and negligible. The voltage at the N-line and the third terminal PE is equal to zero. The purpose of opening switch RY3 and switch RY2 is not to allow the generator to form a circuit with the grid.

When the N line is not connected, the square wave modes of the triode Q1, the triode Q2, the triode Q3 and the triode Q4 are unchanged, and the output is sine waves. The square wave of transistor Q1, transistor Q2, transistor Q3 and transistor Q4 is intended to loop capacitor C3 with a three level topology. The line returns to BUS_N via inductor L, switch RY1, capacitor C3 and capacitor C6, either with the N line not on or with switch SW off. The voltage across the capacitor C3 assumes a voltage between < BUS + and BUS-. The purpose of switch RY4 closure is to connect capacitor C3 to line N to form a loop. The purpose of opening switch RY3 and switch RY2 is not to allow the generator to form a circuit with the grid.

In summary, the detection circuit uses a three-level switching mode set and bus_n and BUS-, the N line respectively forms voltage division on the Y capacitor of PE, and the switching state of the triode to realize the change of the voltage states of the N line and the third terminal PE to detect whether to ground. In addition, since the variation of the voltage characteristic value formed between the N line and the third segment PE is large, detection misjudgment is avoided.

In this embodiment, the method further includes: an amplifier OPA having two input terminals electrically connected to the first and second terminals of the capacitor C3, respectively. Here, the amplifier OPA may amplify the voltage value across the capacitor C3.

In this embodiment, the method further includes: the first end of resistor R1, switch RY2 is electrically connected to the first end of resistor R1, and the first end of switch RY4 is electrically connected to the second end of resistor R1. Here, when the transistors Q1, Q2, Q3, and Q4 are operated, the bus_n, the switch RY1, the resistor R1, and the capacitor C3 form a loop.

In this embodiment, the capacitance value of the capacitor C5 is the same as that of the capacitor C6.

In this embodiment, the third terminal PE is grounded.

In this embodiment, the switches RY1, RY2, RY3, and RY4 are all internal control switches.

In the present embodiment, the switch RY1, the switch RY2, the switch RY3, and the switch RY4 are all internal control relays.

The second embodiment of the present invention also provides a detection method for the detection circuit in the first embodiment, including the following steps:

step 1: the first terminal E is electrically connected to any one of an L1 line, an L2 line and an L3 line in three-phase four lines, the second terminal N is electrically connected to the N line in the three-phase four lines, the third terminal PE is electrically connected to the N line in the three-phase four lines through being connected to one end of a resistor R2, and the other end of the resistor R2 is electrically connected to the N line in the three-phase four lines;

step 2: inputting a first PWM signal to the B pole of the triode Q1, inputting a second PWM signal to the B pole of the triode Q2, and when the first PWM signal is at a high level, the second PWM signal is at a low level; when the first PWM signal is at a low level, the second PWM signal is at a high level; a high level is input to the B pole of the triode Q3, and a low level is input to the B pole of the triode Q4;

step 3: and acquiring the voltage difference between the first end and the second end of the capacitor C3, wherein the N line is not lost when the voltage difference is zero, and otherwise, the N line is lost.

In this embodiment, the resistance of the resistor R2 is less than 4 ohms.

The second embodiment of the present invention also provides a detection method for the detection circuit in the first embodiment, including the following steps:

step 1: the first terminal E is electrically connected to any one of an L1 line, an L2 line and an L3 line in three-phase four lines, the second terminal N is electrically connected to the N line in the three-phase four lines, the third terminal PE is electrically connected to the N line in the three-phase four lines through being connected to one end of a resistor R2, and the other end of the resistor R2 is electrically connected to the N line in the three-phase four lines;

step 2: inputting a first PWM signal to the B pole of the triode Q3, inputting a second PWM signal to the B pole of the triode Q4, and when the first PWM signal is at a high level, the second PWM signal is at a low level; when the first PWM signal is at a low level, the second PWM signal is at a high level; a high level is input to the B pole of the triode Q2, and a low level is input to the B pole of the triode Q1;

step 3: and acquiring the voltage difference between the first end and the second end of the capacitor C3, wherein the N line is not lost when the voltage difference is zero, and otherwise, the N line is lost.

It should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is for clarity only, and that the skilled artisan should recognize that the embodiments may be combined as appropriate to form other embodiments that will be understood by those skilled in the art.

The above list of detailed descriptions is only specific to practical embodiments of the present invention, and they are not intended to limit the scope of the present invention, and all equivalent embodiments or modifications that do not depart from the spirit of the present invention should be included in the scope of the present invention.

Claims (10)

1. A detection circuit for detecting loss of N lines in three-phase four lines, comprising:

a first terminal (E), a second terminal (N), a third terminal (PE), a switch RY1, a switch RY2, a switch RY3, a switch RY4, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, an inductance L, a triode Q1, a triode Q2, a triode Q3 and a triode Q4; the triode Q1, the triode Q2, the triode Q3 and the triode Q4 are NPN type triodes with damping diodes, the switch RY1, the switch RY2, the switch RY3, the switch RY4, the capacitor C1, the capacitor C2, the inductor L, the capacitor C3, the capacitor C4, the capacitor C5, the capacitor C6 and the capacitor C7 are respectively provided with different terminals at the first end and the second end;

the first terminal (E) is electrically connected to the second end of the switch RY2, and the second end of the switch RY1 is electrically connected to the first end of the switch RY 2; the second terminal (N) is electrically connected to the second end of the switch RY4, and the second end of the switch RY3 is electrically connected to the first end of the switch RY 4; the first end of the switch RY1 is electrically connected to the first end of the capacitor C2, and the first end of the switch RY3 is electrically connected to the second end of the capacitor C2; the first end of switch RY2 is electrically connected to the first end of capacitor C1, and the first end of switch RY4 is electrically connected to the second end of capacitor C1; the second end of the inductor L is electrically connected to the first end of the switch RY 1;

the E pole of the triode Q1, the E pole of the triode Q3 and the C level of the triode Q4 are all electrically connected to the first end of the inductor L, the first end of the capacitor C7 is electrically connected to the C pole of the triode Q1, the second end of the capacitor C7 is electrically connected to the E pole of the triode Q2, and the C level of the triode Q2 is electrically connected to the C level of the triode Q3; the first end of the capacitor C4 and the first end of the switch RY3 are electrically connected to the second end of the capacitor C7, and the second end of the capacitor C4 is electrically connected to the E pole of the triode Q4; a first end of the capacitor C3 is electrically connected to the second end of the switch RY3, a first end of the capacitor C5 is electrically connected to the E pole of the transistor Q4, and both the second end of the capacitor C3 and the second end of the capacitor C5 are electrically connected to the third terminal (PE); the first end of the capacitor C6 is electrically connected to the first end of the capacitor C4, and the second end of the capacitor C6 is electrically connected to the third terminal (PE).

2. The detection circuit of claim 1, further comprising:

an amplifier OPA having two input terminals electrically connected to the first and second terminals of the capacitor C3, respectively.

3. The detection circuit of claim 1, further comprising:

the first end of resistor R1, switch RY2 is electrically connected to the first end of resistor R1, and the first end of switch RY4 is electrically connected to the second end of resistor R1.

4. The detection circuit of claim 1, wherein:

the capacitance value of the capacitor C5 is the same as that of the capacitor C6.

5. The detection circuit of claim 1, wherein:

the third terminal (PE) is grounded.

6. The detection circuit of claim 1, wherein:

the switches RY1, RY2, RY3, and RY4 are all internal control switches.

7. The detection circuit of claim 1, wherein:

the switch RY1, the switch RY2, the switch RY3, and the switch RY4 are all internal control relays.

8. A detection method for the detection circuit according to any one of claims 1 to 7, characterized by comprising the steps of:

electrically connecting a first terminal (E) to any one of an L1 line, an L2 line and an L3 line in three-phase four lines, electrically connecting a second terminal (N) to an N line in the three-phase four lines, and electrically connecting a third terminal (PE) to an end of a resistor R2 by connecting the other end of the resistor R2 to the N line in the three-phase four lines;

inputting a first PWM signal to the B pole of the triode Q1, inputting a second PWM signal to the B pole of the triode Q2, and when the first PWM signal is at a high level, the second PWM signal is at a low level; when the first PWM signal is at a low level, the second PWM signal is at a high level; a high level is input to the B pole of the triode Q3, and a low level is input to the B pole of the triode Q4;

and acquiring the voltage difference between the first end and the second end of the capacitor C3, wherein the N line is not lost when the voltage difference is zero, and otherwise, the N line is lost.

9. The method of detecting according to claim 8, wherein:

the resistance value of the resistor R2 is less than 4 ohms.

10. A detection method for the detection circuit according to any one of claims 1 to 7, characterized by comprising the steps of:

electrically connecting a first terminal (E) to any one of an L1 line, an L2 line and an L3 line in three-phase four lines, electrically connecting a second terminal (N) to an N line in the three-phase four lines, and electrically connecting a third terminal (PE) to an end of a resistor R2 by connecting the other end of the resistor R2 to the N line in the three-phase four lines;

inputting a first PWM signal to the B pole of the triode Q3, inputting a second PWM signal to the B pole of the triode Q4, and when the first PWM signal is at a high level, the second PWM signal is at a low level; when the first PWM signal is at a low level, the second PWM signal is at a high level; a high level is input to the B pole of the triode Q2, and a low level is input to the B pole of the triode Q1;

and acquiring the voltage difference between the first end and the second end of the capacitor C3, wherein the N line is not lost when the voltage difference is zero, and otherwise, the N line is lost.