CN117295340A

CN117295340A - Method for manufacturing semiconductor device

Info

Publication number: CN117295340A
Application number: CN202311459421.6A
Authority: CN
Inventors: 蒋家勇; 请求不公布姓名; 石振东
Original assignee: Beijing Pansin Microelectronics Technology Co ltd
Current assignee: Beijing Pansin Microelectronics Technology Co ltd
Priority date: 2023-11-03
Filing date: 2023-11-03
Publication date: 2023-12-26

Abstract

The present disclosure provides a method for manufacturing a semiconductor device. The semiconductor device includes a first region in which a plurality of flash memory cells are formed and a second region in which Metal Oxide Semiconductor (MOS) transistors are formed, each flash memory cell including two memory transistors and a gate transistor disposed between the two memory transistors. The method for manufacturing a semiconductor device according to the present disclosure includes: providing a semiconductor substrate and forming an isolation structure therein; forming a storage gate dielectric stack and a first gate electrode layer of a storage transistor; forming a gate structure of the memory transistor by patterning the memory gate dielectric stack and the first gate electrode layer; forming gate dielectric layers and second gate electrode layers of the gate transistors and the MOS transistors concurrently; concurrently forming a gate structure of the MOS transistor and a gate structure of the gate transistor; and replacing the gate structure of the MOS transistor with the high-K gate dielectric layer and the metal gate.

Description

Method for manufacturing semiconductor device

Technical Field

The present disclosure relates to the field of semiconductor technology, and in particular, to a method for fabricating a semiconductor device including an integrally formed non-volatile memory (NVM) transistor and a Metal Oxide Semiconductor (MOS) transistor.

Background

Flash memory, abbreviated as flash memory, is a non-volatile memory (NVM) that is a device that does not lose stored data even when power is turned off, and is particularly suitable for use in mobile communications and computer storage devices. In addition, some flash memories also have high density storage capability, and are suitable for applications in large-capacity mobile storage media and the like.

Conventional flash memories use a floating gate type cell structure or a SONOS type (Silicon-Oxide-Nitride-Oxide-Silicon) cell structure. However, the conventional floating gate flash memory and SONOS flash memory have problems that the process size cannot be reduced, the cell area is large, the write power consumption is large, and the array area overhead is large, and high-density integration with a gigabit (Gb) capacity or more cannot be realized.

Furthermore, for many applications such as systems on chip, it is desirable to integrate Metal Oxide Semiconductor (MOS) transistors and NVM transistors on a single chip or substrate. However, such integration can severely impact the manufacturing process of the MOS transistor and the NVM transistor.

MOS transistors are typically fabricated using a reference Complementary Metal Oxide Semiconductor (CMOS) process flow that includes the formation and patterning of conductors, semiconductors, and dielectric materials. The combination of these materials, the combination and concentration of processing reagents, and the temperature used in the CMOS process flow are tightly controlled for each process step to ensure proper operation of the resulting MOS transistor.

In addition, NVM transistors include a gate dielectric stack that typically includes two oxide layers and a nitride or oxynitride layer sandwiched therebetween, and the materials and processes used to fabricate the two oxide layers are typically different from those of the reference CMOS process flow, and thus may adversely affect or be affected by the fabrication of the MOS transistor.

Thus, the integration of NVM transistors and MOS transistors can severely impact the reference CMOS process flow and typically require numerous mask set-up and processing steps, which increases manufacturing costs and reduces production efficiency.

The above information disclosed in this background section is only for the understanding of the background of the inventive concept and thus may contain information that does not form the prior art.

Disclosure of Invention

In order to solve the above problems in the prior art, the present disclosure proposes a novel method for manufacturing a semiconductor device including an integrally formed non-volatile memory (NVM) transistor and a Metal Oxide Semiconductor (MOS) transistor.

According to one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The semiconductor device includes a first region in which a plurality of flash memory cells are formed and a second region in which a low voltage Metal Oxide Semiconductor (MOS) transistor is formed, and each flash memory cell includes two memory transistors and one gate transistor disposed between the two memory transistors. The method for manufacturing a semiconductor device according to the present disclosure includes: providing a semiconductor substrate and forming an isolation structure therein; forming a storage gate dielectric stack and a first gate electrode layer of a storage transistor; forming a gate structure of the memory transistor by patterning the memory gate dielectric stack and the first gate electrode layer; forming gate dielectric layers and second gate electrode layers of the gate transistors and the MOS transistors concurrently; concurrently forming a gate structure of the MOS transistor and a gate structure of the gate transistor; and replacing the gate structure of the low-voltage MOS transistor with a high-K gate dielectric layer and a metal gate.

According to the method for manufacturing a semiconductor device of the present disclosure, a non-volatile memory (NVM) transistor may be integrated into a manufacturing process of a MOS transistor.

However, the effects of the present disclosure are not limited to the above-described effects, and various extensions may be made without departing from the spirit and scope of the present disclosure. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the invention.

Fig. 1 is a cross-sectional view illustrating a flash memory cell according to an embodiment of the present disclosure.

Fig. 2 shows an equivalent circuit diagram of a flash memory cell according to an embodiment of the present disclosure.

Fig. 3 shows a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

Fig. 4A to 4O show cross-sectional views of the semiconductor device in respective steps of the method for manufacturing a semiconductor device shown in fig. 3.

Detailed Description

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various exemplary embodiments of the present disclosure. As used herein, an "embodiment" is a non-limiting example of an apparatus or method that uses one or more of the inventive concepts disclosed herein. It may be evident, however, that the exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. Furthermore, the various exemplary embodiments may be different, but are not necessarily exclusive. For example, certain features of other exemplary embodiments may be used or implemented in some exemplary embodiments without departing from the inventive concept.

For the purposes of this disclosure, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" may be construed as any combination of two or more of X only, Y only, Z only, or X, Y and Z, such as XYZ, XYY, YZ and ZZ. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Although the terms "first," "second," etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the terms "comprises" and/or "comprising," when used in this specification, mean that there are stated features, steps, operations, elements, components, and/or groups thereof, but that the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof is not precluded. It should also be noted that as used herein, the terms "substantially," "about," and other similar terms are used as approximation terms and not degree terms and, thus, are used to account for inherent deviations in measured, calculated, and/or provided values that would be recognized by one of ordinary skill in the art.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like elements throughout. Also, in the drawings, the components are not necessarily drawn to scale and the ratio and size of the components may be exaggerated for clarity of illustration.

Embodiments of a method of integrating non-volatile memory (NVM) transistors into a Complementary Metal Oxide Semiconductor (CMOS) fabrication process or process flow including Metal Oxide Semiconductor (MOS) transistors to fabricate a semiconductor device are described herein with reference to the accompanying drawings. However, particular embodiments may be practiced without one or more of these specific details, or in combination with other known methods, materials, and devices. In the following description, numerous specific details are set forth, such as specific materials, dimensions, and process parameters, etc., in order to provide a thorough understanding of the present invention. In the description of embodiments, well-known semiconductor design and fabrication techniques have not been described in particular detail in order to not unnecessarily obscure the present invention. Reference throughout this specification to "an embodiment" means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrase "in an embodiment" appearing in various places throughout the specification are not necessarily all referring to the same embodiment of the disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

Embodiments of the present disclosure are described in more detail below with reference to the accompanying drawings.

Fig. 1 illustrates a cross-sectional view of a flash memory cell MC 100 according to an embodiment of the present disclosure. Fig. 2 shows an equivalent circuit diagram of the flash memory cell MC 100 according to the embodiment of the present disclosure.

As shown in fig. 1, a flash memory cell MC 100 according to an embodiment of the present disclosure may include a substrate 101 including a deep well region DNW 103 of a second doping type and a storage well region CPW 102 of a first doping type disposed on the deep well region DNW 103.

Although the first doping type is defined herein as a P-type and the second doping type is defined herein as an N-type by way of example, the present disclosure is not limited thereto. In an alternative embodiment of the present disclosure, the first doping type may also be N-type, while the second doping type may be P-type.

According to embodiments of the present disclosure, the substrate 101 may be, for example, a silicon substrate.

Further, referring to fig. 1 and 2, the flash memory cell MC 100 includes a first memory transistor MS110, a gate transistor MG 120, and a second memory transistor MD 130 connected in series in this order. The first memory transistor MS110 may be disposed on the memory well region CPW 102 and store the first DATA1. The second memory transistor MD 130 may be disposed on the memory well region CPW 102 and store the second DATA2. The gate transistor MG 120 is disposed between the first memory transistor MS110 and the second memory transistor MD 130 in the horizontal direction DR1 on the memory well region CPW 102 for isolating the first memory transistor MS110 and the second memory transistor MD 130 and performing a gate operation on the first memory transistor MS110 and the second memory transistor MD 130.

According to an embodiment of the present disclosure, the flash memory cell MC 100 includes two storage transistors MS110 and MD 130, and thus the flash memory cell MC 100 can implement a two-bit storage function, i.e., simultaneously store the first DATA1 and the second DATA2.

Further, as shown in fig. 1, the source region of the first memory transistor MS110 is connected to the first electrode S of the flash memory cell MC 100, which may also be referred to as the source S of the flash memory cell MC 100, and the drain region of the second memory transistor MD 130 is connected to the second electrode D of the flash memory cell MC 100, which may also be referred to as the drain D of the flash memory cell MC 100.

Those skilled in the art will recognize that the definition of the source and drain of a flash memory cell is defined herein for ease of description, however the definition of the source and drain of a flash memory cell is relative, and the terms "source" and "drain" are used interchangeably under different operating conditions.

Further, as shown in fig. 1, the first memory transistor MS110 has a gate structure including a channel region 111, a gate dielectric stack 112, a gate electrode 116, and a hard mask barrier 117, which are sequentially disposed in a vertical direction DR 2. The gate dielectric stack 112 has a first oxide layer 113, a storage dielectric layer 114, and a second oxide layer 115 stacked in this order in the vertical direction. Further, the second memory transistor MD 130 has a gate structure including a channel region 131, a gate dielectric stack 132, a gate electrode 136, and a hard mask barrier 137, which are sequentially disposed in the vertical direction DR 2. The gate dielectric stack 132 has a first oxide layer 133, a storage dielectric layer 134, and a second oxide layer 135 stacked in this order in the vertical direction.

According to an embodiment of the present disclosure, the flash memory cell MC 100 includes two memory transistors MS110 and MD 130, and thus can implement a two-bit memory function.

According to an embodiment of the present disclosure, as shown in fig. 1, a flash memory cell MC 100 for two-bit storage may be composed of three closely arranged transistors, namely a gate transistor MG 120 located in the middle of the flash memory cell MC 100, a first storage transistor MS110 located at a first end of the flash memory cell MC 100, and a second storage transistor MD 130 located at a second end of the flash memory cell MC 100.

As shown in fig. 1, a flash memory cell MC 100 may be formed on a memory well region CPW 102 within a semiconductor substrate 101. Further, in order to isolate the memory well region CPW 102 from the substrate 101 in order to apply a voltage to the memory well region CPW 102 under certain operating conditions, as shown in fig. 1, the memory well region CPW 102 may be formed in the deep well region DNW 103.

As shown in fig. 1, a source region 140 formed by N-type doping is provided at a first end of the flash memory cell MC 100, and a drain region 150 formed by N-type doping is also provided at a second end of the flash memory cell MC 100. The source region 140 is connected to the metal source 142, i.e., the first electrode S, located at the upper layer through the contact hole 141, and the drain region 150 is connected to the metal drain 152, i.e., the second electrode D, located at the upper layer through the contact hole 151.

According to embodiments of the present disclosure, the first electrode S and the second electrode D may include metal or highly doped polysilicon. When the first electrode S and the second electrode D are formed of metal, they may include at least one of the following materials: aluminum, titanium nitride, copper, tungsten, cobalt, and manganese.

As described above, the gate structure of the first memory transistor MS110 may have the channel region 111, the gate dielectric stack 112, the gate electrode 116, and the hard mask barrier 117 for sidewall self-alignment in order from bottom to top as shown in fig. 1. According to embodiments of the present disclosure, the gate electrode 116 may comprise, for example, polysilicon, a metal gate, a metal silicide, or a combination of the foregoing materials. The hard mask barrier 117 may include, for example, silicon oxide, silicon nitride, silicon glass, amorphous silicon, or a combination thereof, according to embodiments of the present disclosure.

Further, as shown in fig. 1, the gate dielectric stack 112 has a first oxide layer (tunnel oxide layer) 113, a storage dielectric layer (charge storage layer) 114, and a second oxide layer (blocking oxide layer) 115, which are sequentially stacked in the vertical direction. According to an embodiment of the present disclosure, the first oxide layer 113 and the second oxide layer 115 may include, for example, silicon oxide or aluminum oxide, or the like.

According to embodiments of the present disclosure, the storage medium layer 114 may include one or more layers of storage media. Further, according to an embodiment of the present disclosure, the storage medium forming the storage medium layer 114 may include: mono-or poly-oxides such as hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium aluminum oxide; mono-or poly-nitrides, such as silicon nitride; mono-or poly-nitrogen oxides, such as silicon oxynitride; polycrystalline silicon or nanocrystals; or a combination of the above materials.

When the storage medium layer 114 is formed of, for example, silicon nitride, the first oxide layer 113, the storage medium layer 114, and the second oxide layer 115 may form the gate dielectric stack 112 as an ONO (oxide-nitride-oxide) composite storage medium according to an embodiment of the present disclosure. At this time, the first memory transistor MS110 may be a SONOS type memory transistor.

Further, according to embodiments of the present disclosure, the first memory transistor MS110 may be other trap charge-trapping memory transistors having a similar operation mechanism as conventional SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) type memory transistors, which use a high-K material rich in charge traps, such as Silicon oxynitride, hafnium Oxide, tantalum Oxide, titanium Oxide, zirconium Oxide, hafnium aluminum Oxide, or the like, instead of Silicon Nitride in a SONOS memory as the memory medium layer 114.

Furthermore, according to an embodiment of the present disclosure, the first memory transistor MS110 may also be a floating gate type memory transistor, which uses polysilicon instead of silicon nitride in a SONOS memory to form a floating gate for storing charges as the memory medium layer 114.

Furthermore, according to embodiments of the present disclosure, the first memory transistor MS110 may also be a nano-crystal memory transistor (nano-crystal memory), which uses nanocrystals with quantum dots (quantum dots) instead of silicon nitride in a SONOS memory as the memory medium layer 114.

According to an embodiment of the present disclosure, the length of the gate electrode 116 of the first memory transistor MS110 may be defined by the length of the hard mask barrier 117 disposed on the gate electrode 116 through a self-aligned process. It should be noted by those skilled in the art that reference herein to "length" means the dimension of the stated object in the horizontal direction DR1, and reference herein to "thickness" means the dimension of the stated object in the vertical direction DR 2.

According to the embodiment of the present disclosure, the second memory transistor MD 130 has the same structure as the first memory transistor MS110 and may be manufactured by the same process as the first memory transistor MS110 except that it is disposed at the opposite side of the gate transistor MG 120, and thus a detailed description of the structure of the second memory transistor MD 130 will be omitted herein for brevity.

The gate structure of the gate transistor MG 120 may include a channel region 121, a gate dielectric layer 122, and a gate electrode 123 in this order from bottom to top. According to an embodiment of the present disclosure, the gate electrode 123 of the gate transistor MG 120 is connected to a word line, and the length of the gate electrode 123 thereof is defined by the process dimension of the photolithography process. According to embodiments of the present disclosure, gate dielectric layer 122 may comprise, for example, silicon oxide, silicon oxynitride, or a combination thereof. Further, according to embodiments of the present disclosure, the gate electrode 123 may include, for example, polysilicon, a metal gate, a metal silicide, or a combination of the above materials. In particular, gate dielectric layer 122 may be formed of a high-K material according to embodiments of the present disclosure. The high-k material may have a dielectric constant of about 4 to 20 or greater. The high-k material may include hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide, or strontium titanium oxide. According to embodiments of the present disclosure, gate dielectric layer 122 may be formed from a composite layer comprising two or more of the aforementioned high-k materials. When gate dielectric layer 122 is formed of a high-K material, gate electrode 123 may be a metal gate, examples include titanium, titanium nitride, tantalum nitride, tungsten nitride, ruthenium oxide, iridium oxide, platinum, molybdenum oxide, titanium nitride/tungsten stacks, or tungsten nitride/tungsten stacks. At this time, the gate structure of the gate transistor MG 120 is a high-K metal gate (HKMG) structure.

According to an embodiment of the present disclosure, the channel regions 111, 131 and 121 of the first memory transistor MS110, the second memory transistor MD 130 and the gate transistor MG 120 may each have a first doping type, and the doping concentrations of the channel regions 111 and 131 of the first memory transistor MS110 and the second memory transistor MD 130 may be lower than the doping concentration of the channel region 121 of the gate transistor MG 120.

Further, according to an embodiment of the present disclosure, the channel regions 111 and 131 of the first and second memory transistors MS110 and MD 130 may have a second doping type or be undoped intrinsic channel regions, and the channel region 121 of the gate transistor MG 120 may have a first doping type different from the second doping type.

For example, as shown in fig. 1, in the case where the first doping type is P-type and the second doping type is N-type, the doping concentrations of the P-type channels 111 and 131 of the first memory transistor MS110 and the second memory transistor MD 130 are lower than the doping concentration of the P-type channel 121 of the gate transistor MG 120. Furthermore, channel regions 111 and 131 may also be undoped intrinsic channels or N-type doped channel regions, according to embodiments of the present disclosure.

According to an embodiment of the present disclosure, the flash memory cell MC 100 further includes: a first isolation portion 124 provided between the first memory transistor MS110 and the gate transistor MG 120 in the horizontal direction DR1 for isolating the gate electrode 116 of the first memory transistor MS110 and the gate electrode 123 of the gate transistor MG 120; and a second isolation portion 125 disposed between the gate transistor MG 120 and the second memory transistor MD 130 in the horizontal direction DR1 for isolating the gate electrode 123 of the gate transistor MG 120 and the gate electrode 136 of the second memory transistor MD 130.

Specifically, as shown in fig. 1, the gate electrode 123 of the gate transistor MG 120 is provided on both sides with a first isolation portion 124 and a second isolation portion 125 in the form of sidewalls for electrically isolating the gate electrode 116 of the first memory transistor MS110 and the gate electrode 136 of the second memory transistor MD 130, respectively, with a certain isolation gap length. According to an embodiment of the present disclosure, the first and second spacers 124 and 125 may include the same material as the gate dielectric layer 122.

As shown in fig. 2, the flash memory cell MC 100 includes a first memory transistor MS110, a gate transistor MG 120, and a second memory transistor MD 130 connected in series in this order. The gate transistor MG 120 may isolate the first and second memory transistors MS110 and MD 130 and perform a gate operation on the first and second memory transistors MS110 and MD 130.

The flash memory cell according to the embodiment of the present disclosure can realize two memory transistors in one flash memory cell, so that the equivalent area of each memory bit can be greatly reduced, thereby achieving lower cost and higher integration density.

In addition, the memory transistor in the flash memory unit according to the embodiment of the disclosure can use a SONOS type device structure with a simple structure, and has the advantages of simple process, low gate electrode operation voltage and good data retention reliability.

In addition, in the flash memory cell according to the embodiment of the present disclosure, the mutual influence of two memory bits is isolated by the gate transistor, and the distribution width and lateral diffusion of the stored charge are suppressed, so that a higher stored charge density can be obtained in the silicon nitride memory layer, and the memory window and data reliability are significantly improved.

In particular, the equivalent channel length of the flash memory cell according to the embodiment of the present disclosure is the sum of the lengths of the gate electrodes of the first memory transistor, the gate transistor, and the second memory transistor.

In addition, in the flash memory array composed of the flash memory cells according to the embodiment of the present disclosure, for the flash memory cells not selected to operate, the gate electrodes of the gate transistor and the first and second memory transistors are grounded, so that the entire serial channels of the flash memory cells are completely turned off, the equivalent channel length is enlarged, and thus the source-drain punch-through of the flash memory cells under the condition of high operation voltage can be avoided under the smaller process feature size, thereby overcoming the problem that the gate electrode length of the existing flash memory cells cannot be reduced with the reduction of the process feature size. Accordingly, the flash memory cell according to the embodiment of the present disclosure has better process miniaturization capability, and thus can obtain smaller cell area and manufacturing cost by shrinking the process feature size.

In addition, in the flash memory cell according to the embodiment of the present disclosure, by reducing the doping concentration of the P-type channel region of the first memory transistor and the second memory transistor or designing them as N-type doped channel regions, the threshold voltage of the memory transistor and the gate electrode operating voltage at the time of erasing and reading operations can be reduced, and thus the reliability of the memory transistor can be improved. Meanwhile, by increasing the doping concentration of the P-type channel region of the gating transistor, the penetration resistance voltage of the flash memory unit can be increased, and the leakage current between the source region and the drain region of the unselected flash memory unit can be reduced.

Next, a method for manufacturing a semiconductor device according to an embodiment of the present disclosure will be described with reference to fig. 3 and 4A to 4O. Fig. 3 illustrates a flowchart of a method 300 for fabricating a semiconductor device according to an embodiment of the present disclosure. Fig. 4A to 4O illustrate cross-sectional views of a semiconductor device in various steps of the method 300 for manufacturing a semiconductor device illustrated in fig. 3.

Referring to fig. 3, in step S301, as shown in fig. 4A, a wafer serving as a substrate 401 is provided. According to embodiments of the present disclosure, the wafer may be a first doping type wafer used as a semiconductor substrate, such as a silicon substrate. According to an embodiment of the present disclosure, the first doping type may be defined as a P-type and the second doping type may be defined as an N-type, but it should be recognized by those skilled in the art that the present disclosure is not limited thereto, and the first doping type may also be an N-type, in which case the second doping type may be a P-type.

As shown in fig. 4A, the wafer may be pre-processed, for example, by disposing a liner layer 402 formed of, for example, silicon oxide and a cap layer 403 formed of, for example, silicon nitride on a substrate 401 in this order, wherein the liner layer 402 may be used to reduce stress of the cap layer 403. The spacer layer 402 may be formed by, for example, thermal oxidation, in situ steam oxidation (ISSG), or a deposition process, typically 10nm to 100nm thick, in accordance with embodiments of the present disclosure. Furthermore, according to embodiments of the present disclosure, the cap layer 403 may be formed by a deposition process, such as a conventional low pressure chemical vapor deposition process (LPCVD), which is typically 20nm to 200nm thick.

Subsequently, referring to fig. 3, in step S302, as shown in fig. 4B, a plurality of isolation structures 404 defining active regions may be formed in a substrate 401 by active region patterning according to an embodiment of the present disclosure. According to an embodiment of the present disclosure, the isolation structure 404 may divide the substrate 401 into a first region NVMR in which the flash memory cells are disposed and a second region MOSR adjacent to the first region NVMR in which Metal Oxide Semiconductor (MOS) transistors are disposed.

According to an embodiment of the present disclosure, the flash memory cell disposed in the first region NVMR may correspond to, for example, the flash memory cell MC 100 described above with reference to fig. 1 and 2, i.e., include two memory transistors, such as the first memory transistor MS110 and the second memory transistor MD 130 described above with reference to fig. 1 and 2, and one gating transistor, such as the gating transistor 120 described above with reference to fig. 1 and 2.

According to an embodiment of the present disclosure, a flash array composed of a plurality of the same flash memory cells as the flash memory cell MC 100 described above with reference to fig. 1 and 2 may be provided in the first region NVMR of the semiconductor device. Further, although not shown in the drawings, each flash cell column in the flash array disposed in the first region NVMR may also be isolated from adjacent flash cell columns by the isolation structure 404 according to an embodiment of the present disclosure.

According to embodiments of the present disclosure, the MOS transistor disposed in the second region MOSR may be one or more of a low voltage LV-MOS transistor, an interface IO-MOS transistor, or a high voltage HV-MOS transistor. According to embodiments of the present disclosure, the MOS transistors in the second region MOSR may constitute peripheral circuits for the flash memory cell array in the first region NVMR.

Further, according to embodiments of the present disclosure, MOS transistors disposed in the second region MOSR may also be isolated from adjacent MOS transistors by the isolation structure 404.

According to embodiments of the present disclosure, the active region patterning of the first region NVMR and the second region MOSR may be simultaneously achieved through one photolithography process using the same active region mask layer. Alternatively, the patterning of the active regions of the first region NVMR and the second region MOSR may be achieved by a two-pass photolithography process using different active region mask layers.

Although, as shown in fig. 4B, the isolation structure 404 may be implemented by a Shallow Trench Isolation (STI) process according to an embodiment of the present disclosure, the present disclosure is not limited thereto. Those skilled in the art will recognize that the isolation structure may also be implemented by any isolation process commonly used in integrated circuit processing, such as a local oxidation isolation (LOCOS) process.

For example, the isolation structure 404 may be formed by an STI process according to an embodiment of the present disclosure. Specifically, the STI process may include: a part of the cap layer 403 and a part of the liner layer 402 are sequentially removed by an etching process to form a shallow trench structure having a specific depth in the substrate 401, an isolation dielectric layer or a multi-layered composite isolation dielectric layer such as silicon oxide, silicon nitride and/or polysilicon is filled on the surface of the substrate by a thermal oxidation or low pressure deposition process, and the isolation dielectric layer, cap layer 403 and liner layer 402 are removed by a chemical mechanical polishing process (CMP) and/or an etching process to obtain a flat surface of the substrate 401.

According to embodiments of the present disclosure, the isolation structures 404 in the first region NVMR and the second region MOSR may be implemented by one isolation process. Alternatively, the isolation structures 404 in the first and second regions NVMR and MOSR may be respectively implemented by two isolation processes to form the isolation structures 404 having different widths or depths in the first and second regions NVMR and MOSR, respectively.

Subsequently, referring to fig. 3, in step S303, as shown in fig. 4C, well regions of the flash memory cells, such as deep well region DNW and storage well region CPW, may be formed in the first region NVMR through a first implantation process according to an embodiment of the present disclosure. According to embodiments of the present disclosure, the deep well region DNW of the flash memory cell may correspond to the deep well region DNW 103 of the second doping type, for example, described above with reference to fig. 1, and the storage well region CPW of the flash memory cell may correspond to the storage well region CPW 102 of the first doping type, for example, described above with reference to fig. 1. Further, according to an embodiment of the present disclosure, the MOS transistor of the second region MOSR may also be disposed in the deep well region DNW.

In addition, as shown in fig. 4C, according to an embodiment of the present disclosure, a first channel layer 405 of the flash memory cell may also be formed in the first region NVMR through a first implantation process. According to an embodiment of the present disclosure, the first channel layer 405 of the flash memory cell may be used to subsequently form the channel region 111 of the first memory transistor MS110, the channel region 121 of the gate transistor MG 120, and the channel region 131 of the second memory transistor MD 130, for example, as described above with reference to fig. 1.

According to embodiments of the present disclosure, the first implantation process may comprise at least one of the following process steps: a first well implant, a first anti-punch through implant, and a first turn-on implant. According to embodiments of the present disclosure, the first well region implant, the first anti-punch-through implant, and the first turn-on implant may all be implemented as ion implants. Ion implantation refers to implanting an appropriate ion species to an appropriate concentration with an appropriate energy. According to embodiments of the present disclosure, the ion species, dose, energy used in each process step in the first well region implant, the first anti-punch through implant, and the first turn-on implant may be the same or different.

For example, for the N-type flash memory cell according to the present embodiment, the first well implant may form a P-type well region, such as a storage well region CPW, at a suitable depth inside the substrate of the first region NVMR using impurity ions of the first doping type, i.e., P-type, such as boron ions or boron difluoride ions.

According to the embodiment of the disclosure, the first anti-punch-through implantation may form a P-type first punch-through blocking portion (not shown) at a proper depth of the substrate secondary surface of the first region NVMR by using P-type impurity ions, such as boron ions or boron difluoride ions, so that a junction electric field of the source-drain junction may be reduced, and a device withstand voltage capability may be improved.

According to an embodiment of the present disclosure, the first turn-on implant may form the P-type first channel layer 405 at the substrate surface of the first region NVMR using P-type impurity ions, such as boron ions, boron difluoride ions, or indium ions, and adjust the initial threshold voltages of the memory transistors (e.g., the first memory transistor MS110 and the second memory transistor MD 130 described above with reference to fig. 1) to 0V or more.

Alternatively, according to an embodiment of the present disclosure, the first turn-on implant may further form the N-type first channel layer 405 at the substrate surface of the first region NVMR using the second doping type, i.e., N-type impurity ions, such as phosphorus ions or arsenic ions, and adjust the initial threshold voltage of the memory transistor to 0V or less.

Alternatively, according to embodiments of the present disclosure, the first turn-on implant may be omitted to define the substrate surface of the first region NVMR in an intrinsic or low concentration doped state, thereby adjusting the initial threshold voltage of the memory transistor to an intrinsic state close to 0V.

According to embodiments of the present disclosure, by adjusting the initial threshold voltages of the memory transistors (e.g., the first memory transistor MS110 and the second memory transistor MD 130 described above with reference to fig. 1) to be less than 0V or close to 0V, the gate operating voltages of the memory transistors may be reduced, thereby improving the read and write operation performance.

Subsequently, referring to fig. 3, in step S304, as shown in fig. 4D, the surface of the substrate 401 may be cleaned or pre-cleaned, and then a stack structure 411 including a storage gate dielectric stack 407, a first gate electrode layer 408, and a hard mask barrier layer 409 may be sequentially formed on the surface of the substrate 401 through an oxidation, deposition, or sputtering process according to an embodiment of the present disclosure.

For example, in accordance with an embodiment of the present disclosure, the memory gate dielectric stack 407 may be used to subsequently form the gate dielectric stack 112 of the first memory transistor MS110 and the gate dielectric stack 132 of the second memory transistor MS130 of the flash memory cell MC 100, for example, as described above with reference to fig. 1. Thus, according to an embodiment of the present disclosure, the storage gate dielectric stack 407 may include a first oxide layer (tunnel oxide layer) 407a, a storage dielectric layer (charge storage layer) 407b, and a second oxide layer (blocking oxide layer) 407c stacked in this order from bottom to top in a vertical direction.

According to embodiments of the present disclosure, the first oxide layer 407a and the second oxide layer 407c may include, for example, silicon oxide, silicon oxynitride, hafnium oxide, aluminum oxide, or a combination of the above materials. For example, in the case where the first oxide layer 407a and the second oxide layer 407c include silicon oxide, the first oxide layer 407a and the second oxide layer 407c may be formed using a process of thermal oxidation, high temperature thermal oxidation (HTO), low pressure chemical vapor deposition, in situ vapor oxidation, atomic Layer Deposition (ALD), or the like, and the thickness thereof is typically 1nm to 20nm.

According to embodiments of the present disclosure, the storage medium layer 407b may include one or more storage medium sublayers. Further, as described above, according to an embodiment of the present disclosure, the storage medium forming the storage medium layer 407b may include: mono-or poly-oxides such as hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium aluminum oxide; mono-or poly-nitrides, such as silicon nitride; mono-or poly-nitrogen oxides, such as silicon oxynitride; polycrystalline silicon or nanocrystals; or a combination of the above materials. For example, in the case where the storage medium layer 407b includes silicon nitride, the storage medium layer 407b may be formed using a low pressure chemical vapor deposition or atomic layer deposition process or the like, and the thickness thereof is typically 2nm to 20nm.

For example, where the storage medium layer 407b comprises silicon nitride, a plurality of storage medium sublayers may be formed as the storage medium layer 407b in a stack using an appropriate reactant gas flow ratio during its fabrication, according to embodiments of the present disclosure. For example, as shown in fig. 4D, according to an embodiment of the present disclosure, the storage medium layer 407b may include a first storage medium sub-layer 407b1, a second storage medium sub-layer 407b2, and a third storage medium sub-layer 407b3 formed sequentially from bottom to top over the first oxide layer 407a, wherein the second storage medium sub-layer 407b2 has a higher silicon element content than the first storage medium sub-layer 407b1 and the third storage medium sub-layer 407b3, and thus may be referred to as "silicon-rich silicon nitride". Further, according to an embodiment of the present disclosure, the thickness of the first storage medium sub-layer 407b1 is 1nm to 3nm, and the thicknesses of the second storage medium sub-layer 407b2 and the third storage medium sub-layer 407b3 are each 2nm to 10nm.

Preferably, as shown in fig. 4D, the storage medium layer 407b may further include a fourth storage medium sub-layer 407b4 disposed on the third storage medium sub-layer 407b3, wherein the fourth storage medium sub-layer 407b4 has a higher silicon element content than the third storage medium sub-layer 407b3, and thus may also be referred to as "silicon-rich silicon nitride". In addition, according to an embodiment of the present disclosure, the thickness of the fourth storage medium sub-layer 407b4 may also be 2nm to 10nm.

According to embodiments of the present disclosure, the storage gate dielectric stack 407 may be subjected to a high temperature anneal process using, for example, one or more gases of nitrogen (or argon), hydrogen (and/or oxygen), a laughing gas (or a nitric oxide gas) in a suitable ratio combination to convert the silicon-rich silicon nitride of the fourth storage medium sub-layer 407b4 under the second oxide layer 407c into silicon oxynitride while densifying the second oxide layer 407c to improve the leakage characteristics of the second oxide layer (blocking oxide layer) 407 c. According to an embodiment of the present disclosure, the annealing temperature is 800 ℃ to 950 ℃, and the annealing time is 10 minutes to one hour.

Those skilled in the art will recognize that while embodiments of the present disclosure have been described above in connection with storage medium layer 407b comprising four storage medium sublayers 407b 1-407 b4 as examples, the present disclosure is not so limited. For example, the storage medium layer 407b may also include more or fewer than four storage medium sublayers.

It should be noted that the silicon element content described herein refers to the relative proportions of the chemical elements in the storage medium sublayers, measured in atomic relative amounts, e.g., the Si/N relative proportion in the second storage medium sublayer 407b2 is higher than that in the first storage medium sublayer 407b1, as the second storage medium sublayer 407b2 has properties closer to those of silicon, For example having a specific Si content ₃ N ₄ High refractive index and high trap density, while the first 407b1 and third 407b3 storage medium sublayers have a higher refractive index than Si ₃ N ₄ Is a property of (a).

According to an embodiment of the present disclosure, the first gate electrode layer 408 may be used to subsequently form the gate electrode 116 of the first memory transistor MS110 and the gate electrode 136 of the second memory transistor MS130 of the flash memory cell MC 100, for example, as described above with reference to fig. 1. Thus, as described above, the first gate electrode layer 408 may comprise, for example, polysilicon, a metal gate, a metal silicide, or a combination thereof, in accordance with embodiments of the present disclosure. According to embodiments of the present disclosure, the first gate electrode layer 408 may be formed by, for example, a deposition or sputtering process. For example, in the case where the first gate electrode layer 408 includes polysilicon, the first gate electrode layer 408 may be formed to have a thickness of 10nm to 200nm using a low-pressure chemical vapor deposition process.

In the case where the first gate electrode layer 408 includes polysilicon, an N-type impurity such as phosphorus or arsenic may be added within the first gate electrode layer 408 using, for example, an in-situ doping or ion implantation method, according to an embodiment of the present disclosure. Alternatively, in the case where the first gate electrode layer 408 includes polysilicon, a P-type impurity such as boron or indium may be further added within the first gate electrode layer 408 to reduce the fermi potential of the first gate electrode layer 408, thereby increasing the electron barrier height of the first gate electrode layer 408 and the second oxide layer (blocking oxide layer) 407c thereunder to improve the erase characteristics and reliability of the memory transistor in the flash memory cell, according to an embodiment of the present disclosure.

Alternatively, although not shown in the drawings, in the case where the first gate electrode layer 408 includes polysilicon, a high work function metal interface layer may be formed between the second oxide layer (blocking oxide layer) 407c and the first gate electrode layer 408 according to an embodiment of the present disclosure. Alternatively, the first gate electrode layer 408 may be formed directly using a high work function metal material according to embodiments of the present disclosure. According to embodiments of the present disclosure, a metallic interfacial layer or metallic material, such as titanium or titanium nitride, having a work function greater than that of polysilicon may increase the electron barrier height of the first gate electrode layer 408 and the second oxide layer (blocking oxide layer) 407c thereunder to improve the erase characteristics and reliability of the memory transistor in the flash memory cell.

The hard mask barrier layer 409 may include, for example, silicon oxide, silicon nitride, silicon glass, amorphous silicon, or a combination of the above materials, according to embodiments of the present disclosure. The hard mask barrier layer 409 may be formed by processes such as oxidation, high temperature thermal oxidation, deposition, or sputtering, according to embodiments of the present disclosure. For example, a hard mask barrier layer 409 comprising silicon oxide may be sequentially formed over the first gate electrode layer 408 by a low pressure chemical vapor deposition process to a thickness of about 10nm to 50nm.

Subsequently, referring to fig. 3, in step S305, as shown in fig. 4E, according to an embodiment of the present disclosure, the stacked structure 411 in the region other than the gate regions of the memory transistors of the flash memory cell (e.g., the first memory transistor MS110 and the second memory transistor MS130 of the flash memory cell MC 100 described above with reference to fig. 1) may be removed by patterning, that is, the hard mask barrier layer 409, the first gate electrode layer 408, and the memory gate dielectric stack 407 are sequentially removed such that the surface of the substrate 401 is exposed in the region other than the gate regions of the memory transistors of the flash memory cell. Accordingly, as shown in fig. 4E, a first trench 412a and a second trench 412b may be formed in the first region NVMR, wherein a gate structure of a gate transistor of a flash memory cell (e.g., gate transistor MG 120 of flash memory cell MC 100 described above with reference to fig. 1) may be subsequently formed in the first trench 412 a. In addition, as further described below, the remaining stack structure 411 in the first region NVMR may form a gate structure of a storage transistor of the flash memory cell.

Subsequently, as shown in fig. 4E, an isolation layer 413 may be formed on the exposed surface of the substrate 401 and the sidewalls and/or over the remaining stacked structure 411 by, for example, a thermal oxidation, a high temperature thermal oxidation, or a low pressure chemical vapor deposition process, according to embodiments of the present disclosure. According to embodiments of the present disclosure, the isolation layer 413 may comprise silicon oxide, silicon oxynitride, silicon nitride, or a combination of the above materials, having a thickness of between about 5nm and 30 nm.

Subsequently, as shown in fig. 4E, according to an embodiment of the present disclosure, the isolation layer 413 over the substrate 401 and/or the stacked structure 411 may be removed by anisotropic and/or isotropic etching while the isolation layer 413 remains at the stacked structure 411 sidewall to form an isolation between the gate structure of the memory transistor and the gate structure of the gate transistor of the flash memory cell, wherein the isolation layer 413 formed on the sidewall of the first trench 412a may correspond to the first isolation portion 124 and the second isolation portion 125 of the flash memory cell MC 100 described above with reference to fig. 1, for example.

Subsequently, referring to fig. 3, in step S306, as shown in fig. 4F, a well region of a MOS transistor may be formed in the second region MOSR through a second implantation process according to an embodiment of the present disclosure. As described above, according to embodiments of the present disclosure, the MOS transistors in the second region MOSR may be one or more of low-voltage LV-MOS transistors, interface IO-MOS transistors (not shown), and high-voltage HV-MOS transistors. For example, as shown in fig. 4D, well regions PW and NW (not shown) of the low voltage LV-MOS transistor and well regions HVPW and HVNW (not shown) of the high voltage HV-MOS transistor may be formed in the second region MOSR through a second implantation process.

Further, as shown in fig. 4F, according to an embodiment of the present disclosure, the second channel layer 406 of the MOS transistor may also be formed in the second region MOSR through the second implantation process. As shown in fig. 4F, the second channel layer 406 may include a channel region of a low voltage LV-MOS transistor and a channel region of a high voltage HV-MOS transistor, according to an embodiment of the disclosure.

Similar to the first implantation process described above with reference to fig. 4C, the second implantation process may include at least one of the following process steps according to embodiments of the present disclosure: a second well region implant, a second anti-punch through implant, and a second turn-on implant. According to embodiments of the present disclosure, the second well region implant, the second anti-punch-through implant, and the second turn-on implant may all be implemented as ion implants. In addition, the ion species, dose, energy used in each process step in the second well region implant, the second anti-punch through implant, and the second turn-on implant may be the same or different.

According to an embodiment of the present disclosure, in the second region MOSR, the order of the second implantation process for the low voltage LV-MOS transistor, the second implantation process for the interface IO-MOS transistor, and the second implantation process for the high voltage HV-MOS transistor may be arbitrarily combined. For example, a second implantation process for low voltage LV-MOS transistors may be performed first, followed by a second implantation process for interface IO-MOS transistors, and finally followed by a second implantation process for high voltage HV-MOS transistors.

Subsequently, referring to fig. 3, in step S307, as shown in fig. 4G, a channel region 414 of a gate transistor of a flash memory cell (e.g., gate transistor MG 120 of flash memory cell MC 100 described above with reference to fig. 1) may be formed by patterning a third implantation process performed in first trench 412a, which may correspond to channel region 121 of gate transistor MG 120 of flash memory cell MC 100 described above with reference to fig. 1, for example, according to an embodiment of the present disclosure. According to embodiments of the present disclosure, the third implantation process may comprise at least one of the following process steps: a third anti-punch-through injection and a third turn-on injection. According to embodiments of the present disclosure, both the third anti-punch-through implant and the third turn-on implant may be implemented as ion implants, wherein the ion species, dose, energy used in the third anti-punch-through implant and the third turn-on implant may be the same or different.

For example, for the N-type flash memory cell (or NVM transistor) according to the present embodiment, the third anti-punch-through implant may use P-type impurity ions, such as boron ions or boron difluoride ions, to form a P-type second punch-through barrier (not shown) at a proper depth of the substrate secondary surface of the gate transistor of the flash memory cell (such as the gate transistor MG 120 of the flash memory cell MC 100 described above with reference to fig. 1), so that leakage current may be suppressed and source-drain punch-through voltage may be increased. According to embodiments of the present disclosure, the second punch-through barrier may have a P-type impurity concentration higher than that of the first punch-through barrier.

Further, according to embodiments of the present disclosure, the third turn-on implant may form the P-type channel region 414 of the gate transistor of the flash memory cell at the substrate surface under the first trench 412a using P-type impurity ions, such as boron ions, boron difluoride ions, or indium ions, so that the threshold voltage of the gate transistor may be adjusted to be greater than 0V and less than 1V. As described above, according to embodiments of the present disclosure, the channel region 414 of the gate transistor of the flash memory cell may have a P-type impurity concentration higher than that of the channel region of the storage transistor of the flash memory cell.

According to embodiments of the present disclosure, the first turn-on implant process step in the first implant process and the third turn-on implant process step in the subsequent third implant process may adjust and control the doping concentration of the channel regions of the memory transistor (e.g., the first memory transistor MS110 and the second memory transistor MD 130 of the flash memory cell MC 100 described above with reference to fig. 1) and the gating transistor (e.g., the gating transistor MG 120 of the flash memory cell MC 100 described above with reference to fig. 1), respectively, by controlling the doping concentration, e.g., as described above, such that the doping concentration of the channel region of the memory transistor is lower than the doping concentration of the channel region of the gating transistor. Further, the threshold voltages of the storage transistor and the gate transistor of the flash memory cell can be adjusted and controlled so that better cell read-write performance and off-state performance can be obtained.

Subsequently, referring to fig. 3, in step S308, after the wafer is pre-cleaned, gate dielectric layers of the gate transistors of the flash memory cells in the first region NVMR and the gate dielectric layers of the MOS transistors in the second region MOSR, such as the gate dielectric layers 415 of the low-voltage LV-MOS transistor and the high-voltage HV-MOS transistor shown in fig. 4H, may be formed on the surface of the exposed substrate 401 by a gate oxide process, as shown in fig. 4H, according to an embodiment of the present disclosure. It should be noted that, as shown in fig. 4H, the gate dielectric layer 415 is also formed concurrently at the bottom of the second trench 412b in the first region NVMR, which may be removed simultaneously with the removal of the second gate electrode layer 418 in the second trench 412b in step S311 of fig. 3 described later in connection with fig. 4K.

Gate dielectric layer 415 may comprise silicon oxide, silicon oxynitride, hafnium oxide, or a combination thereof, in accordance with embodiments of the present disclosure. Further, in accordance with embodiments of the present disclosure, the gate oxide process used to form gate dielectric layer 415 may be a gate oxide process commonly used in standard CMOS processes. For example, when silicon oxide is used to form the gate dielectric layer, the gate oxide process may be thermal oxidation, high temperature thermal oxidation, low pressure chemical vapor deposition, in situ vapor oxidation, atomic layer deposition, etc., and the gate dielectric layer is typically formed to a thickness of 1nm to 20nm.

According to an embodiment of the present disclosure, according to configuration requirements of MOS transistors in the second region MOSR, a plurality of gate oxide processes may be combined such that the gate dielectric layers (not shown) of the low voltage LV-MOS transistor, the interface IO-MOS transistor, and the gate dielectric layer 415 of the high voltage HV-MOS transistor have different thicknesses from each other, and the gate dielectric layer 415 of the gate transistor of the flash memory cell may be formed to have the same thickness as the gate dielectric layer 415 of any one of the low voltage LV-MOS transistor, the interface IO-MOS transistor, and the high voltage HV-MOS transistor.

Subsequently, referring to fig. 3, in step S309, as shown in fig. 4I, a second gate electrode layer 418 and an etching hard mask layer 419 may be sequentially formed on the entire surface of the substrate 401, particularly over the gate dielectric layer 415 and the stack structure 411 (including the isolation layers 413 on both sides thereof), according to an embodiment of the present disclosure. According to embodiments of the present disclosure, etching the hard mask layer 419 may be used to optimize the etching process of the second gate electrode layer 418 in a subsequent step, and thus may be omitted in some simplified process flows.

According to an embodiment of the present disclosure, the second gate electrode layer 418 may be used to subsequently form the gate electrode 123 of the gate transistor MG 120 of the flash memory cell MC 100, for example, as described above with reference to fig. 1. Further, the second gate electrode layer 418 may be used to subsequently form gate electrodes of the respective MOS transistors in the second region MOSR. According to embodiments of the present disclosure, the second gate electrode layer 418 may be formed by, for example, a deposition or sputtering process. The second gate electrode layer 418 may include, for example, polysilicon, metal silicide, or a combination thereof, according to embodiments of the present disclosure. In the case where the second gate electrode layer 418 includes polysilicon, the second gate electrode layer 418 may be formed to have a thickness of 50nm to 500nm using a low-pressure chemical vapor deposition process according to an embodiment of the present disclosure. It should be noted that, according to embodiments of the present disclosure, the thickness of the second gate electrode layer 418 needs to be large enough so that the first trench 412a and the second trench 412b are filled so that the second gate electrode layer 418 has a flat upper surface in the first region NVMR, and the upper surface of the second gate electrode layer 418 in the first region NVMR is higher than the upper surface of the second gate electrode layer 418 in the second region MOSR. Further, according to an embodiment of the present disclosure, the upper surface of the second gate electrode layer 418 is higher than the upper surface of the first gate electrode layer 408.

According to embodiments of the present disclosure, the etch hard mask layer 419 may include, for example, silicon oxide, silicon nitride, silicon glass, or a combination of the above materials. According to embodiments of the present disclosure, the etch hard mask layer 419 may be formed by, for example, oxidation, high temperature thermal oxidation, deposition, or a sputtering process. For example, an etched hard mask layer 419 of silicon oxide may be formed on the second gate electrode layer 418 by a low pressure chemical vapor deposition process to a thickness of 20nm to 100nm.

Subsequently, referring to fig. 3, in step S310, as shown in fig. 4J, the etched hard mask layer 419, the second gate electrode layer 418, and the gate dielectric layer 415 in the portion other than the gate region of the MOS transistor in the second region MOSR may be removed by, for example, patterning and selective etching processes according to an embodiment of the present disclosure. In this way, the gate structure of the MOS transistor in the second region MOSR can be formed. Further, as shown in fig. 4J, according to an embodiment of the present disclosure, the etched hard mask layer 419 in the first region NVMR and a portion of the second gate electrode layer 418 may be concurrently removed until the upper surface of the stack structure 411, i.e., the upper surface of the hard mask barrier layer 409 is exposed while the second gate electrode layer 418 is filled in the first trench 412a and the second trench 412 b. Further, as shown in fig. 4J, the second gate electrode layer 418 filled in the first trench 412a in the first region NVMR may correspond to, for example, the gate electrode 123 of the gate transistor MG 120 of the flash memory cell MC 100 described above with reference to fig. 1, and the remaining second gate electrode layer 418 in the second region MOSR may form the gate electrode of the MOS transistor.

Subsequently, referring to fig. 3, in step S311, as shown in fig. 4K, a patterned mask layer, which may be a patterned photoresist layer formed using a standard photolithography process and includes openings corresponding to the second trenches 412b, may be formed in the first region NVMR by patterning, for example, according to an embodiment of the present disclosure. Subsequently, the second gate electrode layer 418 and the gate dielectric layer 415 thereunder, which are exposed through the openings, i.e., not covered by the photoresist layer, may be removed by an anisotropic etching process. That is, the second gate electrode layer 418 and the gate dielectric layer 415 in the second trench 412b are removed, and the second gate electrode layer 418 and the gate dielectric layer 415 in the first trench 412a remain, thereby forming a gate structure of the memory transistor. Accordingly, the hard mask barrier 409 may correspond to, for example, the hard mask barrier 117 of the first memory transistor MS110 and the hard mask barrier 137 of the second memory transistor MD 130 of the flash memory cell MC 100 described above with reference to fig. 1.

Subsequently, referring to fig. 3, in step S312, as shown in fig. 4L, the flash memory cells of the first region NVMR and the lightly doped source drain regions 420 of the transistors of the second region MOSR may be formed by one or more lightly doped source drain (LDD) patterning according to an embodiment of the present disclosure.

According to embodiments of the present disclosure, lightly doped source drain regions 420 may be formed by, for example, an ion implantation process. Further, according to embodiments of the present disclosure, the ion implantation process used to form the lightly doped source drain region 420 of the flash memory cell in the first region NVMR and the ion implantation process used to form the lightly doped source drain region 420 of the MOS transistor in the second region MOSR may be the same or different in ion species, dose, energy. Further, according to embodiments of the present disclosure, the ion implantation process for forming the lightly doped source drain region 420 of the flash memory cell in the first region NVMR may be the same as the ion implantation process for forming the lightly doped source drain region 420 of at least one transistor (e.g., low voltage LV-MOS transistor, interface IO-MOS transistor, or high voltage HV-MOS transistor) in the second region MOSR, e.g., using the same ion species, dose, and/or energy.

For example, for an N-type flash memory cell (or NVM transistor) according to the present embodiment, the ion implantation process for forming its lightly doped source drain region 420 may use N-type impurity ions, such as phosphorus ions or arsenic ions, to form an N-type lightly doped source drain region 420 at the source drain region surface of the flash memory cell.

Alternatively, according to an embodiment of the present disclosure, P-type impurity ions, such as boron ions or boron difluoride ions, may be additionally implanted before performing the ion implantation process for forming the lightly doped source drain region 420 of the flash memory cell to form a P-type cladding region (P-Halo) (not shown) outside the lightly doped source drain region 420 of the flash memory cell, so as to improve the punch-through characteristics and storage characteristics of the flash memory cell.

Subsequently, referring to fig. 3, in step S313, as shown in fig. 4M, sidewalls (spacers) 421 may be formed concurrently on both sides of the gate structures of the flash memory cells in the first region NVMR and the MOS transistors in the second region MOSR through sidewall processes commonly used in integrated circuit processes according to an embodiment of the present disclosure. For example, the sidewall process may first deposit one or more isolation dielectric layers on the surface of the substrate structure, and then remove the isolation dielectric layer over the substrate structure using an anisotropic etching process, thereby forming sidewalls 421.

Subsequently, as shown in fig. 4M, according to an embodiment of the present disclosure, the flash memory cell of the first region NVMR and the heavily doped source drain region 422 of the transistor of the second region MOSR may be formed by a heavily doped source drain implantation process.

As shown in fig. 4M, the lightly doped source drain region 420 and the heavily doped source drain region 422 of the flash memory cell in the first region NVM may together correspond to, for example, the source region 140 and the drain region 150 of the flash memory cell MC 100 described above with reference to fig. 1.

Subsequently, referring to fig. 3, in step S314, as shown in fig. 4N, an inter-polysilicon dielectric layer 420 may be deposited on the entire surface of the semiconductor device by, for example, a deposition process according to an embodiment of the present disclosure. The inter-polysilicon dielectric layer 420 may comprise, for example, silicon oxide, silicon nitride, silicon glass, or a combination thereof, in accordance with embodiments of the present disclosure.

Subsequently, as shown in fig. 4N, according to an embodiment of the present disclosure, an upper surface of the semiconductor device may be planarized by, for example, a CMP process and an upper surface of the gate structure of the low voltage LV-MOS transistor in the second region, i.e., an upper surface of the etched hard mask layer 419 in the gate region thereof, and an upper surface of the gate structure of the gate transistor in the first region NVMR, i.e., an upper surface of the second gate electrode layer 418 in the gate region thereof, may be exposed.

Subsequently, as shown in fig. 4N, according to an embodiment of the present disclosure, the gate structure of the low voltage LV-MOS transistor in the second region may be removed by an etching process, i.e., the etching hard mask layer 419, the second gate electrode layer 418, and the gate dielectric layer 415 are sequentially removed, and the gate structure of the gate transistor in the first region NVMR is removed, i.e., the second gate electrode layer 418 and the gate dielectric layer 415 in the first trench 412a are sequentially removed, such that the upper surface of the substrate 401 is exposed in the gate regions of the low voltage LV-MOS transistor and the gate transistor.

Subsequently, referring to fig. 3, in step S315, as shown in fig. 4O, a gate structure including a high-K gate dielectric layer 416 made of a high-K material and a metal gate 417 may be formed in gate regions of the low-voltage LV-MOS transistor and the gate transistor by, for example, deposition, etching, and CMP processes according to an embodiment of the present disclosure. According to embodiments of the present disclosure, the high-K material may have a dielectric constant of about 4 to 20 or more. The high-K material may include hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide, or strontium titanium oxide. In accordance with embodiments of the present disclosure, high-K gate dielectric layer 416 may be formed from a composite layer comprising two or more of the foregoing high-K materials. In accordance with an embodiment of the present disclosure, the metal gate 417 may include, for example, titanium nitride, tantalum nitride, tungsten nitride, ruthenium oxide iridium, iridium oxide, platinum, molybdenum oxide, titanium nitride/tungsten stacks, or tungsten nitride/tungsten stacks.

In fact, steps S314 and S315 described above with reference to fig. 4N and 4O may be standard HKMG metal replacement gate processes (or back gate processes) for replacing the gate structures of the low voltage LV-MOS transistors in the second region and the gate transistors in the first region NVMR with HKMG gate structures.

Those skilled in the art will recognize that although in the embodiments shown in fig. 3 and 4A to 4O, the gate structures of the low voltage LV-MOS transistor in the second region MOSR and the gate transistor in the first region NVMR are replaced with HKMG gate structures, the present disclosure is not limited thereto. According to the concepts of the present disclosure, at least the gate structures of the low-voltage LV-MOS transistors in the second region MOSR, the interface IO-MOS transistors and the high-voltage HV-MOS transistors, and the gate transistors in the first region NVMR should be replaced with HKMG gate structures in the low-voltage LV-MOS transistors in the second region MOSR. According to an alternative embodiment of the present disclosure, only the gate structure of the low voltage LV-MOS transistor in the second region MOSR may be replaced with the HKMG gate structure, and the interface IO-MOS transistor and the high voltage HV-MOS transistor in the second region MOSR and the gate transistor in the first region NVMR may still maintain the original gate structure including the gate dielectric layer 415 and the second gate electrode layer 418. According to another alternative embodiment of the present disclosure, in addition to replacing the gate structures of the low voltage LV-MOS transistors in the second region MOSR and the gate transistors in the first region NVMR with HKMG gate structures, the gate structures of the interface IO-MOS transistors and/or the high voltage HV-MOS transistors in the second region MOSR may be replaced with HKMG gate structures. All such alternative embodiments are intended to be within the scope of the present disclosure.

Furthermore, according to embodiments of the present disclosure, the materials of the high-K gate dielectric layer 416 and the metal gate 417 in the HKMG gate structure of the low-voltage LV-MOS transistor and/or the interface IO-MOS transistor and/or the high-voltage HV-MOS transistor in the second region MOSR and the HKMG gate structure of the gate transistor in the first region NVMR may be the same or different.

Although not shown, a buffer layer may also be formed between high-K gate dielectric layer 416 and metal gate 417 in accordance with embodiments of the present disclosure. According to embodiments of the present disclosure, the buffer layer may include work function modulating metal materials such as titanium nitride, tantalum, titanium aluminum, and the like. Further, according to embodiments of the present disclosure, the materials of the buffer layer in the HKMG gate structure of the gate transistor in the first region NVMR and the NMOS transistor (and PMOS transistor) in the MOS transistor in the second region MOSR may be the same or different to obtain different threshold voltages by adjusting work functions.

To this end, according to the embodiment of the present disclosure, the front end manufacturing process of the integration process of the flash memory cell in the first region NVMR and the MOS transistor in the second region MOSR is completed.

Finally, according to embodiments of the present disclosure, one or more metal connection layers and corresponding contact and via holes may be formed through a back-end fabrication process commonly used in integrated circuit processes, thereby forming electrical connections between the flash memory cells in the first region NVMR and the transistors in the second region MOSR.

Accordingly, embodiments of a method for fabricating a semiconductor device including an integrally formed non-volatile memory (NVM) transistor and Metal Oxide Semiconductor (MOS) transistor according to the present disclosure are described. The foregoing has been presented for purposes of illustration a limited number of possible embodiments of the present disclosure. Although the present disclosure has been described with reference to embodiments thereof, those skilled in the art will appreciate that various modifications and changes can be made to the embodiments of the disclosure without departing from the spirit and scope of the disclosure as disclosed in the appended claims.

Although numerous details are contained herein, these details should not be construed as limitations on the scope of the disclosure or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features that are described herein in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Furthermore, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

Claims

1. A method for manufacturing a semiconductor device,

wherein the semiconductor device includes a first region in which a plurality of flash memory cells are formed and a second region in which a metal oxide semiconductor MOS transistor is formed, and wherein each flash memory cell includes two memory transistors and one gate transistor disposed between the two memory transistors,

the method comprises the following steps:

providing a semiconductor substrate and forming an isolation structure therein;

forming a storage gate dielectric stack and a first gate electrode layer of the storage transistor;

forming a gate structure of the memory transistor by patterning the memory gate dielectric stack and the first gate electrode layer;

forming a gate dielectric layer and a second gate electrode layer of the gate transistor and the MOS transistor concurrently;

concurrently forming a gate structure of the MOS transistor and a gate structure of the gate transistor; and

and replacing the gate structure of the MOS transistor with a high-K gate dielectric layer and a metal gate.

2. The method of claim 1 wherein the gate structure of the memory transistor comprises, vertically from bottom to top, a channel region, the memory gate dielectric stack, the first gate electrode layer and a hard mask barrier,

The gate structure of the gating transistor comprises a channel region, the gate dielectric layer and the second gate electrode layer which are sequentially arranged along the vertical direction.

3. The method of claim 1, wherein an upper surface of the second gate electrode layer is higher than an upper surface of the first gate electrode layer.

4. The method of claim 1, wherein the MOS transistors disposed in the second region comprise one or more of low voltage MOS transistors, interface MOS transistors, or high voltage MOS transistors, and

the method comprises the steps of replacing a gate structure of the MOS transistor with a high-K gate dielectric layer and a metal gate, and replacing the gate structure of the low-voltage MOS transistor with at least the high-K gate dielectric layer and the metal gate.

5. The method of claim 1, further comprising: and replacing the gate structure of the gating transistor with a high-K gate dielectric layer and a metal gate.

6. The method of claim 1, wherein flash memory cells in the first region are isolated by a first isolation structure, MOS transistors in the second region are isolated by a second isolation structure, and the first region and the second region are isolated by the first isolation structure and/or the second isolation structure, and

Wherein the first isolation structure is the same as or different from the second isolation structure.

7. The method of claim 1, further comprising:

performing a first implantation process for forming a well region of the flash memory cell and a channel region of the memory transistor, and for adjusting a threshold voltage of the memory transistor;

performing a second implantation process for forming a well region and a channel region of the MOS transistor and for adjusting a threshold voltage of the MOS transistor; and

performing a third implantation process for forming a channel region of the gate transistor and for adjusting a threshold voltage of the gate transistor,

wherein the ion species, dose and/or energy of the first implantation process and the third implantation process are the same or different.

8. The method of claim 7, wherein the second implantation process is performed after forming a gate structure of the memory transistor by patterning the memory gate dielectric stack and the first gate electrode layer.

9. The method of claim 7, wherein the first and third implantation processes are performed such that a doping concentration of a channel region of the memory transistor is lower than a doping concentration of a channel region of the gate transistor.

10. The method of claim 1 wherein the storage gate dielectric stack comprises a first oxide layer, a storage dielectric layer, and a second oxide layer from bottom to top in a vertical direction,

wherein the storage medium layer comprises a first storage medium sub-layer to a third storage medium sub-layer which are formed by silicon nitride from bottom to top along the vertical direction, and

wherein the second storage medium sub-layer has a higher silicon element content than the first storage medium sub-layer and the third storage medium sub-layer.

11. The method of claim 10, wherein the storage medium layer further comprises a fourth storage medium sub-layer over the third storage medium sub-layer, and

wherein the fourth storage medium sub-layer has a higher silicon element content than the third storage medium sub-layer.

12. The method of claim 1, further comprising: and forming a high work function metal interface layer between the storage gate dielectric stack and the first gate electrode layer.

13. The method of claim 1, further comprising: an isolation layer is formed for isolating the gate transistor and the memory transistor.

14. The method of claim 1, further comprising: and forming a buffer layer between the high-K gate dielectric layer and the metal gate.

15. The method of claim 5, further comprising: and forming a buffer layer between the high-K gate dielectric layer and the metal gate.