CN117294965A - Image sensor based on back-illuminated technology - Google Patents

Abstract

The application provides an image sensor based on back-illuminated technology, comprising: the pixel array, the analog processing circuit, the digital processing circuit and the frame buffer circuit; the analog processing circuit is connected with the pixel array and is used for quantitatively reading pixel signals after the pixel units are exposed row by row so as to obtain row quantized signals; the frame buffer circuit is connected with the analog processing circuit and is used for buffering the line quantized signals line by line into line buffer signals; the digital processing circuit is connected with the frame buffer circuit and is used for processing the line buffer signal. The image sensor based on the back illumination process provided by the application can improve the quantization speed of the analog processing circuit by increasing the frame buffer circuit for temporarily buffering the signals quantized line by the analog processing circuit, further greatly shorten the quantization window of the whole frame image, realize high frame rate quantization and achieve the image effect similar to a global shutter.

Description

Image sensor based on back-illuminated technology

Technical Field

The application relates to the technical field of imaging, in particular to an image sensor based on a back-illuminated process.

Background

The image sensor converts the light image on the light sensing surface into an electric signal in a corresponding proportional relation with the light image by utilizing the photoelectric conversion function of the photoelectric device. In contrast to light sensitive elements of "point" light sources such as photodiodes, phototriodes, etc., an image sensor is a functional device that divides the light image on its light-receiving surface into a number of small cells that are converted into a usable electrical signal. The exposure modes of the existing image sensor comprise a rolling shutter, a global shutter and the like, and the image sensor is gradually developed to have the characteristics of small volume, light weight, high integration level, high resolution, low power consumption, long service life, low price and the like, and is widely applied to various industries.

In the process of designing and implementing the present application, the inventors found that at least the following problems exist: the characteristic of the rolling shutter image sensor is that the frame rate of the rolling shutter image sensor is limited by the cycle waiting time of line quantization and line data processing, namely the time of pixel signal quantization by an analog circuit is not matched with the time of processing and reading by a digital circuit, so that the frame rate of the rolling shutter image sensor is limited; in addition, the progressive exposure of the rolling shutter is quantified, and the image of the photographed moving object is smeared due to the inter-line exposure time difference.

The foregoing description is provided for general background information and does not necessarily constitute prior art.

Disclosure of Invention

In order to alleviate the above problems, the present application provides an image sensor based on a back-illuminated process, specifically, comprising: the pixel array, the analog processing circuit, the digital processing circuit and the frame buffer circuit;

the analog processing circuit is connected with the pixel array and is used for quantitatively reading pixel signals after the pixel units are exposed row by row so as to obtain row quantized signals;

the frame buffer circuit is connected with the analog processing circuit and is used for buffering the line quantized signals line by line into line buffer signals;

the digital processing circuit is connected with the frame buffer circuit and is used for processing the line buffer signal.

Optionally, the analog processing circuit in the image sensor includes a row driving unit and a quantization unit connected to each other, and the row driving unit is configured to drive and output a photosensitive voltage of each row of pixels to the quantization unit, so that the quantization unit performs quantization reading on the photosensitive voltage.

Optionally, the pixel array rectangle organized in rows and columns in the image sensor is disposed at the center of the silicon chip, and the analog processing circuit, the digital processing circuit and the frame buffer circuit are disposed at the sides of the pixel array.

Optionally, the analog processing circuitry in the image sensor is disposed on the silicon die adjacent to at least two adjacent sides of the pixel array.

Optionally, the frame buffer circuit and the analog processing circuit in the image sensor are disposed on the silicon chip with at least one adjacent side.

Optionally, the frame buffer circuit and the digital processing circuit in the image sensor are disposed on the silicon chip with at least one adjacent side.

Optionally, the digital processing circuit and the analog processing circuit in the image sensor are disposed on the silicon chip with at least one adjacent side;

and/or at least one side of the digital processing circuit is arranged at the edge of the silicon chip.

Optionally, the analog processing circuit in the image sensor is disposed adjacent to three adjacent sides of the pixel array, the three adjacent sides including two opposing column select sides and one row select side.

Optionally, in the image sensor, on the silicon chip, an area of the frame buffer circuit is larger than an area of the analog processing circuit, and an area of the frame buffer circuit is larger than an area of the digital processing circuit.

Optionally, the frame buffer circuit in the image sensor buffers the line quantized signal of a frame image into a line buffer signal of a frame image line by line, so as to acquire and send the frame buffer signal to the digital processing circuit;

and/or the frame buffer circuit buffers the line quantized signal of a frame image into a plurality of line buffer signals line by line so as to acquire and respectively send each line buffer signal to the digital processing circuit.

As described above, in the image sensor based on the back-illuminated process provided by the application, by adding the frame buffer circuit for temporarily buffering the signals quantized by the analog processing circuit line by line, the quantization speed of the analog processing circuit can be increased, the signal processing time of the digital processing circuit is not influenced, the quantization window of the whole frame of image is greatly shortened, the high frame rate quantization is realized, and the image effect similar to the global shutter is achieved.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.

Fig. 1 is a schematic structural diagram of an image sensor based on a backside illuminated process according to an embodiment of the present application.

Fig. 2 is a schematic diagram of a structure of an image sensor based on a backside illuminated process according to an embodiment of the present application.

Fig. 3 is a schematic diagram of a structure of an image sensor based on a backside illuminated process according to an embodiment of the present application.

Fig. 4 is a timing diagram of a frame buffer circuit and a digital processing circuit according to an embodiment of the present application.

Fig. 5 is a second timing diagram of a frame buffer circuit and a digital processing circuit according to an embodiment of the present application.

The realization, functional characteristics and advantages of the present application will be further described with reference to the embodiments, referring to the attached drawings. Specific embodiments thereof have been shown by way of example in the drawings and will herein be described in more detail. These drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the element defined by the phrase "comprising one … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element, and furthermore, elements having the same name in different embodiments of the present application may have the same meaning or may have different meanings, a particular meaning of which is to be determined by its interpretation in this particular embodiment or by further combining the context of this particular embodiment.

It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.

In one aspect, the present application provides an image sensor based on a backside illuminated process. Fig. 1 is a schematic structural diagram of an image sensor based on a backside illuminated process according to an embodiment of the present application.

Referring to fig. 1, in one embodiment, an image sensor includes: pixel array 10, analog processing circuit 20, digital processing circuit 30, and frame buffer circuit 40.

The analog processing circuit 20 is connected to the pixel array 10, and is configured to quantize and read pixel signals after exposing the pixel units row by row, so as to obtain row quantized signals. The frame buffer circuit 40 is connected to the analog processing circuit 20 for buffering the line quantized signal line by line into a line buffered signal. The digital processing circuit 30 is connected to the frame buffer circuit 40 for processing the line buffer signal.

The frame buffer circuit 40 is a buffer circuit for realizing frame buffering, and is capable of buffering the image signal quantized by the analog processing circuit 20, and is read and processed at any time when it is idle by the digital processing circuit 30. The addition of the frame buffer circuit 40 can enable the analog processing circuit 20 to rapidly quantize the pixel signals of the entire frame line by line regardless of the time required for the digital processing circuit 30 to process the quantized data, thereby shortening the quantization window time and improving the image processing speed of the image sensor.

By adding the frame buffer circuit 40 for temporarily buffering the quantized signal of the analog processing circuit 20 line by line, the quantization speed of the analog processing circuit 20 can be increased, the signal processing time of the digital processing circuit 30 is not affected, the quantization window of the whole frame image is greatly shortened, the high frame rate quantization is realized, and the image effect similar to a global shutter is achieved.

In one embodiment, the analog processing circuit 20 in the image sensor includes a row driving unit and a quantization unit connected to each other, and the row driving unit is configured to drive and output the photosensitive voltage of each row of pixels to the quantization unit, so that the quantization unit performs quantization reading on the photosensitive voltage.

The analog processing circuit 20 is responsible for amplifying, reducing noise, quantizing, etc. the voltage signal after the pixel line-by-line exposure. For example, the row driving unit may amplify and transfer charges induced by the pixels to drive the output photosensitive voltage, and the quantization unit further quantizes and reads the charges corresponding to the pixels to form quantized photosensitive data.

Fig. 2 is a schematic diagram of a structure diagram of an image sensor based on a backside illuminated process according to an embodiment of the present application.

Referring to fig. 2, in an embodiment, a pixel array 10 of an image sensor, which is organized in rows and columns, is rectangular and disposed in the center of a silicon wafer, and an analog processing circuit 20, a digital processing circuit 30 and a frame buffer circuit 40 are disposed at the sides of the pixel array 10.

The pixel array 10 may form a rectangular array on a silicon wafer in rows and columns as a photosensitive window of an image sensor. The pixel array 10 is arranged in the center of the silicon wafer, and light is collected towards the direction where light sensing is required. The central position of the silicon wafer is convenient for process manufacture, and can completely and comprehensively sense the light focused by the lens.

The analog processing circuit 20, the digital processing circuit 30 and the frame buffer circuit 40 are arranged at the side of the pixel array 10, and can be connected through metal wires in a silicon chip, and the number of transmission frames per second in the chip can reach about 100 FPS.

With continued reference to fig. 2, in one embodiment, the analog processing circuit 20 in the image sensor is disposed on the silicon in the following manner: adjoining at least two adjacent sides of the pixel array 10.

The analog processing circuit 20 performs processing by inputting a row selection signal to the row side of the pixel array 10, turning on one row of pixels of the pixel array 10 at a time, and reading out the corresponding pixel charges in at least one column at a time from the column selection side of the pixel array 10 by the analog processing circuit 20. Two adjacent sides are shown in fig. 2.

With continued reference to fig. 2, in one embodiment, the frame buffer circuit 40 of the image sensor is disposed on the silicon wafer in the following manner: has at least one adjacent side with the analog processing circuit 20.

The analog processing circuit 20 needs to send the image signal quantized line by line to the frame buffer circuit 40 for temporary storage. The analog processing circuit 20 is disposed adjacent to the frame buffer circuit 40, and can be directly connected through an on-chip metal interconnection line, so that the connection distance is shortened, and the information transmission and processing speed is increased. The frame buffer circuit 40 and the analog processing circuit 20 are shown in fig. 2 as having two contiguous sides.

With continued reference to fig. 2, in one embodiment, the digital processing circuit 30 in the image sensor is disposed on a silicon wafer in the following manner: has at least one adjacent side with the frame buffer circuit 40.

The digital processing circuit 30 may read the buffered quantized signal from the frame buffer circuit 40 for processing. The digital processing circuit 30 is disposed adjacent to the frame buffer circuit 40, and can be directly connected through an on-chip metal interconnection line, so that the connection distance is shortened, and the information transmission and processing speed is increased. Two adjoining sides are shown in fig. 2.

With continued reference to fig. 2, in one embodiment, the digital processing circuit 30 in the image sensor is disposed on a silicon wafer in the following manner: has at least one adjacent side with the analog processing circuit 20.

The digital processing circuit 30 is required to convert the pre-exposure row address digital signal, the sampling row address digital signal, the pre-exposure row transmission digital signal and the sampling row transmission digital signal into the pre-exposure row address analog signal, the sampling row address analog signal, the pre-exposure row transmission analog signal and the sampling row transmission analog signal, and output a transmission control signal capable of controlling the transmission transistor grid electrode in the pixel circuit based on the analog signal and the latch address analog signal, so as to gate each row of pixels, therefore, the digital processing circuit 30 is adjacently arranged with the analog processing circuit 20, and is directly connected through the on-chip metal interconnection line, so that the connection distance can be shortened, and the on-chip high-speed information transmission and processing can be provided.

Optionally, at least one side of digital processing circuit 30 is disposed at the edge of the silicon wafer.

Because the digital processing circuit 30 needs to transmit the processed pixel signals through the data interface, and can select parallel output or serial output data based on the requirement, the digital processing circuit 30 is arranged at the edge of the silicon chip, so that the data interface is convenient to set.

In fig. 2, the digital processing circuit 30 and the analog processing circuit 20 are shown with an adjacent side disposed on the silicon wafer and a side disposed at the edge of the silicon wafer.

Fig. 3 is a schematic diagram of a structure diagram of an image sensor based on a back-illuminated process according to an embodiment of the present application.

Referring to fig. 3, in one embodiment, the analog processing circuit 20 in the image sensor is disposed adjacent to three adjacent sides of the pixel array 10, wherein the three adjacent sides include two opposite column selection sides and one row selection side.

When the analog processing circuit 20 is directly connected or wired to two opposite column selection sides of the pixel array 10, the analog processing circuit 20 can simultaneously quantize and read two columns of pixel signals through one row selection signal, so that multi-row simultaneous reading and accelerated quantization can be realized.

Referring to fig. 2 and 3 in combination, in one embodiment, the area of the frame buffer circuit 40 is larger than the area of the analog processing circuit 20, and the area of the frame buffer circuit 40 is larger than the area of the digital processing circuit 30.

The larger the area of the frame buffer circuit 40, the more quantized data can be buffered, so that the analog processing circuit 20 and the digital processing circuit 30 are free from the limitation caused by the difference of signal processing speeds, and the image processing speed of the image sensor is greatly improved.

Fig. 4 is a timing diagram of a frame buffer circuit and a digital processing circuit according to an embodiment of the present application.

Alternatively, the frame buffer circuit 40 in the image sensor buffers the line quantized signal of one frame image line by line into a line buffer signal of one frame image to acquire and transmit the frame buffer signal to the digital processing circuit 30.

Referring to fig. 4, in an exemplary embodiment, after each frame of the complete image is buffered by the frame buffer circuit 40, the frame buffer circuit processes the read-out of the image information of one frame together with the digital processing circuit 30.

Fig. 5 is a second timing diagram of a frame buffer circuit and a digital processing circuit according to an embodiment of the present application.

Alternatively, the frame buffer circuit 40 buffers the line quantized signal of one frame image line by line into a plurality of line buffer signals to acquire and respectively transmit each line buffer signal to the digital processing circuit 30. In this way, the digital processing circuit 30 can be made to read out frame by frame.

Referring to fig. 5, in an exemplary embodiment, the frame buffer circuit 40 buffers one line of image signals at a time, and the digital processing circuit 30 reads out one line at a time in synchronization with the line-by-line readout, and reads out one line of image signals at a time for processing. In this way, the image signals are read out line by line, and the processing operations can be synchronized by the time frame buffer circuit 40 and the digital processing circuit 30, respectively.

As described above, the image sensor based on the back-illuminated process provided by the application can improve the quantization speed of the analog processing circuit by increasing the frame buffer circuit for temporarily buffering the signals quantized line by the analog processing circuit, does not affect the signal processing time of the digital processing circuit, further greatly shortens the quantization window of the whole frame image, realizes high frame rate quantization, achieves the image effect similar to the global shutter, and has the advantages of simple circuit design and small noise.

The embodiments of the intelligent terminal and the computer readable storage medium provided in the present application may include all technical features of any one of the embodiments of the method, and the expansion and explanation contents of the description are substantially the same as those of each embodiment of the method, which are not repeated herein.

The present embodiments also provide a computer program product comprising computer program code which, when run on a computer, causes the computer to perform the method in the various possible implementations as above.

The embodiments also provide a chip including a memory for storing a computer program and a processor for calling and running the computer program from the memory, so that a device on which the chip is mounted performs the method in the above possible embodiments.

It can be understood that the above scenario is merely an example, and does not constitute a limitation on the application scenario of the technical solution provided in the embodiments of the present application, and the technical solution of the present application may also be applied to other scenarios. For example, as one of ordinary skill in the art can know, with the evolution of the system architecture and the appearance of new service scenarios, the technical solutions provided in the embodiments of the present application are equally applicable to similar technical problems.

The foregoing embodiment numbers of the present application are merely for describing, and do not represent advantages or disadvantages of the embodiments.

The steps in the method of the embodiment of the application can be sequentially adjusted, combined and deleted according to actual needs.

The units in the device of the embodiment of the application can be combined, divided and pruned according to actual needs.

In this application, the same or similar term concept, technical solution, and/or application scenario description will generally be described in detail only when first appearing, and when repeated later, for brevity, will not generally be repeated, and when understanding the content of the technical solution of the present application, etc., reference may be made to the previous related detailed description thereof for the same or similar term concept, technical solution, and/or application scenario description, etc., which are not described in detail later.

In this application, the descriptions of the embodiments are focused on, and the details or descriptions of one embodiment may be found in the related descriptions of other embodiments.

The technical features of the technical solutions of the present application may be arbitrarily combined, and for brevity of description, all possible combinations of the technical features in the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the present application.

The foregoing description is only of the preferred embodiments of the present application, and is not intended to limit the scope of the claims, and all equivalent structures or equivalent processes using the descriptions and drawings of the present application, or direct or indirect application in other related technical fields are included in the scope of the claims of the present application.

Claims (10)

1. An image sensor based on a backside illuminated process, comprising: the pixel array, the analog processing circuit, the digital processing circuit and the frame buffer circuit;

the analog processing circuit is connected with the pixel array and is used for quantitatively reading pixel signals after the pixel units are exposed row by row so as to obtain row quantized signals;

the frame buffer circuit is connected with the analog processing circuit and is used for buffering the line quantized signals line by line into line buffer signals;

the digital processing circuit is connected with the frame buffer circuit and is used for processing the line buffer signal.

2. The image sensor of claim 1, wherein the analog processing circuit includes a row driving unit and a quantization unit connected to each other, the row driving unit for driving and outputting a photosensitive voltage of each row of pixels to the quantization unit so that the quantization unit performs quantization reading of the photosensitive voltage.

3. The image sensor of claim 1 wherein the pixel array rectangular shaped organized into rows and columns is disposed in the center of a silicon wafer, and the analog processing circuitry, digital processing circuitry, and frame buffer circuitry are disposed on the sides of the pixel array.

4. The image sensor of claim 3 wherein the analog processing circuitry is disposed on the silicon die adjacent to at least two adjacent sides of the pixel array.

5. The image sensor of claim 4 wherein the frame buffer circuit and the analog processing circuit are disposed on the silicon die with at least one adjacent side.

6. The image sensor of claim 5 wherein the digital processing circuit and the frame buffer circuit are disposed on the silicon die with at least one adjacent side.

7. The image sensor of claim 3, wherein the digital processing circuit and the analog processing circuit are disposed on the silicon die with at least one adjacent side;

and/or at least one side of the digital processing circuit is arranged at the edge of the silicon chip.

8. The image sensor of claim 3, wherein the analog processing circuit is disposed adjacent to three adjacent sides of the pixel array, the three adjacent sides including two opposing column select sides and one row select side.

9. The image sensor of claim 3, wherein an area of the frame buffer circuit is larger than an area of the analog processing circuit and an area of the frame buffer circuit is larger than an area of the digital processing circuit on the silicon wafer.

10. The image sensor of any one of claims 1-9, wherein the frame buffer circuit buffers line-by-line a line quantized signal of a frame image into a line buffered signal of a frame image to obtain and send the frame buffered signal to the digital processing circuit;

and/or the frame buffer circuit buffers the line quantized signal of a frame image into a plurality of line buffer signals line by line so as to acquire and respectively send each line buffer signal to the digital processing circuit.