CN117294627A - Flow control verification method, device, chip test equipment and readable storage medium - Google Patents
Flow control verification method, device, chip test equipment and readable storage medium Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0876—Network utilisation, e.g. volume of load or congestion level
- H04L43/0882—Utilisation of link capacity
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0805—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability
Abstract
The invention relates to the technical field of chip verification, and provides a flow control verification method, a flow control verification device, chip test equipment and a readable storage medium, wherein a chip to be verified comprises a plurality of sending modules, a plurality of receiving modules and a register, and the method comprises the following steps: acquiring a flow control back pressure signal sent by a target receiving module in a plurality of receiving modules, wherein the flow control back pressure signal represents whether the target receiving module needs flow control or not; acquiring a data transmission signal representing whether to transmit data or not sent by each transmission module and a receiving-transmitting mapping relation of each transmission module; and performing flow control verification on the target receiving module of the chip to be verified according to the flow control back pressure signal, the data transmission signal of each transmitting module and the receiving-transmitting mapping relation of each transmitting module. The invention can verify whether the flow control is normal or not under the scene that a plurality of transmission paths exist simultaneously.
Description
Technical Field
The present invention relates to the field of chip verification technologies, and in particular, to a method and apparatus for verifying a flow control, a chip test device, and a readable storage medium.
Background
When data is transmitted inside the ethernet chip, the transmitting module in the ethernet chip transmits the data to the receiving module, when the receiving module is congested, the buffer area may be burst up and packet loss may be caused, so in order to avoid this problem, the receiving module is generally required to inform the transmitting module whether the transmitting module can receive the data, and when the receiving module is about to be unable to receive the data, the transmitting module is required to stop transmitting the data, which is the flow control mechanism.
In the prior art, whether the current flow control is normal is judged according to whether the content of the transmitted data is correct or not, and only the flow control of only one transmission path can be verified in the mode of normal flow control. In the scenario that multiple transmission paths exist at the same time, the multiple transmission paths may affect each other, so that the verification manner in the prior art cannot verify the situation that the flow control is abnormal due to the mutual effect.
Disclosure of Invention
The invention aims to provide a flow control verification method, a flow control verification device, chip test equipment and a readable storage medium, which can verify whether flow control is normal or not under the condition that a plurality of transmission paths exist simultaneously.
Embodiments of the invention may be implemented as follows:
in a first aspect, the present invention provides a flow control verification method, applied to a chip test device, where the chip test device is electrically connected to a chip to be verified, where the chip to be verified includes a plurality of sending modules for sending data, a plurality of receiving modules for receiving data, and a register for configuring a transmit-receive mapping relationship of each sending module, where the transmit-receive mapping relationship of each sending module characterizes a mapping relationship between each sending module and a receiving module for receiving data sent by each sending module, and the method includes:
acquiring flow control back pressure signals sent by a target receiving module in a plurality of receiving modules, wherein the flow control back pressure signals represent whether the target receiving module needs flow control signals or not;
acquiring a data transmission signal representing whether to transmit data and a receiving-transmitting mapping relation of each transmission module, wherein the data transmission signal is sent by each transmission module;
and performing flow control verification on the target receiving module of the chip to be verified according to the flow control back pressure signal, the data sending signal of each sending module and the receiving-sending mapping relation of each sending module.
In an optional implementation manner, the step of performing flow control verification on the target receiving module of the chip to be verified according to the flow control back pressure signal, the data sending signal of each sending module and the sending-receiving mapping relationship of each sending module includes:
if the flow control back pressure signal is set to be effective and the plurality of sending modules send data according to the respective receiving and sending mapping relation, determining a target sending module with the receiving and sending relation with the target receiving module from the plurality of sending modules according to the receiving and sending mapping relation of each sending module;
judging whether each sending module normally sends data or not according to the data sending signal of each sending module;
if the target sending module does not have a module for sending data normally, and all other modules except the target sending module in the multiple sending modules send data normally, judging that the flow control of the target receiving module is normal, otherwise, judging that the flow control of the target receiving module is abnormal.
In an alternative embodiment, after the step of determining that the flow control of the target receiving module is abnormal, the method includes:
judging a module which normally transmits data in the target transmitting module and a module which does not normally transmit data in other modules except the target transmitting module in a plurality of transmitting modules as an abnormal transmitting module;
and judging that the flow control between the target receiving module and the abnormal sending module is abnormal.
In an alternative embodiment, the target receiving module is randomly determined from a plurality of receiving modules, the target receiving module is one, and the flow control back pressure signals of the other modules except the target receiving module are all set to be free of flow control.
In an optional implementation manner, the step of performing flow control verification on the target receiving module of the chip to be verified according to the flow control back pressure signal, the data sending signal of each sending module and the sending-receiving mapping relationship of each sending module includes:
if the flow control back pressure signal is set to be invalid, all other modules except for a target sending module which has a receiving-transmitting mapping relation with the target receiving module in the plurality of sending modules are set to not send data, and the target sending module is set to send data, judging whether each sending module normally sends data according to the data sending signal of each sending module;
and if the target sending module normally sends data and the modules for sending data do not exist in the other modules except the target sending module, judging that the flow control of the target receiving module is normal, otherwise, judging that the flow control of the target receiving module is abnormal.
In an alternative embodiment, the target receiving module is randomly determined from a plurality of receiving modules, the target receiving module is one, and the flow control back pressure information of the other modules except the target receiving module is set to be in need of flow control.
In an alternative embodiment, the data transmission signal includes two states, namely valid and invalid, and the step of determining, according to the data transmission signal of each of the transmission modules, whether each of the transmission modules normally transmits data includes:
and for any module to be confirmed in the plurality of sending modules, if the data sending signal of the module to be confirmed is in a valid state, judging that the module to be confirmed normally sends data, otherwise, judging that the module to be confirmed does not normally send data.
In a second aspect, the present invention provides a flow control verification device, applied to a chip test device, where the chip test device is electrically connected to a chip to be verified, where the chip to be verified includes a plurality of sending modules for sending data, a plurality of receiving modules for receiving data, and a register for configuring a transmit-receive mapping relationship of each sending module, where the transmit-receive mapping relationship of each sending module characterizes a mapping relationship between each sending module and a receiving module for receiving data sent by each sending module, and the device includes:
the acquisition module is used for acquiring flow control back pressure signals sent by a target receiving module in the plurality of receiving modules, wherein the flow control back pressure signals represent whether the target receiving module needs flow control signals or not;
the acquisition module is further configured to acquire a data transmission signal representing whether to transmit data sent by each transmission module and a transmit-receive mapping relationship of each transmission module;
and the verification module is used for carrying out flow control verification on the target receiving module of the chip to be verified according to the flow control back pressure signal, the data transmission signal of each transmission module and the receiving-transmitting mapping relation of each transmission module.
In a third aspect, the present invention provides a chip test apparatus, comprising a processor and a memory, the memory being configured to store a program, the processor being configured to implement the flow control verification method according to any one of the preceding embodiments when the program is executed.
In a fourth aspect, the present invention provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a flow control verification method as in any of the preceding embodiments.
Compared with the prior art, the embodiment of the invention provides a flow control verification method, a flow control verification device, chip test equipment and a readable storage medium, when a chip to be verified, which comprises a plurality of sending modules and a plurality of receiving modules, needs to be verified, flow control verification is carried out on the target receiving modules of the chip to be verified according to flow control back pressure signals sent by the target receiving modules in the plurality of receiving modules, data sending signals of each sending module and a receiving-transmitting mapping relation, and the flow control back pressure signals of the target receiving modules are validated or not and whether the data sending signals for sending data to the target receiving modules are consistent or not can be judged due to the fact that the receiving-transmitting mapping relation characterizes the mapping relation between each sending module and the receiving module for receiving the data sent by each sending module, so that accurate verification on whether flow control is normal or not is carried out when a plurality of sending channels exist in the chip to be verified.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a diagram showing a structural example of a chip according to the present embodiment.
Fig. 2 is an exemplary diagram of an application scenario provided in this embodiment.
Fig. 3 is a block diagram of a chip test apparatus according to the present embodiment.
Fig. 4 is a flowchart illustrating a flow chart of a flow control verification method according to the present embodiment.
Fig. 5 is a block diagram of a flow control verification device according to this embodiment.
Icon: 10-chip test equipment; 11-a processor; 12-memory; 13-bus; 20-chip; 100-flow control verification device; 110-an acquisition module; 120-verification module.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present invention, it should be noted that, if the terms "upper", "lower", "inner", "outer", and the like indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, or the azimuth or the positional relationship in which the inventive product is conventionally put in use, it is merely for convenience of describing the present invention and simplifying the description, and it is not indicated or implied that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus it should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, if any, are used merely for distinguishing between descriptions and not for indicating or implying a relative importance.
It should be noted that the features of the embodiments of the present invention may be combined with each other without conflict.
In the process of sending data through an ethernet chip, a sender sends the data to a receiver, when congestion occurs at a receiving end, a buffer area may be burst, so that to avoid this problem, the receiver is usually required to inform the sender whether the sender can receive the data, and when the receiver is about to fail to receive the data (for example, when the buffer area is full), the sending of the data needs to be stopped, which is a flow control mechanism. When the data volume stored by the later-stage module exceeds the full water line, the later-stage module sets the flow control signal line to be in an effective state through a flow control signal line fc, informs the earlier-stage module to stop sending data, and sets the flow control signal line fc to be in an ineffective state when the data volume stored by the later-stage module is lower than the full water line, so that the earlier-stage module can continue sending data.
Under the condition of only one flow control signal line, whether the flow control mechanism is correct is easy to check, and because when the flow control signal is generated and the back pressure flow control is not effective, errors such as buffer area bursting and packet loss and the like are necessarily caused to occur in a later module, therefore, only the flow control signal can be set to 1 and effectively ensured during verification, the mode can only be used for the condition that one flow control signal line exists, but in practical application, not all flow control is realized by only one flow control signal line, and the mode is not a simple one-to-one correspondence.
In view of this, the present embodiment provides a flow control verification method, apparatus, chip test device, and readable storage medium, which are capable of verifying whether a flow control is normal or not in a scenario where a plurality of transmission paths exist at the same time, which will be described in detail below.
Referring to fig. 1, fig. 1 is a schematic diagram of a chip structure provided in this embodiment, in fig. 1, a chip 20 includes four transmitting modules A, B, C, D and four receiving modules a ', B', C ', D', each corresponding to a register, each register of each transmitting module is configured with a transmit-receive mapping relationship, the transmit-receive mapping relationship characterizes a receiving module to which data sent by the transmitting module is to be sent, each receiving module corresponds to a scheduler, and each scheduler is configured to schedule data from different transmitting modules and send the data to the receiving module. Each receiving module is also provided with a flow control signal line, such as an arrow line pointing to the dispatcher from the receiving module in fig. 1, when the receiving module needs to flow control, the flow control back pressure signal sent by the flow control signal line is set to be effective, and then the sending module sending data to the receiving module does not send data any more.
It should be noted that fig. 1 is only an example of the chip 20, and in fact, the chip 20 may include more transmitting modules and receiving modules, or may include fewer transmitting modules and receiving modules than fig. 1, and the chip 20 in fig. 1 includes, but is not limited to, an ethernet chip, a memory chip, a sensor chip, and the like.
Referring to fig. 2, fig. 2 is an exemplary diagram of an application scenario provided by the present embodiment, in fig. 2, the chip test device 10 is electrically connected to the chip 20, the chip test device 10 may control to send test data to the chip 20 or stop sending test data, the test data may be sent to at least one of A, B, C, D modules of the chip 20 according to different settings, and the chip test device 10 may obtain, from the chip 20, a data sending signal of the A, B, C, D module, a back pressure signal of the a ', B', C ', D' module, and a transmit-receive mapping relation configured in each register, by using a register and a scheduler, and the chip test device 10 may verify whether the chip 20 is fluidic or not according to the preset data sending conditions and the data sending signal, the normal back pressure signal, and the transmit-receive mapping relation acquired from the chip 20.
It should be noted that, as an implementation manner, a UVM (Universal Verify Method, universal verification methodology) verification environment may be deployed on the chip test apparatus 10, and the implementation of the streaming verification method in this embodiment is performed based on the UVM.
The embodiment of the present invention further provides a block diagram of the chip test apparatus 10 in fig. 2, please refer to fig. 3, fig. 3 shows a block diagram of the chip test apparatus 10 provided in the embodiment of the present invention, the chip test apparatus 10 includes a processor 11, a memory 12 and a bus 13, and the processor 11 and the memory 12 are connected through the bus 13.
The processor 11 may be an integrated circuit chip with signal processing capabilities. The steps of the flow control verification method of the present embodiment may be completed by an integrated logic circuit of hardware in the processor 11 or an instruction in the form of software. The processor 11 may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU for short), a network processor (Network Processor, NP for short), and the like; but may also be a Digital Signal Processor (DSP), application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components.
The memory 12 is used to store a program, such as the flow control verification device 100 in this embodiment. The flow control verification device 100 includes at least one software functional module that may be stored in the memory 12 in the form of software or firmware (firmware) or cured in an Operating System (OS) of the chip test apparatus 10. After receiving the execution instruction, the processor 11 executes a program to implement the flow control verification method disclosed in the above embodiment.
Based on fig. 1 and 2, the present embodiment provides a flow control verification method, which is applied to the chip test device 10 in fig. 2 and the chip test device 10 in fig. 3, and is used for verifying the flow control of the chip in fig. 1 and 2, please refer to fig. 4, fig. 4 is a flowchart illustrating the flow control verification method provided in the present embodiment, and the method includes the following steps:
step S101, obtaining a flow control back pressure signal sent by a target receiving module in a plurality of receiving modules, wherein the flow control back pressure signal represents whether the target receiving module needs flow control or not.
In this embodiment, each receiving module is connected to its corresponding scheduler through a flow control signal line, so as to send a flow control back pressure signal to the scheduler, when the flow control back pressure signal is valid, it means that the receiving module needs to flow control, that is, needs to notify the sending module sending data to the receiving module that it does not continue sending data to the receiving module, and when the flow control back pressure signal is invalid, it means that the receiving module does not need to flow control, and the sending module sending data to the receiving module can continue sending data to the receiving module.
Step S102, a data transmission signal representing whether to transmit data sent by each transmission module and a receiving-transmitting mapping relation of each transmission module are obtained.
In this embodiment, when the data transmission signal is valid, the transmission module normally transmits data, and when the data transmission signal is invalid, the transmission module does not transmit data any more. The transmit-receive mapping relationship of each transmitting module characterizes the receiving module to which the transmitting module transmits the data, for example, the transmitting module a transmits the data to the transmitting module a', and the transmit-receive mapping relationship of the transmitting module a is: A-A'. It should be noted that a transmitting module may transmit data to one or more receiving modules.
And step S103, performing flow control verification on the target receiving module of the chip to be verified according to the flow control back pressure signal, the data transmission signal of each transmitting module and the receiving-transmitting mapping relation of each transmitting module.
In this embodiment, according to different flow control back pressure signals, data transmission signals of different transmission modules and a transmit-receive mapping relationship, flow control verification can be accurately performed, for example, if the flow control back pressure signal of a receiving module is valid, the data transmission signal of the transmission module transmitting data to the receiving module is still valid, which means that flow control is abnormal, and if the flow control back pressure signal of the receiving module becomes invalid, the data transmission signal of the transmission module to the receiving module is not recovered to be valid, which means that flow control is abnormal.
According to the method provided by the embodiment, the mapping relation between each sending module and the receiving module for receiving the data sent by each sending module is characterized by utilizing the receiving-sending mapping relation, whether the flow control back pressure signal of the target receiving module takes effect or not can be judged, and whether the data sending signal for sending the data to the target receiving module is consistent or not can be judged, so that when a plurality of sending channels exist in the chip to be verified at the same time, the accurate verification of whether the flow control is normal or not is realized.
In an alternative embodiment, when the flow control backpressure signal of the target receiving module is set to be valid, one way of flow control verification is:
if the flow control back pressure signal is set to be effective and the plurality of sending modules send data according to the respective receiving and sending mapping relation, determining a target sending module with the receiving and sending relation with the target receiving module from the plurality of sending modules according to the receiving and sending mapping relation of each sending module;
judging whether each sending module normally sends data or not according to the data sending signal of each sending module;
if the target sending module does not have a module for sending data normally and all other modules except the target sending module in the plurality of sending modules send data normally, judging that the flow control of the target receiving module is normal, otherwise, judging that the flow control of the target receiving module is abnormal.
In this embodiment, before the flow control back pressure signal is set to be valid, each sending module sends data according to its own transmit-receive mapping relationship, and when the flow control back pressure signal changes from invalid to valid, the chip test device can determine the sending module that sends data to the target receiving module according to the transmit-receive mapping relationship of each sending module. If the flow control is normal, the sending module sending the data to the target receiving module should not send the data any more. Further, other sending modules except the sending module for sending data to the target receiving module should not be affected, and normally send data, otherwise, the flow control has abnormality.
In order to determine whether the transmitting module normally transmits data, one determination method is as follows:
and for any module to be confirmed in the plurality of sending modules, if the data sending signal of the module to be confirmed is in a valid state, judging that the module to be confirmed normally sends data, otherwise, judging that the module to be confirmed does not normally send data.
In this embodiment, the module to be confirmed is any one of a plurality of transmission modules, which means that for each transmission module, it can be judged in this way whether it normally transmits data. The data transmission signal comprises two states of valid and invalid, when the data transmission signal is valid, the module to be confirmed is judged to normally transmit data, otherwise, the module to be confirmed is judged not to normally transmit data.
In this embodiment, after determining that the flow control of the target receiving module is abnormal, in order to further determine which sending module and the target receiving module are abnormal in flow control, the embodiment further provides a determination method:
judging a module which normally transmits data in the target transmitting module and a module which does not normally transmit data in other modules except the target transmitting module in the plurality of transmitting modules as an abnormal transmitting module;
and judging that the flow control between the target receiving module and the abnormal sending module is abnormal.
In this embodiment, the flow control exception includes both that flow control should be performed and that flow control is not in effect, and that flow control should not be performed but that flow control is incorrect. For example, the sending modules are A, B, C, D, the target receiving modules are a ', a and B, respectively, send data to a', when the flow control back pressure signal of a 'is set to be valid, if a still sends data to a', it means that the flow control between a and a 'is abnormal, and if C no longer sends data, it means that C is erroneously affected by the flow control back pressure signal of a', and the flow control between a and C is abnormal.
In an alternative embodiment, in order to avoid interference between each receiving module and influence the judgment result of the flow control verification of the target receiving module, in this embodiment, the target receiving module is randomly determined from a plurality of receiving modules, the target receiving module is one, and flow control back pressure signals of other modules except the target receiving module are all set to be free from flow control.
In an alternative embodiment, when the flow control back pressure signal of the target receiving module is set to be invalid, one way of flow control verification is:
if the flow control back pressure signal is set to be invalid, all other modules except the target sending module which has a receiving-transmitting mapping relation with the target receiving module in the plurality of sending modules are set to not send data, and the target sending module is set to send data, judging whether each sending module normally sends data according to the data sending signal of each sending module;
if the target sending module normally sends data and the modules for sending data do not exist in the other modules except the target sending module, judging that the flow control of the target receiving module is normal, otherwise, judging that the flow control of the target receiving module is abnormal.
In this embodiment, before the flow control back pressure signal is set to be invalid, the transmitting module that should transmit data to the target transmitting module does not transmit data to the target transmitting module, and in order to avoid interference, before the flow control back pressure signal is set to be invalid, all other modules except for the target transmitting module having a transmitting-receiving mapping relationship with the target receiving module are set to not transmit data. When the flow control back pressure signal is set from effective to ineffective, the sending module sending data to the target sending module should recover sending data, and if not, the flow control is abnormal. Further, the sending module other than the sending module sending data to the target sending module should not be affected, if the sending module other than the sending module sending data to the target sending module also recovers the sending data, this means that the sending module receives the influence of the flow control of the target sending module, and at this time, it is also determined that there is no abnormality in the flow control.
In this embodiment, whether the sending module normally sends data is described in the above process when the flow control back pressure signal of the target receiving module is set to be valid, which is not described here again.
In an alternative embodiment, in order to avoid interference between each receiving module and influence the judgment result of the flow control verification of the target receiving module, the target receiving module is randomly determined from a plurality of receiving modules, the target receiving module is one, and flow control back pressure information of other modules except the target receiving module is set to be in need of flow control.
In this embodiment, in order to ensure the comprehensiveness of the test, other test scenarios may be further supplemented, for example, the flow control back pressure signal of the target receiving module is always set to 1, and at this time, the message of the sending module sending data to the target receiving module should be blocked, if not, it indicates that the flow control is not effective, or that the data flow direction has a problem.
In this embodiment, in order to cover more test scenarios as possible, a random test may be performed in the regression test, for example, if data can be successfully sent by sampling in a test case, statistics is performed, and report is performed after the end of the regression test, because of randomness, all statistical points should have statistical data, and if not, a test case needs to be separately constructed to check whether the flow control is in error.
In order to perform the foregoing embodiments and the corresponding steps in each possible implementation manner, an implementation manner of the flow control verification apparatus 100 is given below, which is applied to an electronic device. Referring to fig. 5, fig. 5 is a block diagram of a flow control verification device according to an embodiment of the present invention, and it should be noted that the basic principle and the technical effects of the flow control verification device 100 according to the present embodiment are the same as those of the corresponding embodiment, and the description of the embodiment is omitted.
The flow control verification device 100 is applied to the chip test equipment 10 and comprises an acquisition module 110 and a verification module 120.
The obtaining module 110 is configured to obtain a flow control back pressure signal sent by a target receiving module in the multiple receiving modules, where the flow control back pressure signal characterizes whether the target receiving module needs a flow control signal;
the acquiring module 110 is further configured to acquire a data transmission signal representing whether to transmit data and a transmit-receive mapping relationship of each transmitting module, where the data transmission signal is sent by each transmitting module;
and the verification module 120 is configured to perform flow control verification on the target receiving module of the chip to be verified according to the flow control back pressure signal, the data transmission signal of each transmitting module, and the transmit-receive mapping relationship of each transmitting module.
In an alternative embodiment, the verification module 120 is specifically configured to:
if the flow control back pressure signal is set to be effective and the plurality of sending modules send data according to the respective receiving and sending mapping relation, determining a target sending module with the receiving and sending relation with the target receiving module from the plurality of sending modules according to the receiving and sending mapping relation of each sending module;
judging whether each sending module normally sends data or not according to the data sending signal of each sending module;
if the target sending module does not have a module for sending data normally and all other modules except the target sending module in the plurality of sending modules send data normally, judging that the flow control of the target receiving module is normal, otherwise, judging that the flow control of the target receiving module is abnormal.
In an alternative embodiment, the verification module 120 is specifically further configured to:
judging a module which normally transmits data in the target transmitting module and a module which does not normally transmit data in other modules except the target transmitting module in the plurality of transmitting modules as an abnormal transmitting module;
and judging that the flow control between the target receiving module and the abnormal sending module is abnormal.
In an alternative embodiment, the target receiving modules in the verification module 120 are randomly determined from a plurality of receiving modules, and the target receiving module is one, and the flow control back pressure signals of the other modules except the target receiving module are all set so that no flow control is required.
In an alternative embodiment, the verification module 120 is further configured to:
if the flow control back pressure signal is set to be invalid, all other modules except the target sending module which has a receiving-transmitting mapping relation with the target receiving module in the plurality of sending modules are set to not send data, and the target sending module is set to send data, judging whether each sending module normally sends data according to the data sending signal of each sending module;
if the target sending module normally sends data and the modules for sending data do not exist in the other modules except the target sending module, judging that the flow control of the target receiving module is normal, otherwise, judging that the flow control of the target receiving module is abnormal.
In an alternative embodiment, the target receiving modules in the verification module 120 are randomly determined from a plurality of receiving modules, and the target receiving module is one, and the flow control back pressure information of the other modules except the target receiving module is set to be in need of flow control.
In an alternative embodiment, the data transmission signal includes two states, namely an active state and an inactive state, and the verification module is specifically configured to, when determining whether each transmission module normally transmits data according to the data transmission signal of each transmission module:
and for any module to be confirmed in the plurality of sending modules, if the data sending signal of the module to be confirmed is in a valid state, judging that the module to be confirmed normally sends data, otherwise, judging that the module to be confirmed does not normally send data.
An embodiment of the present invention provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements a flow control verification method as in any of the preceding embodiments.
In summary, the embodiments of the present invention provide a method, an apparatus, a chip testing device, and a readable storage medium for flow control verification, where the method is applied to the chip testing device, where the chip testing device is electrically connected to a chip to be verified, and the chip to be verified includes a plurality of sending modules for sending data, a plurality of receiving modules for receiving data, and a register for configuring a sending-receiving mapping relationship of each sending module, where the sending-receiving mapping relationship of each sending module characterizes a mapping relationship between each sending module and the receiving module for receiving data sent by each sending module, and the method includes: acquiring a flow control back pressure signal sent by a target receiving module in a plurality of receiving modules, wherein the flow control back pressure signal represents whether the target receiving module needs flow control or not; acquiring a data transmission signal representing whether to transmit data or not sent by each transmission module and a receiving-transmitting mapping relation of each transmission module; and performing flow control verification on the target receiving module of the chip to be verified according to the flow control back pressure signal, the data transmission signal of each transmitting module and the receiving-transmitting mapping relation of each transmitting module. Compared with the prior art, the embodiment has at least the following advantages: (1) The mapping relation between each sending module and the receiving module for receiving the data sent by each sending module is characterized by utilizing the receiving-sending mapping relation, whether the flow control back pressure signal of the target receiving module takes effect or not and whether the data sending signal for sending the data to the target receiving module is consistent or not can be judged, so that when a plurality of sending channels exist in the chip to be verified at the same time, the accurate verification of whether the flow control is normal or not is realized, on one hand, the problems that the communication channel is erroneously back pressure, the bandwidth is influenced and even the chip is suspended and dead due to the flow control error are avoided, and on the other hand, the verification automation is realized and the verification efficiency is improved; (2) An effective verification method is provided for the internal flow control mechanism of the module which is difficult to verify, particularly for the situation that the multi-path flow control has a mapping relation, and the method is not limited to only checking the correctness of the message content and the like, so that the flow control verification is more accurate; (3) The randomness of flow control back pressure is increased, the problem that all ports are back-pressed together is avoided like the traditional concept, namely, the design is error-free, misjudgment and missed judgment in the prior art are avoided, and the verification is more comprehensive; (4) And a regression test is introduced, so that the test coverage condition is more comprehensive.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
Claims (10)
1. The utility model provides a flow control verification method which is characterized in that is applied to chip test equipment, chip test equipment and wait to verify the chip electricity and connect, wait to verify the chip and include a plurality of sending module that are used for sending data, a plurality of receiving module that are used for receiving data and the register that disposes the receiving and dispatching mapping relation of each sending module, the mapping relation between each sending module and the receiving module that is used for receiving each sending module to send data of the representation of receiving of each sending module, the method includes:
acquiring flow control back pressure signals sent by a target receiving module in a plurality of receiving modules, wherein the flow control back pressure signals represent whether the target receiving module needs flow control signals or not;
acquiring a data transmission signal representing whether to transmit data and a receiving-transmitting mapping relation of each transmission module, wherein the data transmission signal is sent by each transmission module;
and performing flow control verification on the target receiving module of the chip to be verified according to the flow control back pressure signal, the data sending signal of each sending module and the receiving-sending mapping relation of each sending module.
2. The method for flow control verification according to claim 1, wherein the step of performing flow control verification on the target receiving module of the chip to be verified according to the flow control back pressure signal, the data transmission signal of each transmitting module, and the transmit-receive mapping relationship of each transmitting module comprises:
if the flow control back pressure signal is set to be effective and the plurality of sending modules send data according to the respective receiving and sending mapping relation, determining a target sending module with the receiving and sending relation with the target receiving module from the plurality of sending modules according to the receiving and sending mapping relation of each sending module;
judging whether each sending module normally sends data or not according to the data sending signal of each sending module;
if the target sending module does not have a module for sending data normally, and all other modules except the target sending module in the multiple sending modules send data normally, judging that the flow control of the target receiving module is normal, otherwise, judging that the flow control of the target receiving module is abnormal.
3. The method of flow control verification according to claim 2, wherein after the step of determining that the flow control of the target receiving module is abnormal, comprising:
judging a module which normally transmits data in the target transmitting module and a module which does not normally transmit data in other modules except the target transmitting module in a plurality of transmitting modules as an abnormal transmitting module;
and judging that the flow control between the target receiving module and the abnormal sending module is abnormal.
4. The flow control verification method according to claim 2, wherein the target receiving module is randomly determined from a plurality of the receiving modules, and the target receiving module is one, and flow control back pressure signals of the remaining modules except the target receiving module are set so that no flow control is required.
5. The method for flow control verification according to claim 1, wherein the step of performing flow control verification on the target receiving module of the chip to be verified according to the flow control back pressure signal, the data transmission signal of each transmitting module, and the transmit-receive mapping relationship of each transmitting module comprises:
if the flow control back pressure signal is set to be invalid, all other modules except for a target sending module which has a receiving-transmitting mapping relation with the target receiving module in the plurality of sending modules are set to not send data, and the target sending module is set to send data, judging whether each sending module normally sends data according to the data sending signal of each sending module;
and if the target sending module normally sends data and the modules for sending data do not exist in the other modules except the target sending module, judging that the flow control of the target receiving module is normal, otherwise, judging that the flow control of the target receiving module is abnormal.
6. The fluid control verification method according to claim 5, wherein the target receiving module is randomly determined from a plurality of the receiving modules, and the target receiving module is one, and fluid control back pressure information of the remaining modules except the target receiving module is set to require fluid control.
7. The method for fluid control verification according to claim 2 or 5, wherein the data transmission signal includes two states of valid and invalid, and the step of judging whether each of the transmission modules normally transmits data according to the data transmission signal of each of the transmission modules includes:
and for any module to be confirmed in the plurality of sending modules, if the data sending signal of the module to be confirmed is in a valid state, judging that the module to be confirmed normally sends data, otherwise, judging that the module to be confirmed does not normally send data.
8. The utility model provides a flow control verifying device, its characterized in that is applied to chip test equipment, chip test equipment and wait to verify the chip electricity and connect, wait to verify the chip and include a plurality of sending modules that are used for sending data, a plurality of receiving module that are used for receiving data and the register of configuration each sending module's receiving-transmitting mapping relation, each sending module's receiving-transmitting mapping relation characteristic each sending module and the receiving module that is used for receiving each sending module to send the data between the mapping relation, the device includes:
the acquisition module is used for acquiring flow control back pressure signals sent by a target receiving module in the plurality of receiving modules, wherein the flow control back pressure signals represent whether the target receiving module needs flow control signals or not;
the acquisition module is further configured to acquire a data transmission signal representing whether to transmit data sent by each transmission module and a transmit-receive mapping relationship of each transmission module;
and the verification module is used for carrying out flow control verification on the target receiving module of the chip to be verified according to the flow control back pressure signal, the data transmission signal of each transmission module and the receiving-transmitting mapping relation of each transmission module.
9. A chip testing apparatus comprising a processor and a memory, the memory for storing a program, the processor for implementing the flow control verification method of any one of claims 1-7 when the program is executed.
10. A computer readable storage medium, having stored thereon a computer program which, when executed by a processor, implements the flow control verification method according to any one of claims 1-7.
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