CN117294392A

CN117294392A - Forward error correction method, forward error correction device, electronic device and storage medium

Info

Publication number: CN117294392A
Application number: CN202311244792.2A
Authority: CN
Inventors: 周鹏
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2023-09-25
Filing date: 2023-09-25
Publication date: 2023-12-26
Anticipated expiration: 2043-09-25
Also published as: CN117294392B

Abstract

At least one embodiment of the present disclosure provides a forward error correction method, a forward error correction apparatus, an electronic apparatus, and a storage medium. The forward error correction method comprises the following steps: receiving a data packet transmitted on a system bus, wherein the data packet comprises n sub-data packets, n is a positive integer and is more than or equal to 2; and transmitting a subpacket to one of the n forward error correction channels in response to receiving one of the n subpackets, wherein the n subpackets correspond one-to-one with the n forward error correction channels; and performing a forward error correction operation on a subpacket in a forward error correction channel. The forward error correction method can support that a part of the received data packet can be sent out to execute forward error correction operation, thereby improving the data transmission efficiency.

Description

Forward error correction method, forward error correction device, electronic device and storage medium

Technical Field

Embodiments of the present disclosure relate to a forward error correction method, a forward error correction apparatus, an electronic apparatus, and a storage medium.

Background

Forward error correction (Forward Error Correction, FEC) is an error control method, which is a technique that, at the transmitting end, encodes a signal in advance according to a certain algorithm before the signal is sent to a channel (i.e., a signal transmission channel), adds a redundancy code with the characteristics of the signal itself, and, at the receiving end, decodes the received signal according to a corresponding algorithm, thereby finding out an error code generated during transmission and correcting it.

Disclosure of Invention

At least one embodiment of the present disclosure provides a forward error correction method, including: receiving a data packet transmitted on a system bus, wherein the data packet comprises n sub-data packets, n is a positive integer and is more than or equal to 2; and transmitting a subpacket to one of the n forward error correction channels in response to receiving one of the n subpackets, wherein the n subpackets correspond one-to-one with the n forward error correction channels; and performing a forward error correction operation on a subpacket in a forward error correction channel.

At least one embodiment of the present disclosure provides a forward error correction apparatus, including a transmission unit and n forward error correction channels, n is a positive integer and n is greater than or equal to 2, where the transmission unit is configured to: receiving a data packet transmitted on a system bus, wherein the data packet comprises n sub-data packets; and transmitting a subpacket to one of the n forward error correction channels in response to receiving one of the n subpackets, wherein the n subpackets correspond one-to-one with the n forward error correction channels; and one forward error correction channel is configured to: forward error correction is performed on a sub-packet.

At least one embodiment of the present disclosure provides an electronic device, including: one or more processors; a memory including one or more computer program modules; wherein the one or more computer program modules are stored in the memory and configured to be executed by the one or more processors to implement the forward error correction method as described above.

At least one embodiment of the present disclosure provides a non-transitory readable storage medium having stored thereon computer-executable instructions, wherein the computer-executable instructions, when executed by a processor, implement the forward error correction method as described above.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments of the present disclosure will be briefly described below. It is apparent that the figures in the following description relate only to some embodiments of the present disclosure and are not limiting of the present disclosure.

Fig. 1 shows a schematic diagram of an exemplary non-return-to-zero (NRZ) and pulse amplitude modulation 4 (PAM 4) eye diagram;

FIG. 2 shows a schematic diagram of an exemplary three-wire interleaved data structure approach;

fig. 3 shows a schematic diagram of an exemplary FEC structure;

FIG. 4 illustrates a flow chart of a forward error correction method in accordance with at least one embodiment of the present disclosure;

FIG. 5 illustrates a schematic diagram of a forward error correction device in accordance with at least one embodiment of the present disclosure;

fig. 6 is a schematic diagram of an FEC structure applicable to a system bus for Peripheral Component Interconnect Express (PCIE) 6.0 in accordance with at least one embodiment of the present disclosure;

FIG. 7 illustrates a schematic diagram of a two-wire interleaved data structure in accordance with at least one embodiment of the present disclosure;

FIG. 8 illustrates a schematic diagram of an electronic device in accordance with at least one embodiment of the present disclosure; and

fig. 9 illustrates a schematic diagram of a non-transitory readable storage medium according to at least one embodiment of the present disclosure.

Detailed Description

Reference will now be made in detail to the specific embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. While the disclosure will be described in conjunction with the specific embodiments, it will be understood that it is not intended to limit the disclosure to the described embodiments. On the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the disclosure as defined by the appended claims. It should be noted that the method operations described herein may be implemented by any functional block or arrangement of functions, and that any functional block or arrangement of functions may be implemented as a physical entity or a logical entity, or a combination of both.

In order that those skilled in the art will better understand the present disclosure, the present disclosure will be described in further detail below with reference to the accompanying drawings and detailed description.

Note that the examples to be presented below are only specific examples and are not intended to limit the embodiments of the present disclosure to the particular shapes, hardware, connection relationships, operations, values, conditions, data, sequences, etc., shown and described. Those skilled in the art can, upon reading the present specification, utilize the concepts of the present disclosure to construct additional embodiments not described in the present specification.

The terms used in the present disclosure are those general terms that are currently widely used in the art in view of the functions of the present disclosure, but may vary according to the intention, precedent, or new technology in the art of the person of ordinary skill in the art. Furthermore, specific terms may be selected by the applicant, and in this case, their detailed meanings will be described in the detailed description of the present disclosure. Accordingly, the terms used in the specification should not be construed as simple names, but rather based on the meanings of the terms and the general description of the present disclosure.

A flowchart is used in this disclosure to describe the operations performed by a system according to embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in order precisely. Rather, the various steps may be processed in reverse order or simultaneously, as desired. Also, other operations may be added to or removed from these processes.

The abbreviations and related terms involved in the present application are first defined and explained.

Cyclic redundancy check (Cyclic Redundancy Check, CRC): a channel coding technique for generating short fixed bit check code according to network data packet or computer file is mainly used for detecting or checking the error possibly occurring after data transmission or storage. It uses the principle of division and remainder to make error detection.

Forward error correction (Forward Error Correction, FEC): an error control mode is a technology of adopting data coding, at the transmitting end, it carries out coding processing according to a certain algorithm in advance before the signal is sent into the channel, adds in redundant code with the characteristics of the signal itself, and at the receiving end, decodes the received signal according to a corresponding algorithm, thereby finding out the error code generated in the transmission process and correcting it.

Error check correction (Error Check Correction, ECC): a technique for enabling 'error checking and correction' to improve the stability and increase the reliability of computer operation.

Peripheral component interconnect express (peripheral component interconnect express, PCIE): a high speed serial computer expansion bus standard.

RS (Reed-Solomon) coding: also known as Reed-solomon codes or Reed-solomon codes, are a type of forward error correction channel coding that is effective for correcting polynomials generated from oversampled data. The RS code is a special non-binary BCH code with very strong error correction capability. For an optional positive integer S a corresponding q-ary BCH code of code length n=qs-1 can be constructed, with q being the power of some prime number. When s=1, q>The q-ary BCH code with code length n=q-1 established at 2 is called RS code. When q=2 ^m (m>1) Binary RS codes, whose symbol symbols are taken from F (2 m), can be used to correct burst errors, which are the most common RS codes.

The ECC Word (ECC Word), the object data for performing an ECC operation, is embodied in the form of data bits+check information in, for example, a memory architecture supporting ECC.

It is to be understood that the terminology defined above is merely exemplary of the specific application scenario in order to better understand the present application, and the present disclosure is not limited thereto.

The system bus provides a standardized interface, so that each component can work in coordination with each other, and can perform operations such as data reading and writing, command transmission and the like according to the needs. The development of system buses presents new opportunities and challenges. At present, FEC technology is widely applied to a system bus or other aspects, and with the development of technology, FEC technology has the disadvantages of larger delay and insufficient error correction capability.

For example, there are critical variations in the technology of the system bus. These variations include, for example: changes in pulse amplitude modulation (e.g., switching from non-return-to-zero (NRZ) to pulse amplitude modulation 4 (PAM 4) signals, resulting in increased sensitivity to noise); changes in steering flow control units (flits) (e.g., steering flow control units (flits) result in changes in controller behavior and performance, the need for tight integration between PHY and controller), and planning for interoperability and testing. Taking the PCIE6.0 bus standard as an example, three main variations of the PCIE5.0 bus standard are as follows: doubling the data rate from 32GT/s to 64GT/s; the coding format is converted from NRZ coding to PAM4 coding, thereby bringing about error correction effect; the transport size ranges from a variable-size Transaction Layer Packet (TLP) to a fixed size Flit (256 bytes (B)).

In addition, the system bus needs to read out the data packet corresponding to the diversion flow control unit (Flit) at a time using FEC, and then perform FEC operation. For example, the FEC used in PCIE6.0 can read 256B data (512 bits are read out according to a protocol cycle, which requires 4 cycles), and then use a three-wire interleaving method to divide into three FEC codes. .

Exemplary aspects of employing PCIE 6.0 and its FEC techniques described above are described below with respect to fig. 1-3 as an example. However, it will be appreciated that the system buses and their FEC techniques referred to in connection with fig. 1-3 are merely exemplary, and that the relevant features may be mapped to other existing or future-occurring system buses and their FEC techniques.

Currently, PCIE 6.0 employs PAM4 modulated signals. With PAM4, the data transmission per clock cycle can be up to 2 bits, not just single bit data transmission. PAM4 takes four different level classes, 2 digits can be expressed per clock cycle, i.e. from 00, 01, 10 to 11. This means that within the same voltage fluctuation range and within the same clock period.

Fig. 1 shows a schematic diagram of an exemplary eye diagram of NRZ and PAM 4. Referring to fig. 1, the voltage level of PAM4 is two times higher than PAM2, i.e., the black region "eye" in the eye pattern is more and smaller, thus resulting in a lower voltage margin and higher bit error rate, making ensuring signal integrity in the device a very critical challenge.

To reduce the impact of bit error rate and improve information integrity, an exemplary FEC technique uses three-wire interleaving. The received data packet (i.e., 256B data corresponding to Flit for PCIE 6.0) may be transmitted to three ECC decoders using a three-wire interlace (see fig. 3). Fig. 2 shows a schematic diagram of an exemplary three-wire interleaved data structure approach.

Referring to FIG. 2, wherein B0-B235 and DLP0-DLP5 (DLP are data link layer packets), together 242B is valid data, CRC0-CRC7 is CRC data of 8B, and ECC0-ECC5 is FEC encoded data of 6B. Total 1flit 256b data. In the three-wire interleaved path (Lane):

byte 0 of n Flit maps to a first set of ECC words (ECC words), byte offset 0;

byte 1 of n Flit maps to a second set of ECC words, with a byte offset of 0;

byte 2 of n Flit maps to a third set of ECC words, with a byte offset of 0;

byte 3 of n Flit maps to a first set of ECC words, byte offset 1;

byte 4 of n Flit maps to a second set of ECC words, byte offset 1;

n……

bytes 248 of n Flit map to a third set of ECC words, byte offset 82;

bytes 249 of the n Flit map to the first set of ECC words, byte offset 83.

n second set of ECC words, byte offset 83 is 00h.

n third set of ECC words, byte offset 83 is 00h.

Then, the ECC bytes are allocated as follows:

bytes 250 and 253 of n Flit map to a second set of ECC words, with byte offsets of 84 and 85, respectively;

bytes 251 and 254 of n Flit map to a third set of ECC words, with byte offsets of 84 and 85, respectively; and

bytes 252 and 255 of n Flit map to the first set of ECC words with byte offsets of 84 and 85, respectively.

Namely:

B0/B3/B6/B9/… … are the same set of ECC words, e.g., referred to as ECC0 words;

B1/B4/B7/B10/… … are the same set of ECC words, e.g., referred to as ECC1 words; wherein the 00 data of 1B are complemented;

B2/B5/B8/B11/… … are the same set of ECC words, e.g., referred to as ECC2 words; wherein the 00 data of 1B are complemented.

In FIG. 2, bytes having the same gray scale (e.g., B0/B3/B6/B9/… … has the same gray scale as described above, B1/B4/B7/B10/… … has the same gray scale as described above, and B2/B5/B8/B11/… … has the same gray scale as described above) are mapped to the same group and thus organized into the same ECC word.

As described with reference to fig. 3, the ECC0 word, the ECC1 word, and the ECC2 word are subjected to ECC operations by three ECC decoders, respectively.

Fig. 3 shows a schematic diagram of an exemplary FEC structure. The FEC structure described with reference to fig. 3 may use the three-wire interleaved FEC technique described with reference to fig. 2.

Referring to fig. 3, the fec structure includes a transmission unit 310, three ECC decoders 320-340, and a CRC check unit 380.

At the receiving end, the transmission unit 310 needs to completely receive 256B data, and 4 cycles are required to receive 256B data according to the bit width 512B, so that the 256B data is ready.

Using the three-wire interleaving scheme shown in FIG. 2, the transmission unit 310 sends 256B data to three ECC decoders 320-340, respectively, where 256B is split into 86B/85B/85B. The number of bytes of the corresponding ECC words of the three ECC decoders 320-340 is 86B, so the last two ECC units 330 and 340 need to be complemented with 0's of 1B to perform ECC operations, and each ECC word 86B can correct 1B.

After an ECC operation by the three ECC decoders 320-340, the corrected 242B data is sent out and 242B data+8B CRC data (250B data total) is sent to the CRC check unit 380 for integrity check. In the CRC check unit 380, the 242B data will perform CRC calculation once again to obtain 8B CRC data, and then the 8B CRC data obtained will be verified with the 8B CRC data output in the ECC unit, and if they are consistent, it indicates that the data is complete.

Thus, the exemplary FEC structure can only transmit 256B data to the ECC decoder for ECC operations after it has received the 256B data, and can correct 3B data in the 256B data and ensure data integrity by the CRC. 256B data includes 242 valid data +8B crc +6B FEC. The data transmission rate was 242/256= 94.53%.

FEC techniques based on, for example, a system bus, have a need for low latency and/or high error correction capability.

At least one embodiment of the present invention provides a forward error correction method, a forward error correction apparatus, an electronic apparatus, and a non-transitory readable storage medium for improving data transmission efficiency and/or improving error correction capability.

Fig. 4 illustrates a flow chart of a forward error correction method 400 in accordance with at least one embodiment of the present disclosure. The forward error correction method 400 described with reference to fig. 4, and additional aspects thereof, may be implemented in the forward error correction device 500, the electronic device, the hardware structure, the software structure, or both the hardware structure and the software structure described below with reference to fig. 5.

Referring to fig. 4, the forward error correction method 400 includes steps S410 to S430.

In step S410, a data packet transmitted on a system bus is received, wherein the data packet includes n sub-data packets, n is a positive integer and n is not less than 2.

The system bus may be an information transmission line between the components of the computing device. For example, system buses include, but are not limited to, ISA bus, EISA bus, VESA bus, PCI bus, compact PCI, PCIE bus, and the like.

For example, the data packet may correspond to a flow control unit of a system bus. Different system buses may correspond to different flow control units. The flow control unit may be the smallest unit of system bus operation. For example, the flow control unit of the PCIE 6.0 bus is 256B, and thus the packet is 256B.

The data packet may be divided into n sub-packets, each of which may include data bits + check information, and may be organized into ECC words for an ECC decoder to perform ECC operations.

In step S420, in response to receiving one of the n sub-packets, one sub-packet is transmitted to one of the n forward error correction channels, where the n sub-packets are in one-to-one correspondence with the n forward error correction channels. For example, the forward error correction channel may perform forward error correction operations on data incoming thereto.

In step S430, a forward error correction operation is performed on a sub-packet in a forward error correction channel. In some embodiments, the forward error correction operations include error check correction decoding and cyclic redundancy check operations.

In some embodiments, the sub-data includes data information and parity information for performing forward error correction operations. For example, the sub data packet may include data information and check information for correcting, for example, at least 1 bit of data in the data information.

Here, the sub-packets may perform forward error correction operations in respective forward error correction channels, and thus may facilitate the respective sub-packets to perform forward error correction operations independently and in parallel.

As described above, the forward error correction method according to at least one embodiment of the present disclosure may support that a portion of a received data packet may be issued to perform a forward error correction operation, thereby improving data transmission efficiency.

Some exemplary additional aspects of forward error correction methods in accordance with at least one embodiment of the present disclosure are described below.

For example, according to a forward error correction method of at least one embodiment of the present disclosure, performing a forward error correction operation on a subpacket in a forward error correction channel includes: performing error checking and correcting operation on one sub data packet, and obtaining the result of the error checking and correcting operation; and performing a cyclic redundancy check (crc) check on the result of the error checking and correcting operation.

It should be noted that, in this context, the forward error correction method according to at least one embodiment of the present disclosure describes decoding aspects of the FEC technique, and may be applied to a receiving end supporting the FEC technique. It will be appreciated that decoding and encoding are reciprocal processes and in an additional aspect, the forward error correction method according to at least one embodiment of the present disclosure describes that the decoding aspect of the FEC technique can be extended to the encoding aspect and can be applied to a transmitting end supporting the FEC technique. Of course, the sender may also be implemented in other manners to obtain the data packet described in the context, which is not limited in this disclosure.

The crc check ensures the integrity of the data, and the data that it needs to receive is completely correct, and the error checking and correcting operation has not only an error detecting function (for example, in terms of error detecting, not weaker than the crc check), but also an error correcting function, so that the correctness of the data is ensured. As such, a forward error correction method according to at least one embodiment of the present disclosure may ensure data integrity via an error checking correction operation+cyclic redundancy check code check.

For example, according to a forward error correction method of at least one embodiment of the present disclosure, transmitting one sub-packet to one of n forward error correction channels includes: transmitting a sub-data packet to m error checking and correcting decoders of a forward error correction channel by using m-line interleaving, so that the byte number of the sub-data packet is equal to the sum of the byte numbers of the error checking and correcting words corresponding to the m error checking and correcting decoders, wherein m is a positive integer and m is more than or equal to 1.

As such, the forward error correction method according to at least one embodiment of the present disclosure does not require padding invalid data, improving the operating efficiency of error checking and correcting operations and/or cyclic redundancy check (crc) checking.

For example, it may be implemented such that the number of bytes of an ECC word (i.e., the number of bytes of an ECC structure of an error check correction decoder) corresponding to each error check correction decoder (i.e., an ECC decoder) is equal, and the number of bytes of a sub-packet is equal to an integer multiple of the number of bytes of an error check correction word corresponding to one error check correction decoder. Illustratively, for a sub-packet of 128B, each error check correction decoder corresponds to a number of ECC bytes of 64B, and 128B may be interleaved to two error check correction decoders by a two-line interleaving. For another example, for a sub-packet of 128B, each error check correction decoder corresponds to 32B in number of ECC bytes, and 128B may be interleaved to four error check correction decoders by four-wire interleaving. Of course, the examples of the present disclosure are not limited thereto, and the number of ECC word bytes corresponding to each error check correction decoder need not be made equal. In addition, the sub-packets may be organized according to the number of ECC bytes corresponding to the error check correction decoder, or an appropriate error check correction decoder may be selected according to the sub-packets.

For example, according to a forward error correction method of at least one embodiment of the present disclosure, m=2, m error check correction decoders include a first error check correction decoder and a second error check correction decoder, the size of one sub packet can be divided by 2, and one sub packet is transmitted to m error check correction decoders using m-line interleaving, including: one sub-packet is transmitted to a first error check correction decoder and a second error check correction decoder using a two-wire interlace.

As such, a forward error correction method in accordance with at least one embodiment of the present disclosure may use two-wire interleaving, thereby improving the operating efficiency of error checking correction operations and/or cyclic redundancy check code checking without padding invalid data.

For example, a forward error correction method according to at least one embodiment of the present disclosure, which transmits one sub-packet to a first error check correction decoder and a second error check correction decoder using two-wire interleaving, includes: mapping odd bytes of a sub-packet to a first error check correction word; and mapping even bytes of a sub-packet to a second error check correction word.

During data transmission, the probability of an error in a byte being adjacent to it increases when it is due to factors such as crosstalk or other factors. For example, referring to FIG. 7 below, byte 0 is mapped to an ECC0 word, and when byte 0 is in error, the probability of either byte 1 or 16 being in error increases, however, bytes 1 and 16 are mapped to an ECC0 word. Considering that the error correction capability of each ECC decoder is limited, for example, the error correction capability of each ECC decoder is 1 byte, and the error of byte 1 is generated, the error-generated byte 0 and the error-generated byte 1 can be mapped into different ECC words by means of two-line interleaving, so that the corresponding ECC decoder can respectively correct the error-generated byte 0 and the error-generated byte 1, in contrast to interleaving the error-generated byte 0 and the error-generated byte 1 into one ECC word, the error correction capability of the ECC decoder is exceeded by the number of bytes in error.

As such, the forward error correction method according to at least one embodiment of the present disclosure facilitates error correction of erroneous bytes by an ECC decoder by way of an odd-even byte alternate mapping such that erroneous bytes may be distributed among different ECC words.

For example, according to the forward error correction method of at least one embodiment of the present disclosure, the system bus conforms to the peripheral component interconnect express protocol, n=2.

As such, the forward error correction method according to at least one embodiment of the present disclosure may improve data transmission efficiency through two forward error correction channels at a high speed of peripheral component interconnection.

For example, according to a forward error correction method of at least one embodiment of the present disclosure, a system bus conforms to a peripheral component interconnect express protocol, n=2, and the number of bytes of one sub data is 128B, and one sub data packet is transmitted to a first error check correction decoder and a second error check correction decoder using two-wire interleaving, comprising:

n maps byte 0 of a sub-packet to a first set of error check correction words, byte offset 0;

n maps byte 1 of a sub-packet to a second set of error check correction words, the byte offset being 0;

n maps byte 2 of a sub-packet to a first set of error check correction words, byte offset 1;

n maps byte 3 of a sub-packet to a second set of error check correction words, byte offset 1;

n maps byte 4 of a sub-packet to a first set of error check correction words, byte offset 2;

n maps byte 5 of a sub-packet to a second set of error check correction words, byte offset 2;

n……

n maps bytes 122 of a sub-packet to a first set of error check correction words, byte offset 61;

n maps bytes 123 of a sub-packet to a second set of error check correction words, byte offset 61;

n maps bytes 124 and 126 of a sub-packet to a first set of error check correction words, byte offset 62;

n maps bytes 125 and 127 of a sub-packet to a second set of error check correction words, byte offset 63.

Thus, a forward error correction method according to at least one embodiment of the present disclosure organizes sub-packets into first and second ECC words that are transmitted to a first ECC decoder (i.e., a first error check correction decoder) and a second ECC decoder (i.e., a second error check correction decoder), respectively, by way of an odd-even byte alternate mapping.

As such, the forward error correction method according to at least one embodiment of the present disclosure may enable transmission of sub-packets to an ECC decoder through a specific 128B data transmission two-line interleaving manner at a high speed of peripheral component interconnect, and improve data transmission efficiency via two forward error correction channels. It will be appreciated that n=2 is not necessary in this embodiment, for example n may also be other positive integers greater than 2.

For example, in accordance with a forward error correction method of at least one embodiment of the present disclosure, the peripheral component interconnect express protocol is a peripheral component interconnect express 6.0 version or a version compatible with the peripheral component interconnect express 6.0 version.

As such, the forward error correction method according to at least one embodiment of the present disclosure may be applied to, for example, peripheral component interconnect high speed 6.0. For example, in the case of peripheral component interconnect high speed 6.0, the sub-packet is 128B, and the ECC operation can be performed by 2 ECC decoders corresponding to an ECC word of 64B.

For example, according to a forward error correction method of at least one embodiment of the present disclosure, the number of bytes of one sub data includes 122B of valid data, 2B of Cyclic Redundancy Check (CRC) data, and 4B of Forward Error Correction (FEC) data, the number of bytes of corresponding error check correction words of the first error check correction decoder and the second error check correction decoder is 64B, and an error check correction operation is performed on one sub data packet, a result of the error check correction operation is obtained, including: performing error check correction operations on the first set of error check correction words and the second set of error check correction words by the first error check correction decoder and the second error check correction decoder, respectively, to obtain 122B error check corrected valid data (e.g., dlp+tlp) and 2B error check corrected cyclic redundancy check code (CRC) data.

As such, a forward error correction method in accordance with at least one embodiment of the present disclosure may employ two ECC decoders having an ECC structure of 64B to process 128B sub-packets and cause the ECC decoders to correct, for example, at least one error through a specific data input.

For example, according to a forward error correction method of at least one embodiment of the present disclosure, performing cyclic redundancy check (crc) check on a result of an error check correction operation includes: performing Cyclic Redundancy Check (CRC) code checking on the effective data after error checking and correcting of the 122B by a single CRC code checking unit to obtain cyclic redundancy check code data after the CRC code checking of the 2B; comparing the cyclic redundancy check code data after the cyclic redundancy check code of 2B is checked with the cyclic redundancy check code (CRC) data after the error check and correction of 2B; and outputting a first value to indicate that one sub-packet has integrity in response to the cyclic redundancy check code data of 2B being inconsistent with the error check corrected cyclic redundancy check code (CRC) data of 2B; or outputting a second value to indicate that one sub-packet has no integrity in response to the cyclic redundancy check code (CRC) data after the cyclic redundancy check code check of 2B being identical to the cyclic redundancy check code (CRC) data after the error check correction of 2B.

In this manner, the forward error correction method according to at least one embodiment of the present disclosure may perform a CRC check operation using a single CRC check unit, guaranteeing the integrity of data.

For example, according to a forward error correction method of at least one embodiment of the present disclosure, performing, by a first and a second error check correction decoder, an error check correction operation on a first and a second set of error check correction words, respectively, includes: performing error check correction operations on the first set of error check correction words and the second set of error check correction words, respectively, by the first error check correction decoder and the second error check correction decoder using a reed-solomon code algorithm.

As such, a forward error correction method in accordance with at least one embodiment of the present disclosure may employ an RS algorithm to enable a single ECC decoder to enable at least data correction of, for example, at least 1 byte. However, the embodiment is not limited thereto, and data error correction of, for example, at least 1 byte may be implemented by other algorithms, and accordingly, the configuration of input data of the ECC decoder may be changed.

For example, according to the forward error correction method of at least one embodiment of the present disclosure, the number of bytes of n sub-packets is equal, and the structures of n forward error correction channels are identical.

In this way, the forward error correction method according to at least one embodiment of the present disclosure may make the corresponding forward error correction structure simple and easy to manufacture.

Corresponding to the forward error correction method 400 according to at least one embodiment of the present disclosure, at least one embodiment of the present disclosure also provides a forward error correction apparatus.

Fig. 5 illustrates a schematic diagram of a forward error correction device 500 in accordance with at least one embodiment of the present disclosure.

Referring to FIG. 5, the forward error correction apparatus 500 includes a transmission unit 510 and n forward error correction channels (e.g., first to nth forward error correction channels 502 to 504), where n is a positive integer and n+.2.

For example, the transmission unit 510 is configured to: receiving a data packet transmitted on a system bus, wherein the data packet comprises n sub-data packets; and transmitting one sub-packet to one of the n forward error correction channels in response to receiving one of the n sub-packets, wherein the n sub-packets are in one-to-one correspondence with the n forward error correction channels.

For example, referring to fig. 5, a packet corresponding to a flow control unit (Flit) may be divided into first through nth sub-packets, each of which may have a corresponding forward error correction channel.

A forward error correction channel is configured to perform forward error correction operations on a subpacket.

For example, referring to fig. 5, a first forward error correction channel 502 may perform a forward error correction operation on a first subpacket therein, and an nth forward error correction channel 504 may perform a forward error correction operation on an nth subpacket therein.

As described above, the forward error correction apparatus according to at least one embodiment of the present disclosure may support that a portion of a received data packet may be issued to perform a forward error correction operation, thereby improving data transmission efficiency.

Some exemplary additional aspects of forward error correction apparatus in accordance with at least one embodiment of the present disclosure are described below.

For example, according to a forward error correction apparatus of at least one embodiment of the present disclosure, one forward error correction channel includes an error check correction decoder group configured to perform an error check correction operation on one sub-packet, and a cyclic redundancy check unit group, to obtain a result of the error check correction operation; and the cyclic redundancy check code check unit group is configured to perform cyclic redundancy check code check on a result of the error check correction operation. The set of error checking correction decoders and the set of cyclic redundancy check code check units may each include one or more error checking correction decoders and cyclic redundancy check code check units.

For example, in accordance with the forward error correction apparatus of at least one embodiment of the present disclosure, the error check correction decoder group includes m error check correction decoders, m is a positive integer and m+.1, the transmission unit is further configured to: and transmitting one sub-data packet to m error check correction decoders by using m-line interleaving, so that the byte number of one sub-data packet is equal to the sum of the byte numbers of the error check correction words corresponding to the m error check correction decoders.

For example, in accordance with the forward error correction apparatus of at least one embodiment of the present disclosure, m=2, the m error check correction decoders include a first error check correction decoder and a second error check correction decoder, the size of one sub-packet is divisible by 2, and the transmission unit is further configured to: one sub-packet is transmitted to a first error check correction decoder and a second error check correction decoder using a two-wire interlace.

For example, in accordance with the forward error correction device of at least one embodiment of the present disclosure, the transmission unit is further configured to:

mapping odd bytes of a sub-packet to a first error check correction word; and

the even bytes of a sub-packet are mapped to a second error check correction word.

For example, in accordance with the forward error correction device of at least one embodiment of the present disclosure, the system bus conforms to a peripheral component interconnect express protocol, n=2, and the number of bytes of one sub-data is 128B, the transmission unit is further configured to:

n……

For example, a peripheral component interconnect express protocol is a peripheral component interconnect express 6.0 version or a version compatible with a peripheral component interconnect express 6.0 version in accordance with a forward error correction device of at least one embodiment of the present disclosure.

For example, according to the forward error correction apparatus of at least one embodiment of the present disclosure, the byte count of one sub data includes the valid data of 122B, the cyclic redundancy check code data of 2B, and the forward error correction data of 4B, the byte count of the corresponding error check correction words of the first error check correction decoder and the second error check correction decoder is 64B, and the first error check correction decoder and the second error check correction decoder are configured to: and performing error checking and correcting operations on the first group of error checking and correcting words and the second group of error checking and correcting words respectively to obtain 122B effective data after error checking and correcting and 2B cyclic redundancy check code data after error checking and correcting.

For example, in accordance with a forward error correction apparatus of at least one embodiment of the present disclosure, a cyclic redundancy check code check unit group includes a single cyclic redundancy check code check unit configured to: performing Cyclic Redundancy Check (CRC) code checking on the effective data after error checking and correcting of 122B to obtain cyclic redundancy check code data after CRC code checking of 2B; comparing the cyclic redundancy check code data after the cyclic redundancy check code of 2B is checked with the cyclic redundancy check code data after the error check and correction of 2B; and outputting a first value to indicate that one sub-packet has integrity in response to the crc data of 2B being inconsistent with the crc data of 2B after error checking and correction; or outputting a second value to indicate that one sub-packet has no integrity in response to the cyclic redundancy check code (CRC) data after the cyclic redundancy check code check of 2B being identical to the cyclic redundancy check code (CRC) data after the error check correction of 2B.

For example, a forward error correction device according to at least one embodiment of the present disclosure, a first error check correction decoder and a second error check correction decoder are configured to: performing error check correction operations on the first set of error check correction words and the second set of error check correction words, respectively, using a reed-solomon code algorithm.

For example, according to the forward error correction apparatus of at least one embodiment of the present disclosure, the number of bytes of n sub-packets is equal, and the structures of n forward error correction channels are the same.

The additional aspects of the forward error correction apparatus 500 according to at least one embodiment of the present disclosure may correspond to the additional aspects of the forward error correction method 400 according to at least one embodiment of the present disclosure, and thus technical effects of the additional aspects of the forward error correction method 400 according to at least one embodiment of the present disclosure may also be mapped to the additional aspects of the forward error correction apparatus 500 according to at least one embodiment of the present disclosure, which will not be described again herein.

In some embodiments, forward error correction apparatus 500 and additional aspects thereof in accordance with at least one embodiment of the present disclosure may be embodied as or included in a memory controller, such as a memory. As such, forward error correction apparatus 500 and additional aspects thereof in accordance with at least one embodiment of the present disclosure may be applied in a memory or memory system.

One or more exemplary aspects described above in connection with fig. 4 and 5 are described below in connection with example application scenarios. It will be appreciated that the example application scenarios described below are merely examples and are not intended to be limiting, and that one or more aspects described above in connection with fig. 4 and 5 are intended to be implemented in a particular application scenario, and that aspects described below in connection with the example application scenarios may be combined with one or more aspects described above in connection with fig. 4 and 5.

An example application scenario involves a schematic diagram of the FEC structure as described in fig. 6 as applicable to the system bus PCIE 6.0 and the two-wire interleaved data structure as shown in fig. 7.

Fig. 6 is a schematic diagram of an FEC structure applicable to a system bus PCIE 6.0 according to at least one embodiment of the present disclosure.

Referring to fig. 6, the fec structure includes a transmission unit 610, ecc decoders 620-650, and CRC check units 680 and 690. The transmission unit 610 may be the same as or similar to the transmission unit 510 described with reference to fig. 5. ECC decoders 620 and 630 and CRC check unit 680 may constitute one forward error correction channel, and ECC decoders 640 and 650 and CRC check unit 690 may constitute another forward error correction channel, where the forward error correction channel may correspond to, for example, the forward error correction channel described with reference to fig. 5.

The FEC structure described with reference to fig. 6 enables 256B Flit data to support 2-shot 128B data transmission, with only two 128B sub-packets. 256B data may be transferred in two times, which may greatly reduce the time for data preparation. For example, the FEC structure described with reference to fig. 3 requires 4 periods to prepare 256B data, in contrast to the FEC structure described with reference to fig. 6 which requires only 2 periods to prepare 128B for FEC operations, e.g., ECC and CRC operations to be sent to the ECC decoder and CRC check unit in the corresponding forward error correction channel, without having to wait for 256B data to be read out in its entirety. In this way, the FEC structure according to at least one embodiment of the present disclosure greatly reduces data transmission delay and improves data transmission efficiency.

In addition, in the FEC structure described with reference to FIG. 6, the ECC decoders 620-650 are identical in structure, e.g., a 64B ECC structure may be used. The 128B data transmitted each time may be 122B valid data+2b CRC data+4b FEC, using a 2-line interleaved data structure, and no padding for invalid data is required. In contrast, the FEC structure as described with reference to fig. 3 uses a three-wire interleaving structure in which 2B invalid data needs to be padded in order for the ECC decoder to perform an ECC operation, since 256 is not divisible by 3. In this way, the FEC structure described with reference to fig. 6 can simplify the hardware structure. In addition, the effective data is improved from 242B to 244B, the effective data transmission rate is 95.31%, and the data transmission rate is effectively improved. For example, the FEC structure described with reference to fig. 6 may increase the data transmission rate by 0.8% compared to the FEC structure described with reference to fig. 3.

The manner in which the data structure for two strokes 128B (e.g., high 128B and low 128B) of data are interleaved in two lines, respectively, is described below in connection with fig. 7. Fig. 7 illustrates a schematic diagram of a two-wire interleaved data structure in accordance with at least one embodiment of the present disclosure.

Referring to fig. 7, for example, for low 128B (bytes 0 through 127), an exemplary two-line interleaving is:

byte 0 of n Flit maps to a first set of ECC words, byte offset 0;

byte 1 of n Flit maps to a second set of ECC words, with a byte offset of 0;

byte 2 of n Flit maps to a first set of ECC words, byte offset 1;

byte 3 of n Flit maps to a second set of ECC words, byte offset 1;

byte 4 of n Flit maps to a first set of ECC words, byte offset 2;

byte 5 of n Flit maps to a second set of ECC words, byte offset 2;

n……

bytes 122 of n Flit map to a first set of ECC words, byte offset 61;

bytes 123 of n Flit map to a second set of ECC words, byte offset 61;

bytes 124 and 126 of n Flit map to a first set of ECC words, byte offset 62;

bytes 125 and 127 of n Flit map to the second set of ECC words, byte offset 63.

Namely:

B0/B2/B4/B6/… … are the same set of ECC words, e.g., referred to as ECC0 words;

B1/B3/B5/B7/… … are the same set of ECC words, e.g., referred to as ECC1 words.

In fig. 7, bytes having the same gradation are mapped to the same group and thus organized to the same ECC word.

As described with reference to fig. 6, the ECC0 word and the ECC1 word may be subjected to ECC operations by an ECC decoder, respectively. For example, ECC0 and ECC1 for 128B on the upper side of FIG. 6 may be performed by ECC decoders 620 and 630, respectively, and ECC0 and ECC1 for 128B on the lower side of FIG. 6 may be performed by ECC decoders 620 and 630, respectively.

Referring back to fig. 6, there are shown ECC decoders 420-450, each having a 64B ECC structure (i.e., corresponding to a 64B byte number of ECC words), based on the two-line interleaved data structure described above, 1B data, for example, can be corrected at a time. In performing an ECC operation on 128B data, two ECC decoders may be used (e.g., ECC decoders 620 and 630 may be used for 128B on the upper side of fig. 6, or ECC decoders 640 and 650 may be used for 128B on the lower side of fig. 6), and both ECC decoders may output valid data (e.g., dlp+tlp) of 122B while outputting 4B FEC data.

The two ECC decoders will send 124B data (including 122B valid data and 2B, i.e., 16 bits of CRC data) to the corresponding CRC check unit (e.g., ECC decoders 620 and 630 output the data to CRC check unit 680 and ECC decoders 640 and 650 output the data to CRC check unit 690). The CRC check units 680 and 690 may have the same structure.

In CRC check units 380 and 390, the CRC value may be calculated again for the valid data of 122B, respectively, and checked with the FEC corrected 16-bit CRC value to output Flit retry 0/Flit retry 1, respectively, to inform the software system whether this data needs to be reread. For example, for each of Flit retry 0/Flit retry 1, the pen data may be indicated as having integrity by a first value and not requiring re-reading of the pen data, and the pen data portion may be indicated as having integrity by a second value and requiring re-reading of the pen data.

One or more beneficial effects may be achieved using the FEC structure described with reference to fig. 6.

For example, using the FEC structure described with reference to fig. 6, the data transmission delay time can be reduced, the data preparation time can be reduced, for example, by approximately 50%.

For example, using the FEC structure described with reference to fig. 6, the ECC/FEC operation unit drops from the previous 86B word to the 64B word, the matrix used in, for example, the RS algorithm will be smaller, the number of algorithm logic stages will be smaller (about 86-64=22, 22/86 about 25%) and the performance will be better.

For example, using the FEC structure described with reference to fig. 6, the effective data is increased from 242 to 244B data, the effective data transmission rate is 95.31%, and the data transmission rate is effectively increased, for example, by 0.8%.

For example, using the FEC structure described with reference to fig. 6, 256B would be able to correct 4B data in terms of error correction capability, improving reliability by 33.33% compared to 3B data that can be corrected with the FEC structure described with reference to fig. 3.

In an additional aspect of the FEC structure described with reference to fig. 6, more FEC encoded data is used (from previous 6B to 8B), while the CRC uses a smaller number (from previous 8B to current 4B), the principle being that the CRC has only the function of error detection, whereas the FEC encoding uses the RS algorithm, not only the function of error detection, but also the function of error correction. The FEC code is not weaker than the CRC code in terms of error detection. Thus, the crc+fec encoded data is adjusted, and there are advantages in terms of CRC encoding to data integrity, which must be completely correct in advance. If there is an error rate between the valid data and the CRC data, the integrity is not guaranteed. And FEC coding is more advantageous. The FEC structure described with reference to fig. 6 can thus be extended, for example, by adding more FEC codes, increasing error correction capability, and reducing the impact of bit error rate on the system.

At least some embodiments of the present disclosure also provide an electronic device. Fig. 8 shows a schematic diagram of an electronic device 800 in accordance with at least one embodiment of the present disclosure.

As shown in fig. 8, the electronic device 800 includes one or more processors 810 and memory 820. Memory 820 includes one or more computer program modules 821. One or more computer program modules 821 are stored in memory 820 and configured to be executed by processor 810, the one or more computer program modules 821 include instructions for performing forward error correction method 400 and additional aspects thereof in accordance with at least one embodiment of the present disclosure, which when executed by processor 810, can perform one or more steps of forward error correction method 400 and additional aspects thereof in accordance with at least one embodiment of the present disclosure. The memory 820 and the processor 810 may be interconnected by a bus system and/or other forms of connection mechanisms (not shown). For example, the bus may be a peripheral component interconnect standard (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus may be classified as an address bus, a data bus, a control bus, or the like.

By way of example, the processor 810 may be a Central Processing Unit (CPU), a Digital Signal Processor (DSP), or other form of processing unit having data processing and/or program execution capabilities, such as a Field Programmable Gate Array (FPGA), or the like; for example, the Central Processing Unit (CPU) may be a RISC-V architecture or other suitable type of architecture, etc. The processor 810 may be a general purpose processor or a special purpose processor that may control other components in the electronic device 800 to perform the desired functions.

By way of example, memory 820 may comprise any combination of one or more computer program products that may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. Volatile memory can include, for example, random Access Memory (RAM) and/or cache memory (cache) and the like. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, and the like. One or more computer program modules 821 may be stored on the computer-readable storage medium, and the processor 810 may execute the one or more computer program modules 821 to implement the various functions of the electronic device 800. The computer program modules include a plurality of computer-executable instructions. Various applications and various data, as well as various data used and/or generated by the applications, etc., may also be stored in the computer readable storage medium.

For example, electronic device 800 may also include input devices such as a touch screen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, and the like; including output devices such as liquid crystal displays, speakers, vibrators, etc.; including storage devices such as magnetic tape, hard disk (HDD or SDD); for example, communication devices such as LAN cards, modems and the like may also be included. The communication apparatus may allow the electronic apparatus 800 to perform wireless or wired communication with other devices to exchange data, performing communication processing via a network such as the internet. The drive is connected to the I/O interface as needed. A removable storage medium such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is mounted on the drive as needed so that a computer program read therefrom is installed into the storage device as needed.

For example, the electronic device 800 may further include a peripheral interface (not shown), and the like. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning (lighting) interface, etc. The communication means may communicate with networks and other devices by way of wireless communication, such as the internet, intranets and/or wireless networks such as cellular telephone networks, wireless Local Area Networks (LANs) and/or Metropolitan Area Networks (MANs). The wireless communication may use any of a variety of communication standards, protocols, and technologies including, but not limited to, global System for Mobile communications (GSM), enhanced Data GSM Environment (EDGE), wideband code division multiple Access (W-CDMA), code Division Multiple Access (CDMA), time Division Multiple Access (TDMA), bluetooth, wi-Fi (e.g., based on the IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and/or IEEE 802.11n standards), voice over Internet protocol (VoIP), wi-MAX, protocols for email, instant messaging, and/or Short Message Service (SMS), or any other suitable communication protocol.

The electronic device 800 may be, for example, a system on a chip (SOC) or a device including the SOC, for example, any device such as a mobile phone, a tablet computer, a notebook computer, an electronic book, a game console, a television, a digital photo frame, a navigator, a home appliance, a communication base station, an industrial controller, a server, or any combination of data processing devices and hardware, which is not limited in the embodiments of the present disclosure. The specific functions and technical effects of the electronic device 800 can be referred to the above description of the forward error correction method 400 and the additional aspects thereof according to at least one embodiment of the present disclosure, and are not repeated herein.

Fig. 9 illustrates a schematic diagram of a non-transitory readable storage medium 900 in accordance with at least one embodiment of the present disclosure.

As shown in fig. 9, a non-transitory readable storage medium 900 has stored thereon computer instructions 910 that when executed by a processor perform one or more steps of the forward error correction method 400 and additional aspects thereof described above.

Illustratively, the non-transitory readable storage medium 900 may be any combination of one or more computer readable storage media, e.g., a computer readable storage medium containing program code for receiving data packets transmitted over a system bus. For another example, a computer-readable storage medium contains program code for transmitting a subpacket to one of n forward error correction channels in response to receiving a subpacket of the n subpackets. For another example, a computer readable storage medium contains program code for performing a forward error correction operation on a subpacket in a forward error correction channel.

Illustratively, when the program code is read by a computer, the computer can execute the program code stored in the computer storage medium to perform one or more steps of, for example, the forward error correction method 400 and additional aspects thereof in accordance with at least one embodiment of the present disclosure.

By way of example, the non-transitory readable storage medium may include a memory card of a smart phone, a memory component of a tablet computer, a hard disk of a personal computer, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), flash memory, and other non-transitory readable storage media or any combination thereof.

At least some embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, so long as identical and similar parts between the various embodiments are mutually referred to.

It is noted that in this document, relational terms such as first, second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may further include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.

For the purposes of this disclosure, the following points are also noted:

(1) The drawings of the embodiments of the present disclosure relate only to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

(2) The embodiments of the present disclosure and features in the embodiments may be combined with each other to arrive at a new embodiment without conflict.

The foregoing is merely exemplary embodiments of the present disclosure and is not intended to limit the scope of the disclosure, which is defined by the appended claims.

Claims

1. A forward error correction method, comprising:

receiving a data packet transmitted on a system bus, wherein the data packet comprises n sub-data packets, n is a positive integer and n is more than or equal to 2; and is also provided with

Transmitting one of the n sub-packets to one of n forward error correction channels in response to receiving the one sub-packet, wherein the n sub-packets are in one-to-one correspondence with the n forward error correction channels; and

and performing forward error correction operation on the sub-data packet in the forward error correction channel.

2. The forward error correction method of claim 1, wherein performing forward error correction operations on the one subpacket at the one forward error correction channel comprises:

Performing error checking and correcting operation on the sub-data packet, and obtaining a result of the error checking and correcting operation; and

and performing Cyclic Redundancy Check (CRC) code checking on the result of the error checking and correcting operation.

3. The forward error correction method of claim 2, wherein transmitting the one subpacket to one of n forward error correction channels comprises:

and transmitting the one sub-data packet to m error checking and correcting decoders of the one forward error correction channel by using m-line interleaving, so that the byte number of the one sub-data packet is equal to the sum of the byte numbers of error checking and correcting words corresponding to the m error checking and correcting decoders, wherein m is a positive integer and m is more than or equal to 1.

4. The forward error correction method of claim 3, wherein m = 2, the m error check correction decoders include a first error check correction decoder and a second error check correction decoder, the size of the one sub-packet is divisible by 2, and,

transmitting the one subpacket to the m error checking and correcting decoders using m-line interleaving, comprising:

the one subpacket is transmitted to the first and second error check correction decoders using a two-wire interlace.

5. The forward error correction method of claim 4, wherein transmitting the one sub-packet to the first and second error check correction decoders using two-wire interleaving comprises:

mapping odd bytes of the one sub-packet to a first error check correction word; and

the even bytes of the one sub-packet are mapped to a second error check correction word.

6. The forward error correction method according to claim 4, wherein the system bus conforms to a peripheral component interconnect express protocol, n=2, and the number of bytes of the one sub data is 128 bytes,

transmitting the one subpacket to the first and second error check correction decoders using a two-wire interlace, comprising:

n maps byte 0 of the one sub-packet to a first set of error check correction words,

byte offset 0;

n maps byte 1 of the one sub-packet to a second set of error check correction words,

byte offset is 0;

n maps byte 2 of the one sub-packet to a first set of error check correction words,

byte offset 1;

n maps byte 3 of the one sub-packet to a second set of error check correction words,

Byte offset 1;

n maps byte 4 of the one sub-packet to a first set of error check correction words,

byte offset 2;

n maps byte 5 of the one sub-packet to a second set of error check correction words,

byte offset 2;

n……

n maps bytes 122 of the one sub-packet to a first set of error check correction words, byte offset 61;

n maps the byte 123 of the one sub-packet to a second set of error check correction words, byte offset 61;

n maps bytes 124 and 126 of the one sub-packet to a first set of error check correction words, byte offset 62;

n maps bytes 125 and 127 of the one sub-packet to a second set of error check correction words, byte offset 63.

7. The forward error correction method of claim 6, wherein the peripheral component interconnect express protocol is a peripheral component interconnect express 6.0 version or a version compatible with the peripheral component interconnect express 6.0 version.

8. The forward error correction method of claim 6, wherein the byte count of one sub data includes 122 bytes of valid data, 2 bytes of cyclic redundancy check code data, and 4 bytes of forward error correction data, the byte counts of the corresponding error check correction words of the first error check correction decoder and the second error check correction decoder are 64 bytes, and,

Performing an error checking and correcting operation on the sub-data packet, and obtaining a result of the error checking and correcting operation, including:

and performing error check correction operation on the first group of error check correction words and the second group of error check correction words by the first error check correction decoder and the second error check correction decoder respectively to obtain 122 bytes of effective data after error check correction and 2 bytes of cyclic redundancy check code data after error check correction.

9. The forward error correction method of claim 8, wherein performing a cyclic redundancy check (crc) check on the result of the error-checking and correcting operation comprises:

performing cyclic redundancy check code check on the 122-byte error check corrected effective data by a single cyclic redundancy check code check unit to obtain 2-byte cyclic redundancy check code checked cyclic redundancy check code data;

comparing the cyclic redundancy check code data after 2 bytes of cyclic redundancy check code verification with the cyclic redundancy check code data after 2 bytes of error checking and correcting; and

outputting a first value to indicate that the one sub-packet has integrity in response to the 2-byte crc check and the 2-byte error check corrected crc data being inconsistent; or alternatively

And outputting a second value to indicate that the one sub-packet has no integrity in response to the 2-byte crc after the crc check and the 2-byte error check corrected crc data being identical.

10. The forward error correction method of claim 8, wherein performing, by the first and second error check correction decoders, error check correction operations on the first and second sets of error check correction words, respectively, comprises:

performing, by the first and second error check correction decoders, error check correction operations on the first and second sets of error check correction words, respectively, using a reed-solomon code algorithm.

11. The forward error correction method of any of claims 1-10, wherein the number of bytes of the n subpackets is equal and the n forward error correction channels are identical in structure.

12. A forward error correction device comprises a transmission unit and n forward error correction channels, wherein n is a positive integer and is more than or equal to 2,

the transmission unit is configured to:

Receiving a data packet transmitted on a system bus, wherein the data packet comprises n sub-data packets; and is also provided with

Transmitting one of the n sub-packets to one of the n forward error correction channels in response to receiving the one sub-packet, wherein the n sub-packets are in one-to-one correspondence with the n forward error correction channels; and is also provided with

The one forward error correction channel is configured to:

and performing forward error correction operation on the one sub-data packet.

13. The forward error correction apparatus of claim 12, wherein said one forward error correction channel comprises a set of error checking correction decoders and a set of cyclic redundancy check code check cells,

the error checking and correcting decoder group is configured to execute error checking and correcting operation on the sub-data packet and acquire the result of the error checking and correcting operation; and is also provided with

The set of cyclic redundancy check code check units is configured to perform cyclic redundancy check code check on a result of the error check correction operation.

14. The forward error correction device of claim 13, wherein the set of error check correction decoders comprises m error check correction decoders, m being a positive integer and m being ≡1, the transmission unit being further configured to:

And transmitting the one sub-data packet to the m error check correction decoders by using m-line interleaving, so that the byte number of the one sub-data packet is equal to the sum of the byte numbers of the error check correction words corresponding to the m error check correction decoders.

15. The forward error correction apparatus of claim 14, wherein m = 2, the m error check correction decoders include a first error check correction decoder and a second error check correction decoder, the size of the one sub-packet is divisible by 2, the transmission unit is further configured to:

16. The forward error correction apparatus of claim 15, wherein the system bus conforms to a peripheral component interconnect express protocol, n = 2, and the number of bytes of the one sub-data is 128 bytes, the transmission unit further configured to:

byte offset 0;

Byte offset is 0;

byte offset 1;

byte offset 2;

n……

17. The forward error correction apparatus of claim 16, wherein the byte count of one sub data includes 122 bytes of valid data, 2 bytes of cyclic redundancy check code data, and 4 bytes of forward error correction data, the byte counts of the corresponding error check correction words of the first error check correction decoder and the second error check correction decoder are 64 bytes, and the first error check correction decoder and the second error check correction decoder are configured to:

And performing error checking and correcting operations on the first group of error checking and correcting words and the second group of error checking and correcting words respectively to obtain 122 bytes of effective data after error checking and correcting and 2 bytes of cyclic redundancy check code data after error checking and correcting.

18. The forward error correction device of claim 17, wherein the set of cyclic redundancy check code check units comprises a single cyclic redundancy check code check unit configured to:

performing Cyclic Redundancy Check (CRC) code checking on the effective data after error checking and correcting of 122 bytes to obtain cyclic redundancy check code data after CRC code checking of 2 bytes;

19. An electronic device, comprising:

one or more processors;

a memory including one or more computer program modules;

wherein the one or more computer program modules are stored in the memory and configured to be executed by the one or more processors to implement the forward error correction method of any of claims 1-11.

20. A non-transitory readable storage medium having stored thereon computer-executable instructions,

wherein the computer executable instructions, when executed by a processor, implement the forward error correction method according to any of claims 1-11.