CN117294298A - Buffer circuit and driving device - Google Patents
Buffer circuit and driving device Download PDFInfo
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- CN117294298A CN117294298A CN202311207836.4A CN202311207836A CN117294298A CN 117294298 A CN117294298 A CN 117294298A CN 202311207836 A CN202311207836 A CN 202311207836A CN 117294298 A CN117294298 A CN 117294298A
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- 239000000872 buffer Substances 0.000 title claims abstract description 41
- 230000007423 decrease Effects 0.000 claims description 17
- 239000003990 capacitor Substances 0.000 claims description 15
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 238000000034 method Methods 0.000 description 5
- 238000013459 approach Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000009123 feedback regulation Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00307—Modifications for increasing the reliability for protection in bipolar transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017545—Coupling arrangements; Impedance matching circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
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- Amplifiers (AREA)
Abstract
The invention discloses a buffer circuit and a driving device, wherein the buffer circuit comprises a first operational amplifier tube, a reference voltage source is coupled to a non-inverting input end of the first operational amplifier tube, and a circuit output end of the first operational amplifier tube is coupled to an inverting input end of the first operational amplifier tube; the positive phase input end of the second operational amplifier is coupled with a reference voltage source, the output end of the second operational amplifier is coupled with the grid electrode of the first transistor, the first transistor is connected between the power end and the output end of the first operational amplifier in series, the first reverse phase input end of the second operational amplifier is coupled with the output end of the circuit, and the second reverse phase input end of the second operational amplifier is coupled with the output end of the second operational amplifier. The voltage at the output end of the buffer circuit can be quickly recovered after the charge is extracted, so that the working precision of the circuit output end equipment is ensured.
Description
Technical Field
The present invention relates to the field of buffer technologies, and in particular, to a buffer circuit and a driving device.
Background
In the fields of signal chains, sensors and the like, voltage buffers can be used for driving modules such as digital-to-analog converters and the like to work, and the digital-to-analog converters often affect the overall performance of a chip. Correspondingly, the voltage buffer circuit also becomes one of the main factors limiting the performance of the digital-to-analog converter.
In the prior art, during the conversion of an analog signal, a digital-to-analog converter typically extracts charges from a buffer circuit, resulting in a drop in the output level of the buffer circuit. In order to ensure the conversion accuracy of the digital-to-analog converter, the level of the output end of the buffer circuit needs to be established to a corresponding height, so that the buffer circuit needs to establish the output voltage to the accuracy required by the digital-to-analog converter in a specified time to ensure the overall performance requirement of the digital-to-analog converter.
Disclosure of Invention
One of the objectives of the present invention is to provide a buffer circuit, which solves the technical problem that in the prior art, the voltage of the output terminal of a voltage buffer is reduced due to charge extraction, resulting in poor overall performance of the device.
One of the objects of the present invention is to provide a driving device.
To achieve one of the above objects, an embodiment of the present invention provides a buffer circuit including: the non-inverting input end of the first operational amplifier tube is coupled with a reference voltage source, and the output end of the circuit is coupled to the inverting input end of the first operational amplifier tube; the positive input end of the second operational amplifier is coupled with a reference voltage source, the output end of the second operational amplifier is coupled with the grid electrode of the first transistor, the first transistor is connected in series between the power supply end and the output end of the first operational amplifier, the first negative input end of the second operational amplifier is coupled with the output end of the circuit, and the second negative input end of the second operational amplifier is coupled with the output end of the second operational amplifier; the second op-amp is configured to: when the voltage of the output end of the circuit is reduced, the voltage of the output end of the second operational amplifier is increased to control the first transistor to increase the charging current of the output end of the circuit.
In order to achieve one of the above objects, an embodiment of the present invention provides a driving device including the buffer circuit described in the above embodiment.
Compared with the prior art, the invention has the following beneficial effects: the second operational amplifier is configured on the basis of the first operational amplifier, the voltage output by the circuit output end can react rapidly when the voltage drops, the grid voltage of the first transistor is controlled to rise, the charging current of the first transistor to the circuit output end is increased through the conduction of the first transistor, the voltage of the circuit output end is lifted, and the voltage of the buffer circuit output end can recover the voltage rapidly after the charge is extracted, so that the working precision of the circuit output end equipment is ensured.
Drawings
Fig. 1 is a circuit configuration diagram of a buffer circuit of the present invention.
Fig. 2 is a circuit configuration diagram of a second op-amp in an embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to specific embodiments shown in the drawings. These embodiments are not intended to limit the invention and structural, methodological, or functional modifications of these embodiments that may be made by one of ordinary skill in the art are included within the scope of the invention.
Referring to fig. 1, in an embodiment of the present invention, a buffer circuit is provided, where the buffer circuit may be coupled to a digital-to-analog converter ADC and configured to provide a voltage to the digital-to-analog converter ADC to ensure operation of the digital-to-analog converter ADC.
The buffer circuit comprises a first operational amplifier A1 and two operational amplifiers A2, wherein the non-inverting input end of the first operational amplifier A1 is coupled with a reference voltage source, and the output end of the buffer circuit is coupled to the inverting input end of the first operational amplifier A1.
The non-inverting input end of the second operational amplifier A2 is coupled with a reference voltage source, the output end is coupled with the grid electrode of the first transistor M1, the first transistor M1 is connected in series between the power end and the output end of the first operational amplifier A1, the first inverting input end of the second operational amplifier A2 is coupled with the output end of the circuit, and the second inverting input end of the second operational amplifier A2 is coupled with the output end of the second operational amplifier A1.
The second operational amplifier A2 is configured to: when the voltage of the output end of the circuit is reduced, the voltage of the output end of the second operational amplifier A2 is increased to control the first transistor M1 to increase the output current of the output end of the circuit.
In this way, the second operational amplifier A2 is configured on the basis of the first operational amplifier A1, so that the voltage output by the output end of the circuit can be quickly reacted when the voltage drops, and the gate voltage of the first transistor M1 is controlled to rise; the first transistor M1 is conducted so as to increase the charging current of the first transistor M1 to the circuit output end, so that the voltage of the circuit output end is raised, and the voltage of the buffer circuit output end can be quickly recovered after the charges are extracted, so that the working precision of the circuit output end equipment is ensured.
The first transistor M1 may be an N-type transistor.
The drain of the first transistor M1 is coupled to a power source, and the source is coupled to the output terminal of the circuit and outputs the output voltage Vout of the circuit. The charging current is expressed as a current output when the first transistor M1 is turned on according to the magnitude of the gate potential.
In an embodiment of the present invention, the second op-amp A2 is further configured to: the first transistor M1 is turned off when the gate potential of the first transistor M1 is equal to the reference voltage Vref of the reference voltage source.
The second operational amplifier A2 controls the first transistor M1 to be charged to enhance the slew of the circuit, and meanwhile, the second operational amplifier A2 may control the first transistor M1 to be turned off when the gate potential of the first transistor M1 is equal to the reference voltage Vref of the reference voltage source, that is, when the output voltage Vout of the output end of the circuit approaches the reference voltage Vref, so that the slew enhancing mode is disabled.
The further rise of the output voltage Vout is controlled based on the gain and bandwidth required by the first op-amp A1 itself to provide the circuit.
The combination of the first operational amplifier A1 and the second operational amplifier A2 not only accelerates the rising speed of the voltage of the output end of the circuit, but also greatly reduces the power consumption and the cost of the control circuit.
The reference voltage Vref of the reference voltage source can be manually adjusted according to the requirement, and the adjustment of the reference voltage Vref of the reference voltage source can be set according to the requirement of the ADC, and can also be comprehensively considered by referring to the parameters of other devices.
The roll enhancement mode exit operation is represented as: the first transistor M1 is turned off and the second op-amp A2 exits.
Next, the output voltage Vout at the circuit output is controlled by the first op-amp A1. The output voltage Vout is controlled from being approximated to the reference voltage Vref to be equal to the reference voltage Vref according to the gain and bandwidth of the first operational amplifier A1 itself.
In one embodiment of the present invention, the output terminal of the first op-amp A1 is coupled to the inverting input terminal of the first op-amp A1.
In this way, the output voltage Vout at the output of the circuit can be controlled to be equal to the reference voltage Vref.
The output end of the first operational amplifier A1 is coupled to the output end of the circuit, and the output end of the circuit is coupled to the inverting input end of the first operational amplifier A1 to form feedback, so that the output voltage Vout of the output end of the first operational amplifier A1 is dynamically equal to the reference voltage Vref of the non-inverting input end of the first operational amplifier A1.
In an embodiment, referring to fig. 2, the second operational amplifier A2 includes a second transistor M2, the second transistor M2 is connected in series between the first current source and the reference ground, and the gate of the first transistor M1 is coupled to the source of the second transistor M2.
The second transistor M2 is configured to: when the output voltage Vout of the circuit output terminal decreases, the gate potential increases in response to the decrease of the output voltage Vout of the circuit output terminal to pull up the gate potential of the first transistor M1.
In this way, the rise or fall of the output voltage Vout can be reflected as the conduction degree of the second transistor M2, so that the second transistor M2 is turned on less when the output voltage Vout decreases and the output current decreases, so that the gate potential of the first transistor M1 is raised to control the first transistor M1 to charge the output voltage Vout to achieve the rise of the output voltage Vout.
The second transistor M2 may be a P-type transistor.
The "output voltage Vout responsive to the output terminal of the circuit" may be understood as that the output voltage Vout is coupled to the gate of the second transistor M2, and the magnitude of the output voltage Vout may control the degree of conduction of the second transistor M2, thereby indirectly controlling the output current of the second transistor M2.
In an embodiment, the second operational amplifier A2 includes a ninth transistor M9, the ninth transistor M9 is connected in series between the first current source and the reference ground, the gate of the ninth transistor M9 is coupled to the output voltage Vout of the output terminal of the circuit, the gate of the first transistor M1 is coupled to the drain of the ninth transistor M9, and the gate of the ninth transistor M9 is coupled to a control signal, and the control signal is used to turn on the ninth transistor M9 to output the current of the first current source.
In this way, the rise or fall of the output voltage Vout can be reflected as the turn-on degree of the ninth transistor M9, so that the ninth transistor M9 is turned on more and the output current is larger when the output voltage Vout decreases, so that the gate potential of the first transistor M1 is raised to control the first transistor M1 to charge the output voltage Vout to achieve the rise of the output voltage Vout.
The ninth transistor M9 may be a P-type transistor.
The control signal may be from a constant current source or a constant voltage source external to the circuit.
In a preferred embodiment of the present invention, referring to fig. 2, a second transistor M2 and a ninth transistor M9 are disposed in series between the first current source and the reference ground. The gate of the first transistor M1 is coupled to the source of the second transistor M2, and the gate of the ninth transistor M9 is coupled to a control signal for turning on the ninth transistor M9 to output the current of the first current source. The drain of the second transistor M2 is coupled to the source of the ninth transistor M9, the drain of the ninth transistor M9 is coupled to the reference ground, and the source of the second transistor M2 is coupled to the first current source.
In this way, the buffer circuit reduces the output current through the second transistor M2, i.e. discharges less to the gate potential of the first transistor M1 and pulls up the gate potential of the first transistor M1; the buffer circuit increases the output current by the ninth transistor M9, that is, charges the gate potential of the first transistor M1 more to pull up the gate potential of the first transistor M1.
The second transistor M2 and the ninth transistor M9 cooperate to enable the gate potential of the first transistor M1 to rise more rapidly, so as to reduce the response time of the output current of the first transistor M1 to increase the output voltage Vout, and ensure that the buffer can recover the output voltage Vout to supply the digital-to-analog conversion device ADC more rapidly.
The source of the ninth transistor M9 is coupled to the first current source, the drain of the ninth transistor M9 is coupled to the source of the second transistor M2, the drain of the second transistor M2 is coupled to the reference ground, the gate of the first transistor M1 is coupled between the ninth transistor M9 and the second transistor M2, the ninth transistor M9 is configured to charge the gate of the first transistor M1, and the second transistor M2 is configured to discharge the gate of the first transistor M1. The charging and the discharging are characterized by an output current.
In an embodiment of the present invention, referring to fig. 2, the second operational amplifier A2 further includes a third transistor M3, the third transistor M3 is connected in series between the second current source and the gate of the second transistor M2, and the gate of the third transistor M3 is coupled to the output voltage Vout.
The circuit receives the dynamically-changed output voltage Vout by using the third transistor M3, so that the magnitude of the output current is controlled to control the conduction degree of the second transistor M2, and the conduction degree of the first transistor M1 is indirectly controlled, thereby forming feedback regulation of the output voltage Vout, ensuring that the output voltage Vout can be clamped at a certain height and improving the reliability of the circuit.
Such as: when the output voltage Vout decreases, the voltage between the gate and the source of the third transistor M3 increases, and the output current increases, so that the gate potential of the second transistor M2 increases, and the voltage between the gate and the source of the second transistor M2 decreases, and the decrease in the output current, that is, the discharge to the first transistor M1, is controlled to be smaller.
The third transistor M3 may be a P-type transistor.
The source of the third transistor M3 is coupled to the second current source, the drain of the third transistor M3 is coupled to the ground and the gate of the second transistor M2 is coupled to the drain of the third transistor M3, and the second transistor M2 is configured to receive the output current of the third transistor M3, thereby controlling the turn-on degree of the first transistor M1 according to the magnitude of the output current of the third transistor M3.
In an embodiment of the present invention, the second operational amplifier A2 further includes a fourth transistor M4, the fourth transistor M4 is connected in series between the second current source and the reference ground, and a gate of the fourth transistor M4 is coupled to a control signal, and the control signal is used to turn on the fourth transistor M4 to output the current of the second current source.
The second operational amplifier A2 further comprises a capacitor C1, a first plate of the capacitor C1 is coupled to the fourth transistor M4, and a second plate of the capacitor C1 is coupled to the output voltage Vout.
The decrease in the output voltage Vout increases the voltage drop across the capacitor C1 and is coupled to the fourth transistor M4 such that the voltage between the gate and the source of the fourth transistor M4 increases to control the fourth transistor M4 to increase the output current, such that the current flowing through the third transistor M3 increases to more rapidly control the second transistor M2, indirectly reducing the response time, resulting in higher reliability of the overall circuit.
The fourth transistor M4 may be a P-type transistor.
The control signal may be from a constant current source or a constant voltage source external to the circuit.
In an embodiment, the second operational amplifier A2 further includes a capacitor C1, a first plate of the capacitor C1 is coupled to the gate of the ninth transistor M9, and a second plate of the capacitor C1 is coupled to the output voltage Vout.
The decrease of the output voltage Vout increases the voltage drop of the capacitor C1 and the voltage between the gate and the source coupled to the ninth transistor M9 increases, so as to control the output current of the ninth transistor M9 to increase, so that the output voltage Vout can rise more quickly, indirectly reducing the response time of the overall circuit, and improving the reliability of the overall circuit.
In a preferred embodiment, referring to fig. 2, the second operational amplifier A2 further includes a capacitor C1, a first plate of the capacitor C1 is coupled to the gates of the fourth transistor M4 and the ninth transistor M9, and a second plate of the capacitor C1 is coupled to the output voltage Vout.
By multiplexing the capacitor C1, the control of the second transistor M2 by the third transistor M3 is made faster, and the ninth transistor M9 is also made to respond faster to output current.
In a preferred embodiment, the fourth transistor M4 may be used in combination with the second transistor M2, the third transistor M3; such as: a second transistor M2 is connected in series between the first current source and the reference ground, and the gate of the first transistor M1 is coupled to the source of the second transistor M2; the source of the fourth transistor M4 is coupled to the second current source, the drain is coupled to the source of the third transistor M3, and the drain of the third transistor M3 is coupled to the gate of the second transistor M2.
The second transistor M2 is configured to: when the output voltage Vout of the circuit output terminal decreases, the gate potential increases in response to the decrease of the output voltage Vout of the circuit output terminal to pull up the gate potential of the first transistor M1.
Thus, the current output from the fourth transistor M4 can be distributed to the third transistor M3 to control the gate potential of the second transistor M2.
In an embodiment of the present invention, referring to fig. 2, the second operational amplifier A2 further includes a fifth transistor M5 and a sixth transistor M6, wherein sources of the fifth transistor M5 and the sixth transistor M6 are respectively coupled to the second current source, a gate of the sixth transistor M6 is coupled to the gate of the first transistor M1, a gate of the fifth transistor M5 is coupled to the reference voltage source, a drain of the fifth transistor M5 is coupled to the reference ground, and a drain of the sixth transistor M6 is coupled to the gate of the second transistor M2.
The gate of the second transistor M2 is coupled to ground and forms a first pull-down current.
The fifth transistor M5 is configured to: the gate potential of the second transistor M2 is pulled down when the first pull-down current is coupled as the output current of the fifth transistor M5, reducing the gate potential of the first transistor M1 to turn off the first transistor M1.
In this way, in the process that the output currents of the fifth transistor M5 and the sixth transistor M6 gradually decrease to gradually increase the output voltage Vout, the gate of the sixth transistor M6 receives the gate potential of the first transistor M1 to form a feedback loop, so that the gate potential of the first transistor M1 can be controlled to be pulled down in time, and the output voltage Vout output by the first transistor M1 is ensured to be turned off in time when reaching a certain height, so as to control the power consumption and the cost of the second operational amplifier A2.
The drains of the sixth transistor M6 and the third transistor M3 are connected in parallel and converged at one point, and the drain of the fifth transistor M5 outputs current to the reference ground; the gate of the second transistor M2 is coupled to the drains of the sixth transistor M6 and the third transistor M3 and coupled between the fifth transistor M5 and the reference ground to receive the output current of the sixth transistor M6 and the third transistor M3 or the output current of the fifth transistor M5.
The fifth transistor M5 may be a P-type transistor, and the sixth transistor M6 may be a P-type transistor.
The "gate of the second transistor M2 is coupled to the ground and forms a first pull-down current" can be understood as: the first pull-down current is formed from the output currents of the sixth transistor M6 and the third transistor M3 and the output current of the fifth transistor M5.
"pulling down the gate potential of the second transistor M2 when the first pull-down current is coupled as the output current of the fifth transistor M5" can be understood as: when the output current of the fifth transistor M5 is greater than the sum of the output currents of the sixth transistor M6 and the third transistor M3, the fifth transistor M5 pulls down the gate potential of the second transistor M2, and the turn-on degree of the second transistor M2 decreases so as to decrease the gate potential of the first transistor M1.
In an embodiment of the present invention, referring to fig. 2, the second operational amplifier A2 further includes a seventh transistor M7 and an eighth transistor M8, the seventh transistor M7 is connected in series between the drain of the fifth transistor M5 and the ground, the eighth transistor M8 is connected in series between the drain of the third transistor M3 and the ground, the gate of the second transistor M2 is coupled to the drain of the eighth transistor M8, the gates of the seventh transistor M7 and the eighth transistor M8 are coupled to each other, and the gate of the seventh transistor M7 is coupled to the drain thereof.
Based on this, the output current of the fifth transistor M5 is coupled and coupled between the gate of the second transistor M2 and the ground by forming a current mirror with the eighth transistor M8 and the seventh transistor M7 so that the gate of the second transistor M2 can be controlled to be pulled down according to the output current of the fifth transistor M5 to turn off the first transistor M1; the second operational amplifier A2 can be timely withdrawn from the swing control, and excessive power consumption is avoided. And, the gate of the seventh transistor M7 is coupled to the drain thereof to form a protection circuit.
In summary, the present invention designs a buffer circuit, which is provided with two operational amplifier tubes, namely a first operational amplifier tube A1 and a second operational amplifier tube A2; the outputs of the first operational amplifier A1 and the second operational amplifier A2 are coupled with the output end of the circuit, when the voltage of the output end of the circuit is reduced, the second operational amplifier A2 is utilized to quickly react to control the first transistor M1 to be conducted more and output more current so as to enable the voltage of the output end of the circuit to be increased, and the first operational amplifier A1 is utilized to carry out later control on the voltage of the output end of the circuit.
In this way, the first operational amplifier A1 and the second operational amplifier A2 can control the voltage of the output end of the circuit in a time-sharing manner to form a large signal establishment process and a small signal establishment process, in the large signal establishment process, the voltage of the output end of the circuit can be raised faster and more efficiently by the voltage swing control of the second operational amplifier A2, so that the voltage is quickly reacted and raised, in the small signal establishment process, the second operational amplifier A2 is withdrawn, and the voltage of the output end of the circuit is finally restored to the required height by the gain and bandwidth control of the first operational amplifier A1. The first operational amplifier A1 and the second operational amplifier A2 cooperate to not only rapidly control the recovery of voltage, but also control the power consumption of the whole circuit to be kept below the economic cost.
Based on the above scheme, the internal circuit of the second operational amplifier A2 is further configured, and one inverting output end of the second operational amplifier A2 is divided into two inverting input ends to form feedback and potential control of the grid electrode of the first transistor M1, wherein the third transistor M3 is adopted to receive the dynamic output voltage Vout, the feedback is adopted to control the opening degree of the first transistor M1 so that the output voltage Vout can dynamically float and change the magnitude, the sixth transistor M6 is adopted to receive the grid potential of the first transistor M1, and a feedback loop is formed by matching with the fifth transistor M5 of the non-inverting input end of the second operational amplifier A2, so that the grid potential of the first transistor M1 can be hung up when the output voltage Vout is excessively high and the output voltage Vout is pulled up to finish large signal establishment, thereby avoiding continuous operation of the second operational amplifier A2 and preventing excessive power consumption and excessive cost; finally, the gain and the bandwidth of the first operational amplifier A1 are utilized to enter a small signal establishment stage to control the output voltage Vout to gradually approach the required voltage Vref.
In an embodiment of the present invention, there is further provided a driving device, where the driving device includes a buffer circuit in any one of the above embodiments, and an output terminal of the buffer circuit is coupled to the digital-to-analog conversion device ADC.
It should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is for clarity only, and that the skilled artisan should recognize that the embodiments may be combined as appropriate to form other embodiments that will be understood by those skilled in the art.
The above list of detailed descriptions is only specific to practical embodiments of the present invention, and they are not intended to limit the scope of the present invention, and all equivalent embodiments or modifications that do not depart from the spirit of the present invention should be included in the scope of the present invention.
Claims (10)
1. A buffer circuit, comprising:
a first operational amplifier (A1) with a non-inverting input coupled to a reference voltage source and a circuit output coupled to an inverting input of the first operational amplifier (A1);
the positive input end of the second operational amplifier tube (A2) is coupled with a reference voltage source, the output end of the second operational amplifier tube is coupled with the grid electrode of the first transistor (M1), the first transistor (M1) is connected between the power end and the output end of the first operational amplifier tube (A1) in series, the first inverting input end of the second operational amplifier tube (A2) is coupled with the output end of the circuit, and the second inverting input end of the second operational amplifier tube (A2) is coupled with the output end of the second operational amplifier tube;
the second operational amplifier (A2) is configured to: when the voltage of the circuit output end is reduced, the voltage of the second operational amplifier (A2) output end is increased to control the first transistor (M1) to increase the output current of the circuit output end.
2. Buffer circuit according to claim 1, characterized in that the second op-amp (A2) is further configured to: the first transistor (M1) is turned off when the gate potential of the first transistor (M1) is equal to the reference voltage (Vref) of the reference voltage source.
3. Buffer circuit according to claim 1, characterized in that the output of the first op-amp (A1) is coupled to the inverting input of the first op-amp (A1).
4. Buffer circuit according to claim 1, characterized in that the second op-amp (A2) comprises a second transistor (M2), the second transistor (M2) being connected in series between a first current source and a reference ground, the gate of the first transistor (M1) being coupled to the source of the second transistor (M2);
the second transistor (M2) is configured to: when the output voltage (Vout) of the circuit output terminal decreases, the gate potential increases in response to the decrease in the output voltage (Vout) of the circuit output terminal to pull up the gate potential of the first transistor (M1).
5. The buffer circuit according to claim 4, characterized in that the second operational amplifier (A2) further comprises a third transistor (M3), the third transistor (M3) being connected in series between a second current source and the gate of the second transistor (M2), the gate of the third transistor (M3) being coupled to the output voltage (Vout).
6. The buffer circuit according to claim 5, wherein the second operational amplifier (A2) further comprises a fifth transistor (M5) and a sixth transistor (M6), the sources of the fifth transistor (M5) and the sixth transistor (M6) being coupled to a second current source, respectively, the gate of the sixth transistor (M6) being coupled to the gate of the first transistor (M1), the gate of the fifth transistor (M5) being coupled to the reference voltage source, the drain of the fifth transistor (M5) being coupled to a reference ground, the drain of the sixth transistor (M6) being coupled to the gate of the second transistor (M2);
a gate of the second transistor (M2) is coupled to ground and forms a first pull-down current;
the fifth transistor (M5) is configured to: -pulling down the gate potential of the second transistor (M2) when the first pull-down current is coupled as the output current of the fifth transistor (M5), -lowering the gate potential of the first transistor (M1) to turn off the first transistor (M1).
7. The buffer circuit according to claim 6, wherein the second operational amplifier (A2) further comprises a seventh transistor (M7) and an eighth transistor (M8), the seventh transistor (M7) being connected in series between the drain of the fifth transistor (M5) and the ground, the eighth transistor (M8) being connected in series between the drain of the third transistor (M3) and the ground and the gate of the second transistor (M2) being coupled to the drain of the eighth transistor (M8), the gates of the seventh transistor (M7) and the eighth transistor (M8) being coupled to each other, the gate of the seventh transistor (M7) being coupled to the drain of itself.
8. The buffer circuit according to claim 1, characterized in that the second operational amplifier (A2) comprises a ninth transistor (M9), the ninth transistor (M9) being connected in series between a first current source and a reference ground, the gate of the ninth transistor (M9) being coupled to the output voltage (Vout) of the circuit output, the gate of the first transistor (M1) being coupled to the drain of the ninth transistor (M9), the gate of the ninth transistor (M9) being coupled to a control signal for turning on the ninth transistor (M9) to output the current of the first current source.
9. The buffer circuit according to claim 8, wherein the second operational amplifier (A2) further comprises a fourth transistor (M4), the fourth transistor (M4) being connected in series between the second current source and a reference ground, the gate of the fourth transistor (M4) being coupled with a control signal for turning on the fourth transistor (M4) to output the current of the second current source;
the second operational amplifier (A2) further comprises a capacitor (C1), a first plate of the capacitor (C1) being coupled to the gate of the fourth transistor (M4) and/or the ninth transistor (M9), a second plate of the capacitor (C1) being coupled to the output voltage (Vout).
10. A driving device comprising a buffer circuit as claimed in any one of claims 1-9, the output of the buffer circuit being coupled to a digital-to-analog conversion device (ADC).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311207836.4A CN117294298A (en) | 2023-09-19 | 2023-09-19 | Buffer circuit and driving device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311207836.4A CN117294298A (en) | 2023-09-19 | 2023-09-19 | Buffer circuit and driving device |
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| CN102946246A (en) * | 2012-11-14 | 2013-02-27 | 东南大学 | Buffer for increasing voltage driving capability |
| JP2017091316A (en) * | 2015-11-12 | 2017-05-25 | 新日本無線株式会社 | Stabilized power supply circuit |
| CN106788393A (en) * | 2017-03-15 | 2017-05-31 | 浙江集速合芯科技有限公司 | A kind of circuit for strengthening the voltage buffer linearity |
| CN106843346A (en) * | 2017-03-30 | 2017-06-13 | 中国电子科技集团公司第二十四研究所 | The reference voltage output circuit of low output impedance |
| CN110831283A (en) * | 2019-11-22 | 2020-02-21 | 深圳市芯飞凌半导体有限公司 | LED driving power supply and controller thereof |
| CN116317996A (en) * | 2023-05-23 | 2023-06-23 | 盈力半导体(上海)有限公司 | Error amplifier and power supply conversion device |
| CN116661546A (en) * | 2023-06-21 | 2023-08-29 | 无锡晟朗微电子有限公司 | Temperature compensation circuit and calibration method thereof |
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| CN101471048A (en) * | 2007-12-27 | 2009-07-01 | 比亚迪股份有限公司 | TFT-LCD driving circuit and LCD device |
| CN102412824A (en) * | 2011-12-02 | 2012-04-11 | 上海贝岭股份有限公司 | Differential reference voltage buffer |
| CN102946246A (en) * | 2012-11-14 | 2013-02-27 | 东南大学 | Buffer for increasing voltage driving capability |
| JP2017091316A (en) * | 2015-11-12 | 2017-05-25 | 新日本無線株式会社 | Stabilized power supply circuit |
| CN106788393A (en) * | 2017-03-15 | 2017-05-31 | 浙江集速合芯科技有限公司 | A kind of circuit for strengthening the voltage buffer linearity |
| CN106843346A (en) * | 2017-03-30 | 2017-06-13 | 中国电子科技集团公司第二十四研究所 | The reference voltage output circuit of low output impedance |
| CN110831283A (en) * | 2019-11-22 | 2020-02-21 | 深圳市芯飞凌半导体有限公司 | LED driving power supply and controller thereof |
| CN116317996A (en) * | 2023-05-23 | 2023-06-23 | 盈力半导体(上海)有限公司 | Error amplifier and power supply conversion device |
| CN116661546A (en) * | 2023-06-21 | 2023-08-29 | 无锡晟朗微电子有限公司 | Temperature compensation circuit and calibration method thereof |
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